KR20080077856A - A method of manufacturing a semiconductor device having a buried gate electrode. - Google Patents

Abstract

A method of manufacturing a semiconductor device having a buried gate electrode is provided. The method includes forming a device isolation film defining an active region in a semiconductor substrate. First and second mask patterns crossing the active region are formed on a substrate having the device isolation layer. The semiconductor substrate and the device isolation layer are etched using the first and second mask patterns as etch masks to form channel trenches crossing the active region. In this case, the second mask pattern is etched to a thickness thinner than the first mask pattern. A gate electrode pattern is formed to fill the channel trench. A buffer mask layer is formed on the substrate having the gate electrode pattern to alleviate the step difference between the first and second mask patterns. The buffer mask layer and the first and second mask patterns are etched back and removed.

Description

Method of fabricating a semiconductor device having a buried gate electrode {Method of fabricating semiconductor device having buried gate electrode}

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2 is a plan view illustrating a method of manufacturing a semiconductor device in accordance with embodiments of the present invention.

3A to 3H are cross-sectional views taken along cut lines I-I 'and II-II' of FIG. 2 to explain a method of manufacturing a semiconductor device according to example embodiments.

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a buried gate electrode.

As the degree of integration of semiconductor memory devices such as DRAM devices increases, the planar area occupied by MOS transistors decreases. As a result, the channel length of the MOS transistor is reduced to generate a short channel effect. In particular, when the short channel effect occurs in an access MOS transistor adopted in the memory cell of the DRAM device, the threshold voltage of the DRAM cell is decreased and the leakage current is increased to degrade the refresh characteristic of the DRAM device.

Accordingly, a recess gate MOS transistor has been introduced as a MOS transistor capable of suppressing a short channel effect by increasing the gate channel length even if the integration degree of the DRAM device is increased. However, even if the recess gate MOS transistor is applied to a semiconductor device such as a DRAM device, the integration of the device may be limited. Contact structures for electrical connection with bit lines and / or capacitors are formed on the source / drain regions of the recess gate MOS transistor, reducing contact resistance and between neighboring contact structures or between the contact structures and the gate electrode. Proper contact area must be ensured to suppress electrical shorts. That is, the active region on both sides of the gate electrode where the source / drain regions are formed should have an area of a certain degree or more for good contact formation. In other words, although the problems due to the short channel effect can be suppressed by applying the recess gate MOS transistor, there is still a need for an appropriate contact area as described above.

Accordingly, in order to overcome the above problems, a semiconductor device having a buried word line is disclosed in US Patent No. 6,770,535 B2 entitled "Semiconductor integrated circuit device and process for manufacturing the same." It was disclosed by Yamada et al. Under the title. According to Yamada, trenches are formed across the channel region and the device isolation film. A word line is formed to fill a portion of the trench. An insulating pattern is formed to fill the remaining portion of the trench. As a result, the word line is buried below the surface of the semiconductor substrate. The buried word line provides a relatively large effective channel length.

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art. Reference numerals 'C0' and 'P0' denote cell areas and peripheral circuit areas, respectively.

Referring to FIG. 1A, a semiconductor substrate 1 having a cell region C0 and a peripheral region P0 is prepared. An isolation layer 2 is formed in the semiconductor substrate 1. The device isolation film 2 may be formed by a known shallow trench isolation technique. Specifically, forming the device isolation film may include forming a trench 2t in the semiconductor substrate 1 and forming a device isolation insulating film 2 filling the inside of the trench 2t. The device isolation insulating film 2 may be formed of a silicon oxide film such as a high density plasma (HDP) oxide film. A cell active region 1c is defined in the cell region C0 and a peripheral active region 1p is defined in the peripheral circuit region P0 by the device isolation layer 2.

A buffer insulating film 4 may be formed on the semiconductor substrate 1 having the device isolation film 2. The buffer insulating film 4 may be formed of a silicon oxide film. Subsequently, a conductive film 6 may be formed on the semiconductor substrate 1. The conductive film 6 may be formed of a polysilicon film. The first mask layer 8 may be formed on the conductive layer 6. The first mask layer 8 may be formed of a silicon nitride layer.

The first mask layer 8 may be patterned to form a first mask pattern 8 ′ in the cell region C0. The first mask layer 8 may be patterned by conventional photolithography and etching processes. The first mask pattern 8 ′ covers the conductive film 6 in a portion overlapping with both ends of the cell active region 1c, and a center portion between the cell active regions 1c between the both ends. It may be formed to expose the conductive film 6 of the portion overlapping with. The first mask layer 8 of the peripheral circuit region P0 may remain as it is without patterning.

Sacrificial spacers 10 may be formed to cover sidewalls of the first mask pattern 8 ′. The sacrificial spacers 10 may be formed by conformally forming a sacrificial layer (not shown) on the semiconductor substrate 1 having the first mask pattern 8 ′ and etching the sacrificial layer over the entire surface. Can be. The sacrificial spacers 10 may be formed of a material film having an etch selectivity with respect to the first mask pattern 8 ′. For example, the sacrificial spacers 10 may be formed of a polysilicon layer.

The second mask layer 12 may be conformally formed on the semiconductor substrate 1 having the sacrificial spacers 10. The second mask layer 12 may be formed of the same material layer as the first mask layer 8. The second mask layer 12 may be formed of a silicon nitride layer. Next, the second mask layer 12 may be planarized to expose the top surfaces of the sacrificial spacers 10. As a result, the second mask pattern 12 ′ remaining between the sacrificial spacers 10 is formed. The planarized second mask layer 12 may remain on the first mask layer 8 in the peripheral circuit region P0. The planarization of the second mask layer 12 may be performed by a chemical mechanical polishing process or an etch-back process. In addition, upper surfaces of the first mask pattern 8 ′ may also be exposed during the planarization process.

Referring to FIG. 1B, the sacrificial spacers 10 may be selectively removed. As a result of selectively removing the sacrificial spacers 10, first and second mask patterns 8 ′ having openings 14 crossing the cell active region 1c on the conductive layer 6 are formed. 12 ') can be formed. The conductive layer 6 and the buffer insulating layer 4 are sequentially etched using the first and second mask patterns 8 ′ and 12 ′ as etching masks, and then the semiconductor substrate 1 is etched to a predetermined depth. Etch with. As a result, channel trenches 18 are formed in the semiconductor substrate 1 across the cell active region 1c. The channel trenches 18 may cross the cell active region 1c and may extend to the device isolation layer 2 adjacent to the cell active region 1c. At the same time, the first and second mask patterns 8 'and 12' are also partially etched. In particular, since the second mask pattern 12 ′ has a narrower width than the first mask pattern 8 ′, the second mask pattern 12 ′ is etched more. As a result, a second mask pattern 12 "thinner than the first mask pattern 8 'is formed. In other words, the first and second mask patterns 8' and 12", and the The thicknesses of the first and second mask layers 8 and 12 stacked in the peripheral circuit region P0 are different from each other. In particular, the second mask pattern 12 ″ may be stacked in the peripheral circuit region P0. Compared to the thicknesses of the first and second mask layers 8 and 12, the thickness is very thin.

Referring to FIG. 1C, a cell gate insulating layer 20 is formed on inner walls of the channel trenches 18. The cell gate insulating film 20 may be formed of a silicon oxide film by a thermal oxidation process. A cell gate electrode film (not shown) is formed on the semiconductor substrate 1 having the cell gate insulating film 20. The cell gate electrode layer may be formed of a titanium nitride layer, and fills the channel trenches 18 and fills the first and second mask patterns 8 ′ and 12 ″ and the peripheral circuit region P0. The cell gate electrode layer 22 may be planarized to form a cell gate electrode pattern 22 remaining in the channel trenches 18. The planarization of the film may be performed by an etch back process, and the upper portion of the first and second mask patterns 8 ′ and 12 ″ and the second mask layer 12 in the peripheral circuit area P0 may be formed. The surface may be performed to expose.

Referring to FIG. 1D, after the cell gate electrode pattern 22 is formed, the first and second mask patterns 8 ′ and 12 ″ and the first and second portions of the peripheral circuit region P0 may be formed. The mask layers 8 and 12 are etched back to remove the first and second mask patterns 8 ′ and 12 ″ and the first and second stacked regions of the peripheral circuit region P0. Since the thicknesses of the second mask layers 8 and 12 are different from each other, the conductive layer 6 of the cell region C0 may be partially etched by the etch back process. In particular, since the second mask pattern 12 ″ is etched the fastest, the conductive film 6 under the second mask pattern 12 ″ is also etched the most so that the conductive film 6 ″ having the thinnest thickness is obtained. In addition, the conductive film 6 'under the first mask pattern 8' may also be partially etched to have a thickness thinner than that of the conductive film 6 in the peripheral circuit region P0. have.

A gate conductive layer 24 and a capping insulating layer 26 may be sequentially formed on the conductive layers 6, 6 ′, 6 ″ and the cell gate electrode pattern 22. The capping insulating film 26 may be formed of a metal film such as tungsten or a metal silicide film such as a tungsten silicide film, and the capping insulating film 26 may be formed of a silicon nitride film.

Referring to FIG. 1F, the capping insulating layer 26, the gate conductive layer 24, and the conductive layers 6, 6 ′, and 6 ″ are patterned to form a peripheral gate pattern 30 on the peripheral active region 1p. The peripheral gate pattern 30 may include a peripheral gate electrode 28 and a peripheral gate capping layer 26 ′ that are sequentially stacked on the peripheral gate pattern 30. The buffer insulating layer 4 may be formed of a stacked conductive layer pattern 6p and a gate conductive layer pattern 24 ′. Meanwhile, the buffer insulating layer 4 may also be patterned while the peripheral gate pattern 30 is formed. A peripheral gate insulating layer 4 ′ may be formed between the peripheral gate electrode 28 and the peripheral active region 1p. As a result, the peripheral gate pattern 30 may form the peripheral active region 1p. Peripheral gate insulating film 4 ', peripheral gate electrode 28 and peripheral gay It can be configured to cache pingmak (26 ').

Meanwhile, the capping insulating layer 26, the gate conductive layer 24, and the conductive layers 6 ′ and 6 ″ on the cell active region 1c are etched away while the peripheral gate pattern 30 is formed. In this case, the conductive layers 6 ′ and 6 ″ are thinner than the conductive layer 6 in the peripheral circuit region P0, so that the cells are formed while forming the peripheral gate pattern 30. The defect that the upper surface of the active region 1c is recessed 35 occurs. As a result, the characteristics of the MOS transistor can be degraded.

The cell gate electrode patterns 22 may be recessed into the channel trenches 18. The cell gate electrode patterns 22 may be recessed into the channel trenches 18 by performing an etching process for forming the peripheral gate pattern 30 and performing an additional transient etching. As a result, cell gate electrodes 22 ′ buried in the channel trenches 18 may be formed.

A conformal insulating film (not shown) is formed on the semiconductor substrate 1 having the peripheral gate pattern 30 and the cell gate electrodes 22 '. The insulating film may be formed of, for example, a silicon nitride film, a silicon oxide film, or a silicon oxynitride film. Afterwards, the insulating layer may be anisotropically etched. As a result, gate spacers 32s covering sidewalls of the peripheral gate pattern 30 may be formed, and cell gate capping layers 32c covering upper surfaces of the cell gate electrodes 22 ′ may be formed. have. The cell gate capping layers 32c may be formed to fill the channel trenches 18 on the cell gate electrodes 22 ′. In this case, the cell gate capping layers 32c may be formed in the region 35 where the upper surface of the cell active region 1c is recessed.

As described above, the conductive layers 6 ′ and 6 ″ are thinner than the conductive layer 6 in the peripheral circuit region P0, and thus, the cell is active during the formation of the peripheral gate pattern 30. The defect that the upper surface of the region 1c is recessed 35 is generated, thus preventing the defect that the upper surface of the cell active region 1c is recessed while forming the peripheral gate pattern 30. There is a need for research on how to do this.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide methods for manufacturing a semiconductor device having an embedded gate electrode capable of preventing a defect in which an upper surface of a cell active region is recessed while forming a peripheral gate pattern.

According to an aspect of the present invention, a method of manufacturing a semiconductor device having a buried gate electrode is provided. The method includes forming a device isolation film defining an active region in a semiconductor substrate. First and second mask patterns crossing the active region are formed on a substrate having the device isolation layer. The semiconductor substrate and the device isolation layer are etched using the first and second mask patterns as etch masks to form channel trenches crossing the active region. In this case, the second mask pattern is etched to a thickness thinner than the first mask pattern. A gate electrode pattern is formed to fill the channel trench. A buffer mask layer is formed on the substrate having the gate electrode pattern to alleviate the step difference between the first and second mask patterns. The buffer mask layer and the first and second mask patterns are etched back and removed.

In some embodiments of the present disclosure, forming the first and second mask patterns may include forming a first mask layer on a substrate having the device isolation layer and patterning the first mask layer to form both ends of the active region. Forming a first mask pattern covering the overlapping portions, exposing a portion overlapping with a center portion between the both ends, forming sacrificial spacers covering sidewalls of the first mask pattern, and filling the sacrificial spacers. The method may include forming a second mask pattern and selectively removing the sacrificial spacers.

In other embodiments, the buffer mask layer may be formed of the same material layer as the first and second mask patterns.

In other embodiments, the first and second mask patterns may be formed of silicon nitride.

In other embodiments, the buffer mask layer may be formed of a silicon nitride layer.

In other embodiments, the buffer mask layer may be formed by a plasma enhanced chemical vapor deposition (PECVD) method.

In another embodiment, before forming the first and second mask patterns, a conductive film may be formed on the substrate having the device isolation film. In this case, the conductive layer may be etched while forming a channel trench that crosses the active region by using the first and second mask patterns as an etching mask. The conductive film may be formed of a polysilicon film.

According to another aspect of the present invention, a method of manufacturing a semiconductor device having a buried gate electrode is provided. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. An isolation layer defining a cell active region and a peripheral active region is formed in the semiconductor substrate. A first conductive film is formed on the semiconductor substrate. First and second mask patterns crossing the cell active region and first and second mask layers covering the peripheral circuit region are sequentially formed on the first conductive layer. The first conductive layer, the semiconductor substrate, and the device isolation layer are etched using the first and second mask patterns as an etching mask to form a channel trench crossing the active region. In this case, the second mask pattern is etched to a thickness thinner than the first mask pattern. A cell gate electrode pattern is formed to fill the channel trench. A buffer mask layer is formed on the substrate having the cell gate electrode pattern to alleviate the step difference between the first and second mask patterns. The buffer mask layer, the first and second mask patterns, and the first and second mask layers are etched back and removed.

In some embodiments of the present disclosure, cell gate insulating layers may be formed on inner walls of the channel trench before forming the cell gate electrode pattern filling the channel trench.

In other embodiments, after the buffer mask layer, the first and second mask patterns, and the first and second mask layers are etched and removed, the first conductive layer is patterned to form a peripheral portion on the peripheral active region. The cell gate electrode pattern may be recessed and the cell gate electrodes embedded in the channel trenches may be formed at the same time as the gate electrode is formed. Subsequently, a conformal insulating film is formed on the semiconductor substrate having the cell and peripheral gate electrodes, and the insulating film is etched to form gate spacers on sidewalls of the peripheral gate electrode and simultaneously cover the cell gate electrodes. Cell gate capping layers may be formed.

In still other embodiments, the forming of the first and second mask patterns and the first and second mask layers may include forming a first mask layer on the substrate having the device isolation layer, and forming the first mask layer on the cell region. A first mask pattern is formed by patterning a mask layer to cover portions overlapping with both ends of the cell active region, and to expose a portion overlapping with a center portion between the both ends, and to cover sidewalls of the first mask pattern. The method may include forming spacers, forming a second mask pattern filling the sacrificial spacers, a second mask layer covering the peripheral circuit region, and selectively removing the sacrificial spacers.

In example embodiments, the buffer mask layer may be formed of the same material layer as the first and second mask patterns.

In other embodiments, the first and second mask patterns may be formed of silicon nitride.

In other embodiments, the buffer mask layer may be formed of a silicon nitride layer.

In other embodiments, the buffer mask layer may be formed by a plasma enhanced chemical vapor deposition (PECVD) method.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

2 is a plan view illustrating a method of manufacturing a semiconductor device in accordance with embodiments of the present invention. 3A through 3H are cross-sectional views taken along line II ′ and II-II ′ of FIG. 2 to explain a method of manufacturing a semiconductor device according to example embodiments. Reference numerals C1 and P1 denote cell regions and peripheral circuit regions, respectively.

2 and 3A, a semiconductor substrate 100 having a cell region C1 and a peripheral region P1 is prepared. The semiconductor substrate 100 may be a single crystal silicon substrate, and may be a first conductivity type, for example, a P-type semiconductor substrate. An isolation layer 102 is formed in the semiconductor substrate 100. The device isolation layer 102 may be formed by a known shallow trench isolation technique.

Specifically, forming the device isolation layer may include forming a trench 101 in the semiconductor substrate 100 and forming a device isolation insulating layer 102 filling the inside of the trench 101. The device isolation insulating film 102 may be formed of a silicon oxide film such as a high density plasma (HDP) oxide film. The cell isolation region 100c defines a cell active region 100c in the cell region C1, and defines a peripheral active region 100p in the peripheral circuit region P1.

A buffer insulating layer 104 may be formed on the semiconductor substrate 100 having the device isolation layer 102. The buffer insulating film 104 may be formed of, for example, a silicon oxide film by a thermal oxidation process. In addition, the buffer insulating film 104 may be formed of a high dielectric film such as a metal oxide film, a metal oxynitride film, or a metal silicate film. Subsequently, a conductive film 106 may be formed on the semiconductor substrate 100. The conductive layer 106 may be formed of a polysilicon layer. In this case, the polysilicon film may be deposited by, for example, a chemical vapor deposition (CVD) process, and during the deposition process, for example, phosphorus (P) or phosphorus (N) -type impurities such as arsenic (As) It may be doped in-situ. In addition, the polysilicon film may be deposited by, for example, a CVD process and then doped with impurities by an ion implantation process. The first mask layer 108 may be formed on the conductive layer 106. The first mask film 108 may be formed of an insulating film, for example, a silicon nitride film.

2 and 3B, the first mask layer 108 may be patterned to form a first mask pattern 108 ′ in the cell region C1. The first mask layer 108 may be patterned by conventional photolithography and etching processes. The first mask pattern 108 ′ covers the conductive layer 106 in a portion overlapping with both ends of the cell active region 100 c, and a center portion between the cell active regions 100 c between the both ends. It may be formed to expose the conductive film 106 of the portion overlapping with. Meanwhile, the first mask layer 108 in the peripheral circuit region P1 may remain as it is without patterning.

Sacrificial spacers 110 may be formed to cover sidewalls of the first mask pattern 108 ′. The sacrificial spacers 110 may be formed by conformally forming a sacrificial layer (not shown) on the semiconductor substrate 100 having the first mask pattern 108 ′ and etching the sacrificial layer over anisotropically. Can be. The sacrificial spacers 110 may be formed of a material film having an etch selectivity with respect to the first mask pattern 108 ′, for example, a material film having an etching rate higher than that of the first mask pattern 108 ′. Can be. For example, the sacrificial spacers 110 may be formed of a polysilicon layer.

2 and 3C, a second mask layer 112 may be conformally formed on the semiconductor substrate 100 having the sacrificial spacers 110. The second mask layer 112 may be formed of the same material layer as the first mask layer 108. For example, the second mask film 112 may be formed of an insulating film such as a silicon nitride film. Next, the second mask layer 112 may be planarized to expose upper surfaces of the sacrificial spacers 110. As a result, the second mask pattern 112 ′ remaining between the sacrificial spacers 110 is formed. Meanwhile, a planarized second mask layer 112 " may remain on the first mask layer 108 in the peripheral circuit region P1. The planarization of the second mask layer 112 is chemical mechanical It may be performed by a chemical mechanical polishing process or an etch-back process, and top surfaces of the first mask pattern 108 ′ may also be exposed during the planarization process.

2 and 3D, the sacrificial spacers 110 may be selectively removed. As described above, the sacrificial spacers 110 are formed of a material layer having an etch selectivity with respect to the first mask pattern 108 ′ and the second mask pattern 112 ′. For example, the first mask pattern 108 ′ and the second mask pattern 112 ′ may be formed of a silicon nitride layer, and the sacrificial spacers 110 may be formed of a polysilicon layer. As a result of selectively removing the sacrificial spacers 110, first and second mask patterns 108 ′ having openings 114 crossing the cell active region 100c on the conductive layer 106, 112 ') can be formed.

The conductive layer 106 and the buffer insulating layer 104 are sequentially etched using the first and second mask patterns 108 ′ and 112 ′ as etch masks, and then the semiconductor substrate 100 is etched to a predetermined depth. Etch with. As a result, channel trenches 118 that cross the cell active region 100c are formed in the semiconductor substrate 100. The channel trenches 118 may cross the cell active region 100c and may extend to the device isolation layer 102 adjacent to the cell active region 100c. At the same time, the first and second mask patterns 108 ′ and 112 ′ may also be partially etched. In particular, since the second mask pattern 112 ′ has a narrower width than the first mask pattern 108 ′, the second mask pattern 112 ′ may be more etched. As a result, a second mask pattern 112 ″ thinner than the first mask pattern 108 ′ may be formed.

2 and 3E, a cell gate insulating layer 120 is formed on inner walls of the channel trenches 118. The cell gate insulating layer 120 may be formed of a silicon oxide layer by a thermal oxidation process. In addition, the cell gate insulating layer 120 may be formed of a high dielectric layer such as a metal oxide layer, a metal oxynitride layer, or a metal silicate layer using a CVD process or an atomic layer deposito (ALD) process.

A cell gate electrode film (not shown) is formed on the semiconductor substrate 100 having the cell gate insulating film 120. The cell gate electrode layer may be formed of a titanium nitride layer, and fills the channel trenches 118 to cover the first and second mask patterns 108 ′ and 112 ″ and the peripheral circuit region P1. The cell gate electrode layer 122 may be planarized to form a cell gate electrode pattern 122 remaining in the channel trenches 118. The planarization of the film may be performed by a CMP process or an etch back process, and the first and second mask patterns 108 ′ and 112 ″, and the second mask layer 112 in the peripheral circuit region P1. ) May be performed so that the top surface of is exposed.

2 and 3F, after the cell gate electrode pattern 122 is formed, the first and second mask patterns 108 ′ and 112 ″ are formed on a substrate having the cell gate electrode pattern 122. The buffer mask layer 123 may be formed to alleviate the step difference, and the buffer mask layer 123 may be formed of the same material layer as the first and second mask patterns 108 ′ and 112 ″. The buffer mask layer 123 may be formed of a silicon nitride layer. Since the buffer mask layer 123 is formed to alleviate the step difference between the first and second mask patterns 108 ′ and 112 ″, the buffer mask layer 123 may be formed using a method having poor step coverage characteristics. For example, the buffer mask layer 123 may be formed by a plasma enhanced chemical vapor deposition (PECVD) method, and as a result, voids 123v between the first and second mask patterns 108 ′ and 112 ″. ) May occur.

2 and 3G, the first and second masks of the buffer mask layer 123, the first and second mask patterns 108 ′ and 112 ″, and the peripheral circuit region P1 are described. The layers 108 and 112 are etched and removed, and the steps between the cell region C1 and the peripheral circuit region P1 are alleviated by the buffer mask layer 123, and thus, the etch back process is performed. In comparison, the thickness difference between the conductive layer 106 between the cell region C1 and the peripheral circuit region P1 may be reduced.

The gate conductive layer 124 and the capping insulating layer 126 may be sequentially formed on the substrate on which the conductive layer 106 is exposed. The gate conductive layer 124 may be formed of a metal layer such as tungsten or a metal silicide layer such as a tungsten silicide layer. In addition, the capping insulating layer 126 may be formed of a silicon nitride layer.

2 and 3H, the capping insulating layer 126, the gate conductive layer 124, and the conductive layer 106 are patterned to form a peripheral gate pattern 130 on the peripheral active region 100p. can do. The peripheral gate pattern 130 may include a peripheral gate electrode 128 and a peripheral gate capping layer 126 ′ that are sequentially stacked. In addition, the peripheral gate electrode 128 may be formed of a conductive film pattern 106 ′ and a gate conductive film pattern 124 ′ that are sequentially stacked. Meanwhile, the buffer insulating layer 104 may also be patterned while forming the peripheral gate pattern 130. As a result, a peripheral gate insulating layer 104 ′ interposed between the peripheral gate electrode 128 and the peripheral active region 100p may be formed. As a result, the peripheral gate pattern 130 may include a peripheral gate insulating layer 104 ′, a peripheral gate electrode 128, and a peripheral gate capping layer 126 ′ that are sequentially stacked on the peripheral active region 100p. have.

Meanwhile, the capping insulating layer 126, the gate conductive layer 124, and the conductive layer 106 of the cell region C1 may be etched and removed while forming the peripheral gate pattern 130. In this case, the thickness difference between the conductive layer 106 between the cell region C1 and the peripheral circuit region P1 may be reduced by the buffer mask layer 123 as compared with the related art. The defect that the upper surface of the 100c is recessed can be prevented.

The cell gate electrode patterns 122 may be recessed into the channel trenches 118. The cell gate electrode patterns 122 may be recessed into the channel trenches 118 by performing an etching process for forming the peripheral gate pattern 130 and performing an additional transient etching. As a result, cell gate electrodes 122 ′ buried in the channel trenches 118 may be formed. The cell gate electrodes 122 ′ may be formed to have an upper surface positioned at a level lower than the surface of the cell active region 100 c.

A conformal insulating film (not shown) is formed on the semiconductor substrate 100 having the peripheral gate pattern 130 and the cell gate electrodes 122 ′. The insulating film may be formed of, for example, a silicon nitride film, a silicon oxide film, or a silicon oxynitride film. Afterwards, the insulating layer may be anisotropically etched. As a result, gate spacers 132s may be formed to cover sidewalls of the peripheral gate pattern 130, and cell gate capping layers 132c may be formed to cover top surfaces of the cell gate electrodes 122 ′. have. The cell gate capping layers 132c may be formed to fill the channel trenches 118 on the cell gate electrodes 122 ′. In this case, upper surfaces of the cell gate capping layers 132c may be positioned at substantially the same level as the surface of the cell active region 100c.

As described above, according to the present invention, after forming a channel trench using mask patterns to form a buried gate electrode, forming a cell gate electrode pattern inside the channel trench, and then alleviating the steps of the mask patterns. A buffer mask film having poor step coverage characteristics is formed, and then the buffer mask film and the mask patterns are etched back and removed. Accordingly, the thickness difference between the conductive film in the cell region and the peripheral circuit region can be reduced by the buffer mask film, thereby preventing a defect in which the upper surface of the cell active region is recessed. .

Claims (16)

Forming a device isolation film defining an active region in the semiconductor substrate Forming first and second mask patterns across the active region on the substrate having the device isolation layer; By using the first and second mask patterns as an etching mask, the semiconductor substrate and the device isolation layer are etched to form a channel trench that crosses the active region, wherein the second mask pattern is thinner than the first mask pattern. Etched into Forming a gate electrode pattern filling the channel trench, Forming a buffer mask layer on the substrate having the gate electrode pattern to alleviate the step difference between the first and second mask patterns; And etching back the buffer mask layer and the first and second mask patterns. The method of claim 1, Forming the first and second mask patterns, Forming a first mask film on the substrate having the device isolation film; Patterning the first mask layer to cover portions overlapping with both ends of the active region, and forming a first mask pattern exposing portions overlapping with a center portion between the both ends; Forming sacrificial spacers covering sidewalls of the first mask pattern, Forming a second mask pattern filling the sacrificial spacers, Selectively removing the sacrificial spacers. The method of claim 1, The buffer mask layer may be formed of the same material layer as the first and second mask patterns. The method of claim 1, The first and second mask patterns are formed of a silicon nitride film. The method of claim 1, And the buffer mask layer is formed of a silicon nitride layer. The method of claim 1, The buffer mask film is a semiconductor device manufacturing method, characterized in that formed by plasma enhanced chemical vapor deposition (PECVD) method. The method of claim 1, Before forming the first and second mask patterns, The method may further include forming a conductive layer on the substrate having the device isolation layer, wherein the conductive layer is etched at the same time as forming a channel trench across the active region using the first and second mask patterns as an etch mask. A method for manufacturing a semiconductor device. The method of claim 7, wherein The conductive film is a manufacturing method of a semiconductor device, characterized in that the polysilicon film formed. Preparing a semiconductor substrate having a cell region and a peripheral circuit region; Forming an isolation layer defining a cell active region and a peripheral active region in the semiconductor substrate, Forming a first conductive film on the semiconductor substrate, Forming first and second mask patterns crossing the cell active region and first and second mask layers sequentially covering the peripheral circuit region on the first conductive layer, The first conductive layer, the semiconductor substrate, and the device isolation layer are etched using the first and second mask patterns as an etch mask to form a channel trench that crosses the active region, wherein the second mask pattern is the second mask pattern. Etched to a thickness thinner than 1 mask pattern, Forming a cell gate electrode pattern filling the channel trench, Forming a buffer mask layer on the substrate having the cell gate electrode pattern to alleviate the step difference between the first and second mask patterns; And etching back the buffer mask layer, the first and second mask patterns, and the first and second mask layers. The method of claim 9, Before forming the cell gate electrode pattern filling the channel trench, And forming cell gate insulating layers on inner walls of the channel trench. The method of claim 9, After the buffer mask layer, the first and second mask patterns, and the first and second mask layers are etched back and removed, Patterning the first conductive layer to form a peripheral gate electrode on the peripheral active region, and simultaneously recessing the cell gate electrode pattern to form buried cell gate electrodes in the channel trenches, Forming a conformal insulating film on the semiconductor substrate having the cell and peripheral gate electrodes, And etching the insulating film to form gate spacers on sidewalls of the peripheral gate electrode and to form cell gate capping layers covering the cell gate electrodes. The method of claim 9, Forming the first and second mask patterns and the first and second mask layers, Forming a first mask film on the substrate having the device isolation film; Patterning the first mask layer on the cell region to cover portions overlapping with both ends of the cell active region, and forming a first mask pattern exposing portions overlapping with the center portion between the both ends; Forming sacrificial spacers covering sidewalls of the first mask pattern, Forming a second mask pattern filling the sacrificial spacers and a second mask layer covering the peripheral circuit region; Selectively removing the sacrificial spacers. The method of claim 9, The buffer mask layer may be formed of the same material layer as the first and second mask patterns. The method of claim 9, The first and second mask patterns are formed of a silicon nitride film. The method of claim 9, And the buffer mask layer is formed of a silicon nitride layer. The method of claim 9, The buffer mask film is a semiconductor device manufacturing method, characterized in that formed by plasma enhanced chemical vapor deposition (PECVD) method.

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