KR20080069361A - Test device of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test device for a semiconductor device, comprising: a memory cell including a cell transistor and a capacitor, accessed by a word line and a bit line to read / write data, for detecting a SAC failure between a gate and a landing plug; And a word line voltage selector for selectively supplying a ground voltage and a back bias voltage to a word line, and a cell plate voltage selector for selectively supplying a bit line precharge voltage and a core voltage to a cell plate voltage applying terminal of a capacitor. As a result, the difference between the cell plate voltage level and the word line voltage level can be increased to efficiently detect SAC defects between the gate and the landing plug, thereby improving subsequent package characteristics.

Description

TEST EQUIPMENT OF SEMICONDUCTOR DEVICE

1 is a cross-sectional view showing a semiconductor device according to the prior art.

Figure 2 is a waveform diagram showing the operation of the test apparatus for a semiconductor device according to the prior art.

3 is a circuit diagram showing a test apparatus for a semiconductor device according to the present invention.

4 is a detailed circuit diagram of the word line voltage selector illustrated in FIG. 3.

FIG. 5 is a detailed circuit diagram of the cell plate voltage selector illustrated in FIG. 3.

6 is a waveform diagram showing an operation of a test apparatus for a semiconductor device according to the present invention;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test device for semiconductor devices, and more particularly, to a technology capable of testing a self alignment contact (SAC) defect between a gate and a landing plug.

As the degree of integration of semiconductor devices increases, gaps between conductive lines such as gates become narrower, and thus contact process margins decrease.

In order to secure such a contact process margin, a Self Aligned Contact (SAC) process is being performed.

1 is a cross-sectional view showing a semiconductor device according to the prior art.

Referring to FIG. 1, a gate 12 is formed on a semiconductor substrate 10, and a landing plug 14 is formed between the gates 12.

A storage electrode contact plug 16 is formed in contact with the landing plug 14, and a storage electrode 18 is formed on the storage electrode contact plug 16.

The operation of the prior art having such a configuration will be described with reference to FIG.

2 is a waveform diagram illustrating an operation of a test apparatus for a semiconductor device according to the related art.

The cold probe test is performed by changing the temperature at a low temperature below a certain temperature. The cold probe test writes " 1 " data to a memory cell (T1 section), and then After the cell transistor is turned off, a pause time of 100 ms or more is allowed (T2 section), and then "1" data is read (T3 section).

At this time, the cell plate voltage VCP maintains the bit line precharge voltage VBLP level (half potential of the core voltage VCORE) in the T1, T2, and T3 sections, and the voltage of the word line WL is T1 and T3 sections. Has a high voltage VPP level, and has a ground voltage VSS level in the T2 period.

However, when a SAC failure occurs between the gate 12 and the landing plug 14, the cell plate voltage VCP applied to the storage electrode 18 and the voltage applied to the gate 12 of the cell transistor (word line WL). The leakage current is generated by the potential difference of voltage).

As a result, the data stored in the memory cell is lowered by? V1 at the core voltage VCORE level.

On the other hand, the hot probe test (hot probe test) proceeds in the same order as the low temperature probe test while changing the temperature at a high temperature above a certain temperature.

However, since the effects of the junction leakage current and the gate off leakage current are greater than those of the low temperature probe test, the low temperature probe test is required to detect only the SAC failure between the gate 12 and the landing plug 14. effective.

However, as the semiconductor device is highly integrated, the line width of the gate 12 is reduced, so that a SAC defect occurs due to a process margin. In this case, there is a limit to screen the SAC defect with a small amount of change as ΔV1.

The present invention has been made to solve the above problems, and an object thereof is to provide a test apparatus for a semiconductor device capable of detecting a SAC defect between a gate and a landing plug.

According to an aspect of the present invention, a semiconductor device testing apparatus includes a memory cell including a cell transistor and a capacitor and accessed by a word line and a bit line to read / write data; A word line voltage selector for selectively supplying a ground voltage and a back bias voltage to the word line; And a cell plate voltage selector for selectively supplying a bit line precharge voltage and a core voltage to the cell plate voltage applying terminal of the capacitor.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram showing a test apparatus for a semiconductor device according to the present invention.

The test apparatus of the present invention includes an equalizer 10, a sense amplifier driver 20, a sense amplifier 30, a word line voltage selector 40, a cell plate voltage selector 50, and a memory cell C. do.

The equalizer 10 precharges and equalizes the bit line BL and the bit line bar / BL to the bit line precharge voltage VBLP level according to the equalization signal BLEQ.

The sense amplifier driver 20 includes a pull-up part 22, an equalizer 24, and a pull-down part 26.

Here, the pull-up unit 22 pulls up the pull-up line RTO to the power supply voltage VDD level according to the pull-up control signal RTOEN.

The equalizer 24 equalizes the pull-up line RTO and the pull-down line SB to the bit line precharge voltage VBLP level according to the equalization signal BLEQ.

The pull-down unit 26 pulls down the pull-down line SB to the ground voltage VSS level according to the pull-down control signal SBEN.

The sense amplifier 30 is a latch type and is enabled by a pull-up control signal and a pull-down control signal applied through a pull-up line RTO and a pull-down line SB, and thus, a bit line BL and a bit line bar (/ BL). Sensing and amplifying the voltage difference.

The word line voltage selector 40 selectively supplies the ground voltage VSS and the back bias voltage VBB to the word line WL.

The cell plate voltage selector 50 selectively supplies the bit line precharge voltage VBLP and the core voltage VCORE to the cell plate voltage VCP applying terminal.

The memory cell C includes a cell transistor and a capacitor and is accessed by the word line WL and the bit line BL to read / write data. Here, the gate of the cell transistor is connected to the word line WL, and the plate electrode of the capacitor is connected to the cell plate voltage VCP applying terminal.

4 is a detailed circuit diagram of the word line voltage selector 40 shown in FIG. 3.

The word line voltage selector 40 includes a selector 42, a selector 44, a selector 46, and a selector 48.

The selector 42 includes an NMOS transistor N1. The NMOS transistor N1 is connected between the high voltage VPP applying terminal and the node A to receive the test signal TEST1 through the gate terminal.

The selector 44 includes an NMOS transistor N2. The NMOS transistor N2 is connected between the back bias voltage VBB applying terminal and the node A to receive the test signal TEST2 through the gate terminal.

The selector 46 includes an NMOS transistor N3. The NMOS transistor N3 is connected between the node A and the word line WL to receive the test signal TEST3 through the gate terminal.

The selector 48 includes an NMOS transistor N4. The NMOS transistor N4 is connected between the ground voltage VSS applying end and the word line WL to receive the test signal TEST4 through the gate terminal.

Here, the test signals TEST1 to TEST4 are signals applied by the user from the outside during the probe test, and a time point at which each signal is activated may be arbitrarily selected by the user.

FIG. 5 is a detailed circuit diagram of the cell plate voltage selector 50 shown in FIG. 3.

The cell plate voltage selector 50 includes a selector 52 and a selector 54.

The selector 52 includes an NMOS transistor N5. The NMOS transistor N5 is connected between the core voltage VCORE applying end and the cell plate voltage VCP applying end to receive the test signal TEST5 through the gate terminal.

The selector 54 includes an NMOS transistor N6. The NMOS transistor N6 is connected between the bit line precharge voltage VBLP applying end and the cell plate voltage VCP applying end to receive the test signal TEST6 through the gate terminal.

Here, the bit line precharge voltage VBLP has half the potential of the core voltage VCORE.

The test signals TEST5 and TEST6 are signals applied by a user from the outside during the probe test, and a time point at which each signal is activated may be arbitrarily selected by the user.

The operation of the present invention having such a configuration will be described with reference to FIG. 6 as follows.

6 is a waveform diagram illustrating an operation of a test apparatus for a semiconductor device according to the present invention.

First, "1" data is written to the memory cell C during the T4 period.

At this time, the NMOS transistor N6 is turned on by activating the test signal TEST6 and the NMOS transistors N1 and N3 are turned on by activating the test signals TEST1 and TEST3.

Accordingly, the bit line precharge voltage VBLP is applied to the cell plate voltage VCP applying terminal, and the high voltage VPP is applied to the word line WL.

Next, a pause time is allowed while the cell transistor of the memory cell C is turned off during the T5 period.

At this time, the test signal TEST5 is activated to turn on the NMOS transistor N5, and the test signals TEST2 and TEST3 are activated to turn on the NMOS transistors N2 and N3.

Accordingly, the core voltage VCORE is applied to the cell plate voltage VCP applying end, and the back bias voltage VBB is applied to the word line WL.

At this time, the data stored in the memory cell C rises from the core voltage VCORE level by 1/2 core voltage VCORE level as the cell plate voltage VCP increases.

However, when the SAC failure occurs, a leakage current is generated by the potential difference between the cell plate voltage VCP and the word line WL voltage.

As a result, the data level drops by ΔV2 at the sum of core voltage VCORE and half core voltage VCORE.

Then, "1" data is read into the memory cell C during the T6 period.

At this time, the NMOS transistor N6 is turned on by activating the test signal TEST6 and the NMOS transistors N1 and N3 are turned on by activating the test signals TEST1 and TEST3.

Accordingly, the bit line precharge voltage VBLP is applied to the cell plate voltage VCP applying terminal, and the high voltage VPP is applied to the word line WL.

That is, the cell plate voltage VCP level and the word line WL voltage are increased by raising the cell plate voltage VCP level to the core voltage VCORE level and lowering the word line WL voltage level to the back bias voltage VBB level during the pause time. The potential difference between the levels is such that the core voltage VCORE is combined with the back bias voltage VBB.

Therefore, the potential difference between the cell plate voltage VCP level and the word line (WL) voltage level is increased from the conventional half core voltage VCORE to the sum of the core voltage VCORE, the half core voltage VCORE, and the back bias voltage VBB, thereby further reducing leakage current. It happens a lot.

As a result, the voltage level of the data after the pause time is lowered by ΔV2 larger than the conventional ΔV1 at the core voltage VCORE level, so that the SAC defect between the gate and the landing plug can be efficiently screened.

As described above, the test apparatus of the semiconductor device according to the present invention applies a core voltage to the cell plate voltage applying terminal during a pause time during a probe test, and applies a back bias voltage to the word line, thereby providing a cell plate voltage level. The difference between the and wordline voltage levels can be made large to effectively detect SAC failures between the gate and landing plugs, thereby improving subsequent package characteristics.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (6)

A memory cell including a cell transistor and a capacitor, the memory cell being accessed by word lines and bit lines to read / write data; A word line voltage selector for selectively supplying a ground voltage and a back bias voltage to the word line; And A cell plate voltage selector for selectively supplying a bit line precharge voltage and a core voltage to the cell plate voltage applying terminal of the capacitor. Test device for a semiconductor device comprising a. The test apparatus of claim 1, wherein the word line voltage selector further selectively supplies a high voltage. 3. The word line voltage selector of claim 2, wherein the word line voltage selector A first selector selectively turned on according to a first test signal to transfer the high voltage to a first node; A second selector selectively turned on according to a second test signal to transfer the back bias voltage to the first node; A third selector selectively turned on according to a third test signal to transfer a voltage of the first node to the word line; And A fourth selector selectively turned on according to a fourth test signal to transfer the ground voltage to the word line Test device for a semiconductor device comprising a. 4. The test apparatus of claim 3, wherein the first, second, third and fourth selectors comprise MOS transistors. The method of claim 4, wherein the cell plate voltage selector A fifth selector selectively turned on according to a fifth test signal to transfer the core voltage to the cell plate voltage applying terminal; And A sixth selector selectively turned on according to a sixth test signal to transfer the bit line precharge voltage to the cell plate voltage applying terminal; Test device for a semiconductor device comprising a. 6. The test device of claim 5, wherein the fifth and sixth selectors comprise MOS transistors.

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