KR20080059864A - LCD panel and manufacturing method - Google Patents

Abstract

The present invention relates to a liquid crystal display panel and a method of manufacturing the same that can improve the viewing angle.

According to an exemplary embodiment of the present invention, a liquid crystal display panel includes a plurality of data lines; A plurality of gate lines intersecting the data lines; And a plurality of cells defined by the data line and the gate line, each cell having a first pixel electrode connected to a first node and a second node connected to a second node and separated from the first pixel electrode. A pixel electrode, a first thin film transistor supplying a first data voltage from the data line to the first node in response to a scan pulse from the gate line, and a second data voltage of the second node in response to the scan pulse A second thin film transistor for supplying the second pixel electrode to the second pixel electrode, a capacitor connected between the first and second nodes to determine the second data voltage supplied to the second node, the first pixel electrode and the storage voltage. A first storage capacitor formed between the supplied storage electrodes, and a second storage capacitor formed between the second pixel electrode and the storage electrode. A capacitor is provided.

Description

Liquid crystal display panel and its manufacturing method {LIQUID CRYSTAL DISPLAY PANEL AND FABRICATING METHOD THEREOF}

1 is a plan view illustrating a thin film transistor array substrate of a conventional liquid crystal display panel.

FIG. 2 is a cross-sectional view illustrating a thin film transistor array substrate and an upper color filter array substrate taken along the line "I-I '" of FIG.

3 is a circuit diagram schematically illustrating a liquid crystal display panel according to a first exemplary embodiment of the present invention.

4 is a diagram illustrating a rising angle of liquid crystal when an electric field is applied to the liquid crystal display panel according to the first exemplary embodiment of the present invention.

5 is a plan view illustrating a thin film transistor array substrate of a liquid crystal display panel according to a first exemplary embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a thin film transistor array substrate taken along lines “II-II ′” and “III-III ′” of FIG. 3.

7A to 7D are views illustrating a method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.

8 is a plan view illustrating a thin film transistor array substrate of a liquid crystal display panel according to a second exemplary embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a thin film transistor array substrate taken along lines "IV-IV '" and "V-V'" in FIG.

10 is a plan view illustrating another example of a storage capacitor.

11A to 11D illustrate a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention.

12 is a circuit diagram schematically illustrating a liquid crystal display panel according to a third exemplary embodiment of the present invention.

<Brief description of symbols for the main parts of the drawings>

2, 102, 302: gate line 4, 104, 304: data line

5, 105, 305: cell area

6, 106, 206, 306, 406: thin film transistor

8, 108, 208, 308, 408: gate electrode

10, 110, 210, 310, 410: source electrode

12, 112: drain electrodes 13, 113, 213, 313, 413: contact holes

14, 114, 214, 314, 414 pixel electrodes

16, 116, 316: storage electrode 18, 118, 218: storage capacitor

44: upper substrate 45: lower substrate

47: black matrix 48, 148, 348: active layer

49: color filter 50, 150, 350: ohmic contact layer

51 common electrode 53 liquid crystal molecule

60: thin film transistor array substrate

70: color filter array substrate 119, 319: first capacitor electrode

120 and 320 capacitors 122 and 322 second capacitor electrodes

128, 328: separation area

The present invention relates to a liquid crystal display panel and a method for manufacturing the same, and more particularly to a liquid crystal display panel and a method for manufacturing the same that can improve the viewing angle.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. The liquid crystal display drives the liquid crystal cell by an electric field formed between the pixel electrode and the common electrode, and is classified into a vertical electric field application type and a horizontal electric field application type according to the direction of the electric field. Among them, the vertical field applying liquid crystal display includes a liquid crystal display panel including a thin film transistor array substrate and a color filter array substrate, which are bonded to each other with a liquid crystal cell interposed therebetween, and the pixel electrode and the color filter formed on the thin film transistor array substrate. The liquid crystal of the twisted nematic (TN) mode is driven by the vertical electric field formed between the common electrodes formed on the array substrate. Such a vertical field application liquid crystal display device has an advantage of large aperture ratio.

FIG. 1 is a plan view illustrating a thin film transistor array substrate of a conventional vertical field applied liquid crystal display panel, and FIG. 2 illustrates a thin film transistor array substrate and an upper color filter array substrate cut along the line "I-I" in FIG. 1. It is sectional drawing.

1 and 2, the thin film transistor array substrate 60 intersects the gate line 2 and the data line 4 formed on the lower substrate 45 to intersect with the gate insulating layer 46 therebetween. The thin film transistor 6 formed in each section, the pixel electrode 14 formed in the cell region 5 provided in the intersection structure, and the storage capacitor 18 formed in the overlapping portion of the pixel electrode 14 and the storage electrode line 16. ).

The gate line 2 supplying the scan pulse and the data line 4 supplying the data voltage are formed in a cross structure to define the cell region 5.

The thin film transistor 6 keeps the data voltage of the data line 4 charged and maintained in the pixel electrode 14 in response to the scan pulse of the gate line 2. To this end, the thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode connected to the pixel electrode 14. 12). In addition, the thin film transistor 6 further includes an active layer 48 that overlaps with the gate electrode 8 and the gate insulating layer 46 therebetween to form a channel between the source electrode 10 and the drain electrode 12. . The active layer 48 is also formed to overlap the data line 4. The data line 4, the source electrode 10, and the drain electrode 12 and the ohmic contact layer 50 for ohmic contact are further formed on the active layer 48.

The pixel electrode 14 is connected to the drain electrode 12 of the thin film transistor 6 through the contact hole 13 penetrating the protective film 52 and is formed in the cell region 5.

The color filter array substrate 70 includes a black matrix 47 for preventing light leakage on the upper substrate 44 and increasing contrast by absorbing external light, a color filter 49 for realizing color, and a thin film transistor array substrate ( The common electrode 51 which forms a vertical electric field with the pixel electrode 14 of 60 is provided.

Accordingly, an electric field is formed between the pixel electrode 14 supplied with the data voltage through the thin film transistor 6 and the common electrode 51 supplied with the common voltage. The electric field causes the liquid crystal molecules 53 between the thin film transistor array substrate 60 and the color filter array substrate 70 to rotate by dielectric anisotropy. In addition, the light transmittance that passes through the cell region 5 is changed according to the degree of rotation of the liquid crystal molecules 53 to realize gray scale.

The storage capacitor 18 includes a storage electrode line 16 overlapping a portion of the pixel electrode 14 with the gate insulating layer 46 and the passivation layer 52 interposed therebetween. This storage capacitor 18 allows the data voltage charged in the pixel electrode 14 to remain stable until the next data voltage is supplied.

In the liquid crystal molecules 53 illustrated in FIG. 2, an electric field is applied between the pixel electrode 14 and the common electrode 51. At this time, the liquid crystal molecules 53 have the same rising angle regardless of the position. As a result, the conventional vertical field application liquid crystal display device has a disadvantage that the viewing angle is narrow, such that display quality is deteriorated due to uneven brightness depending on the viewing angle of the image. In particular, problems such as gray inversion occur in directions other than the main viewing angle.

Accordingly, an object of the present invention is to provide a liquid crystal display panel and a method of manufacturing the same that can improve the viewing angle.

In order to achieve the above object, the liquid crystal display panel according to an embodiment of the present invention comprises a plurality of data lines; A plurality of gate lines intersecting the data lines; And a plurality of cells defined by the data line and the gate line, each cell having a first pixel electrode connected to a first node and a second node connected to a second node and separated from the first pixel electrode. A pixel electrode, a first thin film transistor supplying a first data voltage from the data line to the first node in response to a scan pulse from the gate line, and a second data voltage of the second node in response to the scan pulse A second thin film transistor for supplying the second pixel electrode to the second pixel electrode, a capacitor connected between the first and second nodes to determine the second data voltage supplied to the second node, the first pixel electrode and the storage voltage. A first storage capacitor formed between the supplied storage electrodes, and a second storage capacitor formed between the second pixel electrode and the storage electrode. A capacitor is provided.

The storage electrode overlaps the first storage electrode overlapping the first pixel electrode between the first data line and the first pixel electrode, and the first and second pixel electrodes respectively between the first and second pixel electrodes. A second storage electrode, a third storage electrode overlapping the second pixel electrode between the second data line adjacent to the first data line, and the second pixel electrode, and the first to third storage electrodes; And a storage electrode line.

The storage electrode may include a first storage electrode overlapping the first pixel electrode between a first data line and the first pixel electrode, a second data line adjacent to the first data line, and the second pixel electrode. And a second storage electrode overlapping the second pixel electrode, and a storage electrode line connecting the first and second storage electrodes.

The storage electrode includes a storage electrode line that crosses the first and second pixel electrodes and overlaps the first and second pixel electrodes.

The storage electrode has an opaque metal.

The second data voltage is a voltage at which the first data voltage is reduced by the capacitor.

Areas of the first pixel electrode and the second pixel electrode are different from each other.

The first data voltage and the second data voltage have different values.

According to another exemplary embodiment of the present invention, a liquid crystal display panel includes a plurality of data lines; A plurality of gate lines intersecting the data lines; And a plurality of cells defined by the data line and the gate line, each cell having a first pixel electrode connected to a first node and a second node connected to a second node and separated from the first pixel electrode. A pixel electrode, a thin film transistor that supplies a first data voltage from the data line to the first node in response to a scan pulse from the gate line, and is connected between the first and second nodes to supply to the second node A capacitor configured to determine a second data voltage, a first storage capacitor formed between the first pixel electrode and a storage electrode to which the storage voltage is supplied, and a second storage capacitor formed between the second pixel electrode and the storage electrode. do.

A method of manufacturing a liquid crystal display panel according to an exemplary embodiment of the present invention includes a gate line, a first gate electrode of a first thin film transistor connected to the gate line, a first capacitor electrode connected to the gate line, and the gate line on a substrate. Forming a first conductive pattern group including a second gate electrode of the second thin film transistor connected to the second thin film transistor and a storage electrode; Forming a gate insulating film on the substrate on which the first conductive pattern group is formed; A data line crossing the gate line insulated from the gate line, a first source electrode of the first thin film transistor connected to the data line, a first drain electrode of the first thin film transistor facing the first source electrode, and the first A second capacitor electrode connected to the drain electrode, a second source electrode of the second thin film transistor connected to the second capacitor electrode, and a second drain electrode of the second thin film transistor facing the second source electrode. Forming a semiconductor layer forming a second conductive pattern group and channel portions of the first and second thin film transistors; Forming a passivation layer including a first contact hole and a second contact hole on the gate insulating layer on which the second conductive pattern group and the semiconductor layer are formed; And a third conductive pattern group including a first pixel electrode connected to the first drain electrode through the first contact hole, and a second pixel electrode connected to the second drain electrode through the second contact hole. Forming a step.

According to another embodiment of the present invention, a method of manufacturing a liquid crystal display panel includes a gate line on a substrate, a gate electrode of a thin film transistor connected to the gate line, a first capacitor electrode connected to the gate line, and a storage electrode. Forming a first conductive pattern group; Forming a gate insulating film on the substrate on which the first conductive pattern group is formed; A data line crossing the gate line to be insulated from the gate line, a source electrode of the thin film transistor connected to the data line, a drain electrode of the thin film transistor facing the source electrode, and a second capacitor electrode connected to the drain electrode. Forming a semiconductor layer forming a second conductive pattern group and a channel portion of the thin film transistor; Forming a passivation layer including a first contact hole and a second contact hole on the gate insulating layer on which the second conductive pattern group and the semiconductor layer are formed; And a third conductive pattern group including a first pixel electrode connected to the drain electrode through the first contact hole, and a second pixel electrode connected to the second capacitor electrode through the second contact hole. Steps.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 12.

3 is a circuit diagram schematically illustrating a liquid crystal display panel according to a first exemplary embodiment of the present invention.

Referring to FIG. 3, the liquid crystal display panel according to the first exemplary embodiment of the present invention may include first and second thin film transistors in a cell region defined by a data line DL and a gate line GL that cross each other. Transistor: TFT (TFT1, TFT2), the first pixel electrode Ep1 connected to the first node N1, and the second pixel connected to the second node N2 and separated from the first pixel electrode Ep1. An electrode Ep2 is provided.

The first TFT TFT1 supplies the first data voltage from the data line DL to the first node N1 in response to the scan pulse from the gate line GL, and the second TFT TFT2 supplies the gate line. In response to the scan pulse from GL, the second data voltage of the second node N2 is supplied to the second pixel electrode Ep2.

A capacitor C is connected between the first node N1 and the second node N2. The second data voltage is a voltage supplied to the second node N2 by reducing the first data voltage of the first node N1 by the capacitor C. FIG.

The first liquid crystal cell Clc1 and the second liquid crystal cell Clc2 are disposed between the common electrode Ec to which the common voltage is supplied, and the first and second pixel electrodes Ep1 and Ep2, respectively. It is driven by an electric field formed between the first and second pixel electrodes Ep1 and Ep2.

The liquid crystal display panel according to the first embodiment of the present invention further includes a storage electrode Est. The storage electrode Est overlaps the first pixel electrode Ep1 to form a first storage capacitor Cst1, and the storage electrode Est overlaps the second pixel electrode Ep1 to form a second storage capacitor Cst2. The first storage capacitor Cst1 charges the first data voltage supplied to the first pixel electrode Ep1, and the second storage capacitor Cst2 charges the second data voltage supplied to the second pixel electrode Ep2. Done.

With this structure, when an electric field is formed in the liquid crystal display panel according to the first embodiment of the present invention, the first angle θ1, which is an angle at which the liquid crystal molecules in the first liquid crystal cell Clc1 are raised, The sizes of the second angle θ2, which is the angle at which the liquid crystal molecules in the second liquid crystal cell Clc2 rise in response, are different from each other as shown in FIG. 4. In this case, since the magnitude of the first data voltage supplied to the first pixel electrode Ep1 is greater than the magnitude of the second data voltage supplied to the second pixel electrode Ep2, a larger electric field is applied to the first liquid crystal cell Clc1. The first angle θ1 is greater than the second angle θ2.

5 is a plan view illustrating a thin film transistor array substrate of a vertical field applied liquid crystal display panel according to a first exemplary embodiment of the present invention, and FIG. 6 is a line "II-II '" and "III-III'" of FIG. 5. It is sectional drawing which shows the thin film transistor array substrate cut along this.

5 and 6, the liquid crystal display panel according to the first embodiment of the present invention will be described in detail.

5 and 6, the thin film transistor array substrate according to the first exemplary embodiment of the present invention may include a gate line 102 and a data line formed on the lower substrate 145 to intersect with the gate insulating layer 146 therebetween. 104, the first and second thin film transistors 106 and 206 formed at each intersection thereof, and the first and second electrodes respectively formed with the isolation region 128 interposed therebetween in the cell region 105 provided in the intersection structure. The pixel electrodes 114 and 214, and the first and second storage capacitors 118 and 218 formed in an overlapping portion of the first and second pixel electrodes 114 and 214 and the storage electrode line 116 are provided.

The gate line 102 for supplying the scan pulse and the data line 104 for supplying the data voltage are formed in a cross structure to define the cell region 105.

The first thin film transistor 106 keeps the data voltage of the data line 104 charged and maintained in the first pixel electrode 114 in response to the scan pulse of the gate line 102. To this end, the first thin film transistor 106 includes a first gate electrode 108 connected to the gate line 102, a first source electrode 110 and a first pixel electrode 114 connected to the data line 104. The first drain electrode 112 connected to the () is provided. In addition, the first thin film transistor 106 overlaps with the first gate electrode 108 and the gate insulating layer 146 therebetween, and forms an active layer for forming a channel between the first source electrode 110 and the first drain electrode 112. 148 is further provided. The active layer 148 is also formed to overlap the data line 104. The data line 104, the first source electrode 110 and the first drain electrode 112 and the ohmic contact layer 150 for ohmic contact are further formed on the active layer 148.

The first pixel electrode 114 is formed in the cell region 105 by being connected to the first drain electrode 112 of the first thin film transistor 106 through the first contact hole 113 penetrating the passivation layer 152. .

The second thin film transistor 206 keeps the data voltage of the data line 104 charged and maintained in the second pixel electrode 214 in response to the scan pulse of the gate line 102. To this end, the second thin film transistor 206 includes a second gate electrode 208 connected to the gate line 102 and a second source formed by extending the first drain electrode 112 of the first thin film transistor 106. An electrode 210 and a second drain electrode 212 connected to the second pixel electrode 214 are provided. In addition, the second thin film transistor 206 is formed with an active layer 148 and an ohmic contact layer 150 extending from the first thin film transistor 106. The active layer 148 overlaps the second gate electrode 208 and the gate insulating layer 146 to form a channel between the second source electrode 210 and the second drain electrode 212. The ohmic contact layer 150 allows the active layer 148 to make ohmic contact with the second source electrode 210 and the second drain electrode 212.

The second pixel electrode 214 is connected to the second drain electrode 212 of the second thin film transistor 206 through the second contact hole 213 penetrating through the passivation layer 152, so that the first pixel of the cell region 105 is formed. The pixel electrode 114 is formed on one side.

A capacitor 120 is formed between the first and second thin film transistors 106 and 206. The capacitor 120 includes first and second capacitor electrodes 119 and 122 disposed with the gate insulating layer 145, the active layer 146, and the ohmic contact layer 150 interposed therebetween. The capacitor 120 has a data voltage supplied to the first drain electrode 112 through the data line 104 and the first source electrode 110 to the second source electrode 210 of the second thin film transistor 206. When supplied, it reduces the magnitude of the original data voltage supplied from the data line 104. Thus, when the second pixel electrode 214 is supplied with a lower data voltage than the first pixel electrode 114 to form a vertical electric field with the common electrode of the color filter array substrate (not shown), the second pixel electrode The liquid crystal molecules disposed in the region 214 have a lower rising angle than the liquid crystal molecules disposed in the region of the first pixel electrode 114. That is, the liquid crystal molecules in the area of the first pixel electrode 114 and the liquid crystal molecules in the area of the second pixel electrode 214 have different rising angles, so that the display quality does not significantly decrease even when viewed from various angles. In this case, it is effective to form different areas of the first pixel electrode 114 and the second pixel electrode 214.

The liquid crystal display panel according to the first exemplary embodiment of the present invention having the thin film transistor array substrate further includes a color filter array substrate (not shown). The color filter array substrate forms a vertical electric field together with the thin film transistor array substrate to drive the liquid crystal molecules injected into the space therebetween to express the gray level of the liquid crystal display device.

The first and second storage capacitors 118 and 218 overlap the portions of the first and second pixel electrodes 114 and 214 with the gate insulating layer 146 and the passivation layer 152 interposed therebetween. It consists of. The first and second storage capacitors 118 and 218 allow the data voltages charged in the first and second pixel electrodes 114 and 214 to remain stable until the next data voltage is supplied.

7A to 7D are views illustrating a method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention illustrated in FIG. 6.

7A to 7D are manufacturing methods using four mask processes, but the manufacturing method of the liquid crystal display panel according to the first exemplary embodiment of the present invention is irrelevant to the number of masks.

First, the gate line 102, the first and second gate electrodes 108 and 208, the first capacitor electrode 119 and the storage electrode line 116 are formed on the lower substrate 145 using the first mask process. A first conductive pattern group including the same is formed as shown in FIG. 7A.

In detail, the gate metal layer is formed on the lower substrate 145 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form the gate lines 102, the first and second thin film transistors 106 and 206, and the first and second gate electrodes 108. 208, a first conductive pattern group including a first capacitor electrode 119 constituting the capacitor 120, and a storage electrode line 116 constituting the first and second storage capacitors 118 and 218. Is formed. As the gate metal layer, a metal such as aluminum (Al), molybdenum (Mo), chromium (Cr), or the like is used as a single layer or a multilayer structure.

The gate insulating film 146 is coated on the lower substrate on which the first conductive pattern group is formed as shown in FIG. 7B. And a semiconductor pattern including the active layer 148 and the ohmic contact layer 150 on the gate insulating layer 146 using the second mask process, the data line 104, the first and second source electrodes 110 and 210. And a second conductive pattern group including the first and second drain electrodes 112 and 212 and the second capacitor electrode 122.

In detail, the gate insulating layer 146, the amorphous silicon layer, the n + amorphous silicon layer, and the source / drain metal layer are sequentially formed on the lower substrate 145 on which the first conductive pattern group is formed through a deposition method such as PECVD or sputtering. do. Here, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the material of the gate insulating film 146. As the source / drain metal layer, a metal such as aluminum (Al), molybdenum (Mo), chromium (Cr), titanium, tantalum, or molybdenum alloy (Mo alloy) is used in a single layer or multilayer structure.

Next, a photoresist pattern having a step is formed on the source / drain metal layer by a photolithography process using a second mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in each of the channel portions of the first and second thin film transistors 106 and 206 as the second mask, the height of the photoresist pattern of the channel portion is lower than that of other source / drain patterns. Have it.

Subsequently, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern, such that the data line 104, the first and second source electrodes 110 and 210, the first and second drain electrodes 112 and 212, The second conductive pattern group including the second capacitor electrode 122 is integrally formed.

The ohmic contact layer 150 and the active layer 148 are formed by simultaneously patterning the n + amorphous silicon layer and the amorphous silicon layer by a dry etching process using the same photoresist pattern.

Thereafter, the photoresist pattern having a relatively low height is removed from the channel portions by an ashing process, and then the source / drain metal pattern and the ohmic contact layer 150 of the channel portions are etched by the dry etching process. Accordingly, the active layers 148 of the channel portions are exposed to separate the first and second source electrodes 110 and 210 and the first and second drain electrodes 112 and 212, respectively, and the second conductive pattern is formed by a strip process. The photoresist pattern remaining on the group is removed.

A protective film 152 including the first and second contact holes 113 and 213 is formed on the gate insulating layer 146 on which the second conductive pattern group is formed as shown in FIG. 7C.

In detail, the passivation layer 152 is entirely formed on the gate insulating layer 146 on which the second conductive pattern group is formed by a deposition method such as PECVD. Subsequently, the protective layer 152 is patterned by a photolithography process and an etching process using a third mask to form first and second contact holes 113 and 213. The first contact hole 113 penetrates the passivation layer 152 to expose the first drain electrode 112, and the second contact hole 213 penetrates the passivation layer 152 to expose the second drain electrode 212. Let's do it.

As the material of the protective film 152, an inorganic insulating material such as the gate insulating film 146, an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, PFCB, or the like is used.

A third conductive pattern group including the first and second pixel electrodes 114 and 214 is formed on the passivation layer 152 as shown in FIG. 7D.

In detail, the transparent conductive film is apply | coated on the protective film 152 by the vapor deposition method, such as sputtering. Subsequently, the transparent conductive layer is etched through a photolithography process and an etching process using a fourth mask, thereby including a third conductive pattern group including the first and second pixel electrodes 114 and 214 with the separation region 128 interposed therebetween. Is formed. The first pixel electrode 114 is electrically connected to the first drain electrode 112 through the first contact hole 113, and the second pixel electrode 214 is connected to the second drain through the second contact hole 213. It is electrically connected to the electrode 212.

Herein, materials of the transparent conductive film include indium tin oxide (ITO), tin oxide (TO), indium tin zinc oxide (IZO), and indium zinc oxide (IZO). ) And the like are used.

As described above, the liquid crystal display panel according to the first embodiment of the present invention is formed by separating the pixel electrodes of the thin film transistor array substrate into the first and second pixel electrodes 114 and 214, thereby increasing the viewing angle of the liquid crystal display panel. have.

8 is a plan view illustrating a thin film transistor array substrate of a vertical field applied liquid crystal display panel according to a second exemplary embodiment of the present invention, and FIG. 9 is a line "IV-IV '" and "V-V'" of FIG. 8. It is sectional drawing which shows the thin film transistor array substrate cut along this.

8 and 9, the thin film transistor array substrate according to the second exemplary embodiment of the present invention may include a gate line 302 and a data line intersecting the gate insulating layer 346 over the lower substrate 345. 304, the first and second thin film transistors 306 and 406 formed at each intersection thereof, and the first and second electrodes respectively formed with the isolation region 328 interposed therebetween in the cell region 305 provided in the intersection structure. The pixel electrodes 314 and 414 and the storage electrodes 316 overlapping portions of edges of the first and second pixel electrodes 314 and 414 are provided.

The gate line 302 for supplying the scan pulse and the data line 404 for supplying the data voltage are formed in a cross structure to define the cell region 305.

The first thin film transistor 306 keeps the data voltage of the data line 304 charged and maintained in the first pixel electrode 314 in response to the scan pulse of the gate line 302. To this end, the first thin film transistor 306 may include a first gate electrode 308 connected to the gate line 302, a first source electrode 310 and a first pixel electrode 314 connected to the data line 304. ) Is provided with a first drain electrode 312. In addition, the first thin film transistor 306 overlaps the first gate electrode 308 with the gate insulating layer 346 therebetween, and forms an channel between the first source electrode 310 and the first drain electrode 312. 348 is further provided. The active layer 348 is also formed to overlap the data line 304. The data line 304, the first source electrode 310 and the first drain electrode 312 and the ohmic contact layer 350 for ohmic contact are further formed on the active layer 348.

The first pixel electrode 314 is connected to the first drain electrode 312 of the first thin film transistor 306 through the first contact hole 313 passing through the passivation layer 352 and is formed in the cell region 305. .

The second thin film transistor 406 maintains the data voltage of the data line 304 charged to the second pixel electrode 414 in response to the scan pulse of the gate line 402. To this end, the second thin film transistor 406 includes a second gate electrode 408 connected to the gate line 302 and a second source formed by extending the first drain electrode 312 of the first thin film transistor 306. An electrode 410 and a second drain electrode 412 connected to the second pixel electrode 414 are provided. In addition, an active layer 348 and an ohmic contact layer 350 extending from the first thin film transistor 306 are formed in the second thin film transistor 406. The active layer 348 overlaps the second gate electrode 408 and the gate insulating layer 346 to form a channel between the second source electrode 410 and the second drain electrode 412. The ohmic contact layer 350 allows the active layer 348 to make ohmic contact with the second source electrode 410 and the second drain electrode 412.

The second pixel electrode 414 is connected to the second drain electrode 412 of the second thin film transistor 406 through the second contact hole 413 penetrating the passivation layer 352, so that the first pixel of the cell region 305 is formed. The pixel electrode 314 is formed on one side.

A capacitor 320 is formed between the first and second thin film transistors 306 and 406. The capacitor 320 includes first and second capacitor electrodes 319 and 322 disposed with the gate insulating layer 345, the active layer 346, and the ohmic contact layer 350 interposed therebetween. The capacitor 320 has a data voltage supplied to the first drain electrode 312 through the data line 304 and the first source electrode 310 to the second source electrode 410 of the second thin film transistor 406. When supplied, it reduces the magnitude of the original data voltage supplied from the data line 304. Thus, when the second pixel electrode 414 is supplied with a lower data voltage than the first pixel electrode 314 to form a vertical electric field with the common electrode of the color filter array substrate (not shown), the second pixel electrode The liquid crystal molecules disposed in the region 414 have a lower rising angle than the liquid crystal molecules disposed in the region of the first pixel electrode 314. That is, the liquid crystal molecules in the region of the first pixel electrode 414 and the liquid crystal molecules in the region of the second pixel electrode 414 have different rising angles, so that the display quality does not significantly decrease even when viewed from various angles. In this case, the areas of the first pixel electrode 314 and the second pixel electrode 414 may be formed to be different from each other as in the liquid crystal display panel according to the first embodiment of the present invention.

The storage electrode 316 receives a storage voltage and overlaps a portion of the first side of each of the first and second pixel electrodes 314 and 414 with the storage electrode line 316a, the data line 304, and the first pixel electrode ( The first storage electrode 316b overlapping the first pixel electrode 314 between the 314 and the separation region 328, and overlapping the first and second pixel electrodes 314 near the separation region 328. A second storage electrode 316c, and a third storage electrode 316d overlapping the second pixel electrode 414 between the neighboring data line and the second pixel electrode 414. The first to third storage electrodes 316b to 316d are connected to the storage electrode line 316a. A gate insulating film 346 and a protective film 352 are formed between the storage electrode 316 and the first and second pixel electrodes 314 and 414.

The storage electrode 316 forms a storage capacitor at a portion overlapping with the first and second pixel electrodes 314 and 414, so that the data voltages charged in the first and second pixel electrodes 314 and 414 are respectively the next data. Keep stable until voltage is applied.

In addition, the storage electrode 316 according to the second embodiment of the present invention may be formed around the first and second pixel electrodes 314 and 414 to improve a problem such as light leakage. In particular, when the storage electrode is formed in the separation region 328 as in the first embodiment, the separation region 328 corresponds to the separation region 328 in order to solve problems such as light leakage and disclination. A black matrix must be formed on the color pulp array substrate. However, when the black matrix is formed, the aperture ratio of the liquid crystal display panel is reduced because the black matrix should be formed wider than the separation region 328 in consideration of the bonding margin. On the other hand, when the storage electrode is formed as in the second embodiment of the present invention, it is not necessary to form a black matrix, which is effective in the aperture ratio.

The liquid crystal display panel according to the second exemplary embodiment of the present invention having the thin film transistor array substrate further includes a color filter array substrate (not shown). The color filter array substrate forms a vertical electric field together with the thin film transistor array substrate to drive the liquid crystal molecules injected into the space therebetween to express the gray level of the liquid crystal display device.

FIG. 10 is a diagram illustrating another example of the storage electrode 316 illustrated in FIG. 8.

Since the thin film transistor array substrate shown in FIG. 10 is the same except that the second storage electrode 316c is removed from the thin film transistor array substrate of FIG. 8, the same reference numerals will be given, and detailed descriptions thereof will be omitted. . In the thin film transistor array substrate illustrated in FIG. 10, the storage electrode 316 is not disposed in the isolation region 328 as in the first embodiment of the present invention, thereby improving light leakage at the edge of the cell region 305. . In this case, a black matrix is formed on a portion of the color filter array substrate bonded to the thin film transistor array substrate illustrated in FIG. 10 in order to improve light leakage and replacement of the isolation region 328.

11A through 11D are views illustrating a method of manufacturing a thin film transistor array substrate according to the second embodiment of the present invention illustrated in FIG. 8.

11A to 11D are manufacturing methods using four mask processes, but the manufacturing method of the liquid crystal display panel according to the second exemplary embodiment of the present invention is independent of the number of masks.

First, a gate line 302, first and second gate electrodes 308 and 408, a first capacitor electrode 319, and a storage electrode 316 are included on a lower substrate 345 using a first mask process. A first conductive pattern group is formed as shown in FIG. 11A.

In detail, the gate metal layer is formed on the lower substrate 345 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form the gate lines 302 and the first and second thin film transistors 306 and 406. , A first conductive pattern group including a first capacitor electrode 319 constituting the capacitor 320, and a storage electrode 316 is formed. As the gate metal layer, a metal such as aluminum (Al), molybdenum (Mo), chromium (Cr), or the like is used as a single layer or a multilayer structure.

The gate insulating film 346 is coated on the lower substrate on which the first conductive pattern group is formed as shown in FIG. 11B. The semiconductor pattern including the active layer 348 and the ohmic contact layer 350 on the gate insulating layer 346 using the second mask process, the data line 304, the first and second source electrodes 310 and 410. The second conductive pattern group including the first and second drain electrodes 312 and 412 and the second capacitor electrode 322 is formed.

In detail, the gate insulating layer 346, the amorphous silicon layer, the n + amorphous silicon layer, and the source / drain metal layer are sequentially formed on the lower substrate 345 on which the first conductive pattern group is formed through a deposition method such as PECVD or sputtering. do. Here, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the material of the gate insulating film 346. As the source / drain metal layer, a metal such as aluminum (Al), molybdenum (Mo), chromium (Cr), titanium, tantalum, or molybdenum alloy (Mo alloy) is used in a single layer or multilayer structure.

Next, a photoresist pattern having a step is formed on the source / drain metal layer by a photolithography process using a second mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in each of the channel portions of the first and second thin film transistors 306 and 406 as the second mask, the height of the photoresist pattern of the channel portion is lower than that of other source / drain patterns. Have it.

Subsequently, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern, such that the data line 304, the first and second source electrodes 310 and 410, the first and second drain electrodes 312 and 412, The second conductive pattern group including the second capacitor electrode 322 is integrally formed.

In addition, the ohmic contact layer 350 and the active layer 348 are formed by simultaneously patterning the n + amorphous silicon layer and the amorphous silicon layer by a dry etching process using the same photoresist pattern.

Thereafter, the photoresist pattern having a relatively low height is removed from the channel portions by an ashing process, and then the source / drain metal pattern and the ohmic contact layer 350 of the channel portions are etched by the dry etching process. Accordingly, the active layers 348 of the channel portions are exposed to separate the first and second source electrodes 310 and 410 and the first and second drain electrodes 312 and 412, respectively, and the second conductive pattern is formed by a strip process. The photoresist pattern remaining on the group is removed.

A passivation layer 352 including first and second contact holes 313 and 413 is formed on the gate insulating layer 346 on which the second conductive pattern group is formed using the third mask process as illustrated in FIG. 11C.

In detail, the passivation layer 352 is entirely formed on the gate insulating layer 346 on which the second conductive pattern group is formed by a deposition method such as PECVD. Subsequently, the passivation layer 352 is patterned by a photolithography process and an etching process using a third mask to form first and second contact holes 313 and 413. The first contact hole 313 penetrates the passivation layer 352 to expose the first drain electrode 312, and the second contact hole 413 penetrates the passivation layer 352 to expose the second drain electrode 412. Let's do it.

As the material of the protective film 352, an inorganic insulating material such as the gate insulating film 346, an acrylic insulating compound having a low dielectric constant, or an organic insulating material such as BCB or PFCB may be used.

A third conductive pattern group including the first and second pixel electrodes 314 and 414 is formed on the passivation layer 352 as illustrated in FIG. 11D.

In detail, the transparent conductive film is coated on the protective film 352 by a deposition method such as sputtering. Subsequently, the transparent conductive layer is etched through a photolithography process and an etching process using a fourth mask, thereby including a third conductive pattern group including the first and second pixel electrodes 314 and 414 with an isolation region 328 therebetween. Is formed. The first pixel electrode 314 is electrically connected to the first drain electrode 312 through the first contact hole 313, and the second pixel electrode 414 is connected to the second through the second contact hole 413. It is electrically connected to the drain electrode 412.

Herein, materials of the transparent conductive film include indium tin oxide (ITO), tin oxide (TO), indium tin zinc oxide (IZO), and indium zinc oxide (IZO). ) And the like are used.

In the liquid crystal display panels according to the first and second embodiments of the present invention, two pixel electrodes are formed in one cell region to receive a data voltage through each thin film transistor, but as illustrated in FIG. The electrode may supply the data voltage through the thin film transistor, and the other pixel electrode may receive the data voltage through a capacitor formed to overlap the pixel electrode.

12 is a circuit diagram schematically illustrating a liquid crystal display panel according to a third exemplary embodiment of the present invention.

Referring to FIG. 12, a liquid crystal display panel according to a third exemplary embodiment of the present invention may include a thin film transistor TFT and a first node in a cell region defined by a data line DL and a gate line GL that cross each other. The first pixel electrode Ep1 connected to N1, the second pixel electrode Ep2 connected to the second node N2 and separated from the first pixel electrode Ep1, and the first node N1 and the second The capacitor C is connected between the nodes N2.

The TFT supplies the first data voltage from the data line DL to the first node N1 in response to the scan pulse from the gate line GL, and the first data voltage is reduced by the capacitor C to obtain the first data voltage. It is supplied to the second node N2 as a second data voltage. The second node N2 supplies a second data voltage to the second pixel electrode Ep2.

The first liquid crystal cell Clc1 and the second liquid crystal cell Clc2 are disposed between the common electrode Ec to which the common voltage is supplied, and the first and second pixel electrodes Ep1 and Ep2, respectively. It is driven by an electric field formed between the first and second pixel electrodes Ep1 and Ep2.

The liquid crystal display panel according to the third embodiment of the present invention further includes a storage electrode Est. The storage electrode Est overlaps the first pixel electrode Ep1 to form a first storage capacitor Cst1, and the storage electrode Est overlaps the second pixel electrode Ep1 to form a second storage capacitor Cst2. The first storage capacitor Cst1 charges the first data voltage supplied to the first pixel electrode Ep1, and the second storage capacitor Cst2 charges the second data voltage supplied to the second pixel electrode Ep2. Done.

In the third embodiment of the present invention, the second pixel electrode Ep2, which receives the second data voltage through the capacitor C, is supplied to the first pixel electrode Ep1 as in the first and second embodiments. By receiving the second data voltage relatively lower than the one data voltage, the same effects as those shown in the first and second embodiments of the present invention can be obtained.

As described above, the liquid crystal display panel and the method of manufacturing the same according to the present invention improve the viewing angle by differently adjusting the rising angle of the liquid crystal molecules by forming pixel electrodes receiving different data voltages in one cell region. In addition, the liquid crystal display panel and a method of manufacturing the same according to the present invention can minimize the occurrence of light leakage and the position by disposing the storage electrode between the pixel electrodes.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (28)

A plurality of data lines; A plurality of gate lines intersecting the data lines; And A plurality of cells defined by the data line and the gate line, Each of the cells is a first pixel electrode connected to a first node, a second pixel electrode connected to a second node and separated from the first pixel electrode, and a first pixel electrode from the data line in response to a scan pulse from the gate line. A first thin film transistor supplying a first data voltage to the first node, a second thin film transistor supplying a second data voltage of the second node to the second pixel electrode in response to the scan pulse; A capacitor connected between two nodes to determine the second data voltage supplied to the second node, a first storage capacitor formed between the first pixel electrode and a storage electrode to which the storage voltage is supplied, and the second pixel electrode And a second storage capacitor formed between the storage electrode and the storage electrode. The method of claim 1, The storage electrode overlaps the first storage electrode overlapping the first pixel electrode between the first data line and the first pixel electrode, and the first and second pixel electrodes respectively between the first and second pixel electrodes. A second storage electrode, a third storage electrode overlapping the second pixel electrode between the second data electrode and the second data line adjacent to the first data line, and the first to third storage electrodes And a storage electrode line for connecting. The method of claim 1, The storage electrode may include a first storage electrode overlapping the first pixel electrode between a first data line and the first pixel electrode, a second data line adjacent to the first data line, and the second pixel electrode. And a second storage electrode overlapping the second pixel electrode, and a storage electrode line connecting the first and second storage electrodes. The method of claim 1, And the storage electrode includes a storage electrode line that crosses the first and second pixel electrodes and overlaps the first and second pixel electrodes. The method according to any one of claims 2 to 4, And the storage electrode comprises an opaque metal. The method of claim 1, And the second data voltage is a voltage at which the first data voltage is reduced by the capacitor. The method of claim 1, The area of the first pixel electrode and the second pixel electrode are formed differently from each other. The method of claim 1, And the first data voltage and the second data voltage have different values. A plurality of data lines; A plurality of gate lines intersecting the data lines; And A plurality of cells defined by the data line and the gate line, Each of the cells is a first pixel electrode connected to a first node, a second pixel electrode connected to a second node and separated from the first pixel electrode, and a first pixel electrode from the data line in response to a scan pulse from the gate line. A thin film transistor for supplying a first data voltage to the first node, a capacitor connected between the first and second nodes to determine a second data voltage supplied to the second node, the first pixel electrode, and a storage voltage And a second storage capacitor formed between the supplied storage electrodes, and a second storage capacitor formed between the second pixel electrode and the storage electrode. The method of claim 9, The storage electrode overlaps the first storage electrode overlapping the first pixel electrode between the first data line and the first pixel electrode, and the first and second pixel electrodes respectively between the first and second pixel electrodes. A second storage electrode, a third storage electrode overlapping the second pixel electrode between the second data line adjacent to the first data line, and the second pixel electrode, and the first to third storage electrodes; And a storage electrode line. The method of claim 9, The storage electrode may include a first storage electrode overlapping the first pixel electrode between a first data line and the first pixel electrode, a second data line adjacent to the first data line, and the second pixel electrode. And a second storage electrode overlapping the second pixel electrode, and a storage electrode line connecting the first and second storage electrodes. The method of claim 9, And the storage electrode includes a storage electrode line that crosses the first and second pixel electrodes and overlaps the first and second pixel electrodes. The method according to any one of claims 10 to 12, And the storage electrode comprises an opaque metal. The method of claim 9, And the second data voltage is a voltage at which the first data voltage is reduced by the capacitor. The method of claim 9, The area of the first pixel electrode and the second pixel electrode are formed differently from each other. The method of claim 9, And the first data voltage and the second data voltage have different values. A gate line on a substrate, a first gate electrode of a first thin film transistor connected to the gate line, a first capacitor electrode connected to the gate line, a second gate electrode of a second thin film transistor connected to the gate line, and Forming a first conductive pattern group including a storage electrode; Forming a gate insulating film on the substrate on which the first conductive pattern group is formed; A data line crossing the gate line insulated from the gate line, a first source electrode of the first thin film transistor connected to the data line, a first drain electrode of the first thin film transistor facing the first source electrode, and the first A second capacitor electrode connected to the drain electrode, a second source electrode of the second thin film transistor connected to the second capacitor electrode, and a second drain electrode of the second thin film transistor facing the second source electrode. Forming a semiconductor layer forming a second conductive pattern group and channel portions of the first and second thin film transistors; Forming a passivation layer including a first contact hole and a second contact hole on the gate insulating layer on which the second conductive pattern group and the semiconductor layer are formed; And Forming a third conductive pattern group including a first pixel electrode connected to the first drain electrode through the first contact hole, and a second pixel electrode connected to the second drain electrode through the second contact hole Method of manufacturing a liquid crystal display panel comprising the step of. The method of claim 17, The storage electrode overlaps the first storage electrode overlapping the first pixel electrode between the first data line and the first pixel electrode, and the first and second pixel electrodes respectively between the first and second pixel electrodes. A second storage electrode, a third storage electrode overlapping the second pixel electrode between the second data line adjacent to the first data line, and the second pixel electrode, and the first to third storage electrodes; A storage electrode line is provided. The method of claim 17, The storage electrode may include a first storage electrode overlapping the first pixel electrode between a first data line and the first pixel electrode, a second data line adjacent to the first data line, and the second pixel electrode. And a second storage electrode overlapping the second pixel electrode, and a storage electrode line connecting the first and second storage electrodes. The method of claim 17, And the storage electrode includes a storage electrode line crossing the first and second pixel electrodes and overlapping the first and second pixel electrodes. The method according to any one of claims 18 to 20, And the storage electrode comprises an opaque metal. The method of claim 17, The area of the first pixel electrode and the second pixel electrode are formed differently from each other. Forming a first conductive pattern group including a gate line, a gate electrode of a thin film transistor connected to the gate line, a first capacitor electrode connected to the gate line, and a storage electrode on a substrate; Forming a gate insulating film on the substrate on which the first conductive pattern group is formed; A data line crossing the gate line to be insulated from the gate line, a source electrode of the thin film transistor connected to the data line, a drain electrode of the thin film transistor facing the source electrode, and a second capacitor electrode connected to the drain electrode. Forming a semiconductor layer forming a second conductive pattern group and a channel portion of the thin film transistor; Forming a passivation layer including a first contact hole and a second contact hole on the gate insulating layer on which the second conductive pattern group and the semiconductor layer are formed; And Forming a third conductive pattern group including a first pixel electrode connected to the drain electrode through the first contact hole, and a second pixel electrode connected to the second capacitor electrode through the second contact hole Method of manufacturing a liquid crystal display panel comprising the step. The method of claim 23, The storage electrode overlaps the first storage electrode overlapping the first pixel electrode between the first data line and the first pixel electrode, and the first and second pixel electrodes respectively between the first and second pixel electrodes. A second storage electrode, a third storage electrode overlapping the second pixel electrode between the second data line adjacent to the first data line, and the second pixel electrode, and the first to third storage electrodes; A storage electrode line is provided. The method of claim 23, The storage electrode may include a first storage electrode overlapping the first pixel electrode between a first data line and the first pixel electrode, a second data line adjacent to the first data line, and the second pixel electrode. And a second storage electrode overlapping the second pixel electrode, and a storage electrode line connecting the first and second storage electrodes. The method of claim 23, And the storage electrode includes a storage electrode line crossing the first and second pixel electrodes and overlapping the first and second pixel electrodes. The method according to any one of claims 24 to 26, And the storage electrode comprises an opaque metal. The method of claim 23, The area of the first pixel electrode and the second pixel electrode are formed differently from each other.

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