KR20080051627A - Thin film transistor and thin film transistor array panel comprising same - Google Patents

Abstract

Provided are a thin film transistor capable of realizing uniform display characteristics, and a thin film transistor array panel including the thin film transistor. The thin film transistor includes a channel region having a plurality of protrusions crystallized on an insulating substrate and extending in a first direction and inclined at a first angle with respect to a source region, a drain region, and a second direction perpendicular to the first direction. A gate line arranged in the second direction, the gate line having a semiconductor layer formed on the semiconductor layer and inclined at a second angle with respect to the first direction, and a source electrode and a drain electrode respectively connected to the source region and the drain region. Include.

Description

Thin film transistor and thin film transistor display panel including same {Thin film transistor and thin film transistor panel having the same}

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line AA ′ of the thin film transistor array panel of FIG. 1.

3 illustrates a sequential solidification apparatus used to manufacture a thin film transistor array panel according to an exemplary embodiment of the present invention.

4 illustrates the mask of FIG. 3 in detail.

5A and 5B are plan views illustrating a substrate for explaining a process of crystallizing amorphous silicon using the crystallization apparatus of FIG. 3.

(Explanation of symbols for the main parts of the drawing)

110: substrate material 111: buffer layer

130: semiconductor layer 131: channel region

132a, 132b: low concentration doped drain region

133a: source region 133b: drain region

136: gate line 137: projection line

141: gate insulating film 151: gate electrode

152: interlayer insulating film 161: source electrode

162: drain electrode 171: protective film

172: pixel electrode 181: first contact hole

182: second contact hole 183: third contact hole

200; Crystallization device 210: light source

220: attenuator 230,232,234: reflector

240: focusing lens 250: mask

251a: first pattern 251b: second pattern

252: transmission region 253a, 253b: boundary portion

255: blocking region 257: crystallization region

260: image lens 270: substrate

280: move stage

The present invention relates to a thin film transistor and a thin film transistor array panel including the same, and more particularly, to a thin film transistor formed of polycrystalline silicon and having uniform display characteristics, and a thin film transistor array panel including the same.

 The thin film transistor substrate is used as a substrate such as a liquid crystal display device or an organic EL display device having pixels in a matrix array.

A liquid crystal display is composed of two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and applies a voltage to the electrodes to rearrange the liquid crystal molecules of the liquid crystal layer to determine the amount of light transmitted. As a device for adjusting, a thin film transistor is used as a switching element for controlling an image signal transmitted to an electrode.

An organic EL display device displays an image by electrically exciting and emitting a fluorescent organic material, and includes a driving thin film transistor and a switching thin film transistor that supply a current for emitting light to each pixel. Unlike the liquid crystal display device, such an organic EL display device is a self-luminous display, which can realize a wide viewing angle, a fast response speed, and the like, thus attracting attention as a next-generation display candidate.

The thin film transistor substrate used in such a display device includes amorphous silicon or polycrystalline silicon as the semiconductor layer of the channel portion. Among them, polycrystalline silicon has excellent electrical characteristics and good stability in the channel portion, and is used in high-performance liquid crystal display devices and organic EL display devices.

On the other hand, polycrystalline silicon is derived from amorphous silicon, which is a method of depositing or heat-treating amorphous silicon at a high temperature, but recently, a sequential lateral solidification process (SLS) capable of low temperature processing has been studied. It is becoming. The sequential lateral solidification technique takes advantage of the fact that silicon particles grow at the interface between liquid and solid silicon in a direction perpendicular to the interface, and shift the magnitude of the laser beam energy and the shift of the irradiation range of the laser beam to an optical system. And crystallizing the amorphous silicon by appropriately adjusting the mask to laterally grow the silicon particles by a predetermined length.

The characteristic feature of the sequential side solid crystallization is that the crystals growing in the opposite direction meet and form protrusions, which cause the quality of the display device to be poor due to the interruption of current flow.

An object of the present invention is to provide a thin film transistor capable of realizing uniform display characteristics.

Another object of the present invention is to provide a thin film transistor array panel including the thin film transistor.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an embodiment of the present invention, a thin film transistor includes a plurality of protrusions that are crystallized on an insulating substrate and extend in a first direction and are perpendicular to a source region, a drain region, and a first direction. A semiconductor layer including a channel region inclined at a first angle with respect to two directions, a gate line having a gate electrode formed at a second angle with respect to the first direction on the semiconductor layer, and arranged in a second direction; A source electrode and a drain electrode connected to the source region and the drain region, respectively.

In addition, a thin film transistor array panel according to another embodiment of the present invention for achieving the above technical problem is crystallized on the insulating substrate and the insulating substrate and provided with a plurality of protrusions in the first direction, the source region, the drain region and the first direction and the like. A semiconductor layer including a channel region formed to be inclined at a second angle perpendicular to the first direction, a gate insulating film formed on the semiconductor layer, and a gate electrode formed to be inclined at a second angle with respect to the first direction on the gate insulating film; And an interlayer insulating film having a gate line arranged in a second direction, and first and second contact holes formed on the gate electrode and exposing a source region and a drain region. A source electrode and a drain electrode electrically connected to the source region and the drain region through the contact hole, respectively, the source electrode and the drain electrode And a pixel electrode formed on the passivation layer and having a third contact hole exposing the drain electrode, and a pixel electrode formed on the passivation layer and electrically connected to the drain electrode through the third contact hole.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention;

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

As illustrated in FIG. 1, the semiconductor layer 130 crystallized on an insulating substrate (not shown) includes a plurality of protrusion rows 137 extending in a first direction, and include a source region 133a and a drain region 133b. And a channel region 131 inclined at a first angle θ1 in a second direction perpendicular to the first direction. In addition, the gate line 136 includes a gate electrode 151 formed to be inclined at a second angle θ2 with respect to the first direction. The source electrode 161 and the drain electrode 162 connect the source region 133a and the drain region 133b. In this case, the semiconductor layer 130 is formed of a polycrystalline silicon layer, and the protrusion 137 is located at a grain boundary of the polycrystalline silicon layer.

In this case, the first direction corresponds to the plurality of extended protrusion lines 137 and the second direction is the same as the gate line 136. At this time, the first angle θ1 is formed to be inclined within a range of more than 0 ° and less than 20 °.

The channel region 131 includes the lightly doped drain regions 132a and 132b, and the lightly doped drain regions 132a and 132b are formed to be aligned with the gate electrode 151.

In this case, the gate electrode 151 is formed by the second angle θ2 within a range of greater than 0 ° and less than 20 ° with respect to the first direction. The lightly doped drain regions 132a and 132b formed in alignment with the gate electrode 151 thus formed are formed on both sides of the gate electrode 151, and the protrusions 137 having substantially the same number of protrusions 137 are formed. Here, the projection lines 137 of the lightly doped drain regions 132a and 132b are formed by a sequential lateral solidification method.

First, the sequential solidification method will be described with reference to FIGS. 3 to 5B.

 The crystallization apparatus 200 used for the present invention includes a light source 210, an attenuator 220, a focus lens 240, a mask 250, an imaging lens 260, In addition, a translation stage 280 on which the substrate 270 containing amorphous silicon is disposed is sequentially arranged, between the attenuator 220 and the focus lens 240, and between the imaging lens 260 and the movement stage 280. The plurality of reflectors 230, 232, and 234 for reflecting the incident light at a predetermined angle to change the direction of the light are respectively disposed between the?

4 illustrates the mask of FIG. 3 in detail.

In this case, the first pattern 251a has a shape in which the transmission region and the blocking region are alternately disposed in the column direction and extend in the horizontal direction. In the second pattern 251 b, the transmission region 252 and the blocking region 255 are alternately disposed, and are formed in a reverse phase with the first pattern 251 a.

The transmission region 252 is made transparent so that the laser beam can pass therethrough. The blocking region 255 is formed of a light shielding film so that the laser beam does not transmit when the laser beam is irradiated. When irradiating a laser beam, crystals grow laterally at both interfaces of the molten amorphous silicon film, and the crystals of each side grown stop the growth as the grain boundaries collide with each other.

5A is a plan view illustrating a crystallization direction of an amorphous silicon thin film according to laser beam irradiation. 5B is a plan view illustrating a crystal shape of an amorphous silicon thin film according to the laser beam irradiation of FIG. 3.

As shown in FIG. 5A, silicon is crystallized by irradiating a laser beam onto a substrate on which an amorphous silicon film is formed using the mask of FIG. 4. At this time, since the crystallization is performed only in the portion exposed to the laser beam, the crystallization proceeds only in the region corresponding to the transmission region of the mask, and stops at the boundary where different crystals meet from the edge. Hereinafter, referring to FIG. 5B, a crystal shape is grown by crystallization after irradiating a laser beam. As mentioned above, crystal growth stops at the boundary where different crystals meet.

The polycrystalline silicon layer manufactured as described above is partially patterned and used as the semiconductor layer 130.

Hereinafter, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2.

FIG. 2 is a cross-sectional view taken along the line AA ′ of the thin film transistor array panel of FIG. 1.

1 and 2, the buffer layer 111 is formed on the substrate material 110, and has a plurality of protrusion rows 137 in the crystallized first direction, and includes a source region 133a, a drain region 133b, The semiconductor layer 130 including the channel region 131 formed to be inclined at a first angle θ1 and in a second direction perpendicular to the first direction is formed. A gate insulating film 141 is formed on the semiconductor layer 130, and a gate electrode 151 is inclined at a first angle θ2 with respect to the first direction on the gate insulating film 141, and the second direction is provided. Gate lines 136 arranged in a row are formed.

In addition, an interlayer insulating layer 152 having first and second contact holes 181 and 182 exposing the source region 133a and the drain region 133b is formed on the gate electrode 151. The source electrode 161 and the drain electrode 162 electrically connected to the source region 133a and the drain region 133b are formed on the interlayer insulating layer 152 through the first and second contact holes 181 and 182, respectively. It is.

A passivation layer 171 having a third contact hole 183 exposing the drain electrode 162, and formed on the passivation layer 171 and electrically connected to the drain electrode 162 through the third contact hole 183. The pixel electrode 172 is formed.

Here, the characteristic of the sequential lateral solidification method used in manufacturing the semiconductor layer 130 is that the crystals growing in the opposite direction meet to form a plurality of protrusions 137, which prevents the flow of current. It may cause a poor quality of the display device or a bad characteristic. There is a method of tilting a mask to form crystallization in the sequential side-solidification method in order to be less affected by the protrusions 137. However, this has some equipment difficulties. In addition, when the crystal grows, the portion where the crystal overlaps with the crystal must be kept constant. If the overlap portion is misaligned, the characteristics of the thin film transistor are changed. To compensate for this, the channel region 131 is tilted at a predetermined angle to be patterned. Such patterning reduces image quality defects and characteristic defects caused by the protrusions 137 formed in the sequential side solidification method. In addition, the tilting of the mask used in the sequential solidification method overcomes the difficulties in using the equipment and overlaps the parts so that the parts are constantly maintained, thereby improving the superiority of the channel region 131. In addition, substantially the same number of protrusions 137 of the lightly doped drain regions 132a and 132b are formed to improve the superiority of the channel region 131. In this case, when the gate electrode 151 is formed, the pattern of the channel region 131 is patterned at an angle in substantially the same manner as the patterning for forming the channel region 131, thereby reducing the influence of the protrusion 137 and improving the channel superiority.

As described above, the embodiments of the present invention have been described to be formed at an angle to the channel region 131 in each semiconductor layer. However, the present invention is not limited thereto and may be manufactured in various forms. Those skilled in the art will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, according to the thin film transistor and the thin film transistor array panel including the same, it is possible to prevent the boundary portion formed by silicon crystal growth from being recognized as unevenness. Therefore, by using the polycrystalline silicon film formed by this method, a thin film transistor having high field effect mobility and uniform characteristics can be made.

In addition, when fabricating a thin film transistor substrate of a liquid crystal display using the polycrystalline silicon film formed by the present invention, a driving circuit including a device such as CMOS can be formed together on the thin film transistor substrate, thereby reducing manufacturing costs and processes. You can.

Claims (12)

A semiconductor comprising a plurality of protrusions crystallized on an insulating substrate and extending in a first direction, and including a source region, a drain region, and a channel region inclined at a first angle with respect to a second direction perpendicular to the first direction. layer; A gate line on the semiconductor layer, the gate line having a gate electrode inclined at a second angle with respect to the first direction and arranged in the second direction; And And a source electrode and a drain electrode connected to the source region and the drain region, respectively. According to claim 1, And the semiconductor layer is formed of a polycrystalline silicon layer, and the protrusions are positioned at grain boundaries of the polycrystalline silicon layer. According to claim 1, The first angle is a thin film transistor having a range of more than 0 ° and less than 20 °. According to claim 1, The semiconductor layer may include a lightly doped drain region formed in alignment with the gate electrode in the channel region. The method of claim 4, wherein And the lightly doped drain regions are formed on both sides of the gate electrode, and the pair of lightly doped drain regions are formed with substantially the same number of protrusions. According to claim 1, The second angle is a thin film transistor having a range of more than 0 ° and less than 20 °. Insulating substrate; A semiconductor layer crystallized on the insulating substrate, the semiconductor layer having a plurality of protrusion rows in a first direction, and including a source region and a drain region inclined at a first angle and a second direction perpendicular to the first direction; A gate insulating film formed on the semiconductor layer; A gate line on the gate insulating layer, the gate electrode being inclined at a second angle with respect to the first direction and arranged in the second direction; An interlayer insulating layer formed on the gate electrode and having first and second contact holes exposing the source region and the drain region; A source electrode and a drain electrode formed on the interlayer insulating layer and electrically connected to the source region and the drain region through the first and second contact holes, respectively; A passivation layer formed on the source electrode and the drain electrode and having a third contact hole exposing the drain electrode; And And a pixel electrode formed on the passivation layer and electrically connected to the drain electrode through the third contact hole. The method of claim 7, wherein The semiconductor layer may include a polycrystalline silicon layer, and the projection lines may be disposed at grain boundaries of the polycrystalline silicon layer. The method of claim 7, wherein The first angle has a thin film transistor array panel having a range of more than 0 ° and less than 20 °. The method of claim 7, wherein The semiconductor layer may include a lightly doped drain region formed in alignment with the gate electrode in the channel region. The method of claim 10, The low concentration doped drain regions are formed on both sides of the gate electrode, and the pair of low concentration doped drain regions each include a substantially same number of the projection lines. The method of claim 7, wherein The second angle has a range of greater than 0 ° and less than 20 °.

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