KR20080048936A - Method of manufacturing oxide thin film transistor substrate and oxide thin film transistor substrate - Google Patents

Abstract

A method of manufacturing an oxide thin film transistor substrate is provided. In the method of manufacturing an oxide thin film transistor substrate, a gate wiring is formed on an insulating substrate, and a stacked structure of an oxide semiconductor pattern and a data wiring is formed on the gate wiring, wherein the oxide semiconductor pattern is divided into a first region and a second region. The thickness of the first region is formed to be thinner than the thickness of the second region, and the data line is formed on the second region.

Description

Method of manufacturing of oxide thin film transistor array substrate and oxide thin film transistor array substrate}

The present invention relates to a method for manufacturing an oxide thin film transistor substrate and an oxide thin film transistor substrate manufactured by the same, and more particularly, to a method and a substrate for manufacturing an oxide thin film transistor having a high charge mobility and a high on / off current ratio.

As the size and quality of liquid crystal display devices continue to increase, there is a demand for improving electrical characteristics of thin film transistors that drive liquid crystals. In the case of the conventional thin film transistor, hydrogenated amorphous silicon (a-Si: H) was used as a semiconductor film in which a channel is formed.

In the case of hydrogenated amorphous silicon, the charge mobility and the on / off current ratio are relatively low. In addition, the optical band gap of the hydrogenated amorphous silicon is about 1.8 eV, which causes leakage photocurrent from the backlight unit and afterimages caused by an increase in dangling bonds. have.

An object of the present invention is to provide a method for manufacturing an oxide thin film transistor substrate having an oxide thin film transistor of excellent characteristics.

Another object of the present invention is to provide an oxide thin film transistor substrate having an oxide thin film transistor having excellent characteristics.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

In the method of manufacturing the oxide thin film transistor substrate according to the embodiments of the present invention for achieving the above technical problem, a gate wiring is formed on an insulating substrate, and a stacked structure of an oxide semiconductor film pattern and a data wiring is formed on the gate wiring. The oxide semiconductor film pattern may be divided into a first region and a second region, and the thickness of the first region may be smaller than that of the second region, and the data line may be formed on the second region. The oxide thin film transistor substrate according to the embodiments of the present invention for achieving the above another technical problem is a gate wiring formed on an insulating substrate, an oxide semiconductor pattern formed on the gate line, the first region and An oxide semiconductor pattern divided into a second region, wherein a thickness of the first region is thinner than a thickness of the second region, The first comprises a data line formed on the second region.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only the embodiments make the disclosure of the present invention complete, and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Although the first, second, etc. are used to describe various elements, components, regions, wirings, layers and / or sections, these elements, components, regions, wirings, layers and / or sections are defined by these terms. Of course, it is not limited. These terms are only used to distinguish one element, component, region, wiring, layer or section from another element, component, region, wiring, layer or section. Accordingly, the first element, the first component, the first region, the first wiring, the first layer, or the first section, which will be described below, may be referred to as the second element, the second component, or the second region within the spirit of the present invention. Of course, it may also be a second wiring, a second layer or a second section.

The spatially relative terms " below ", " beneath ", " lower ", " above ", " upper " It may be used to easily describe the correlation of a device or components with other devices or components. Spatially relative terms are to be understood as including terms in different directions of the device in use or operation in addition to the directions shown in the figures. For example, when flipping a device shown in the figure, a device described as "below" or "beneath" of another device may be placed "above" of another device. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in other directions, so that spatially relative terms can be interpreted according to orientation.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.

Unless otherwise defined, all terms used in the present specification (including technical and scientific terms) may be used in a sense that can be commonly understood by those skilled in the art. In addition, the terms defined in the commonly used dictionaries are not ideally or excessively interpreted unless they are specifically defined clearly.

Embodiments described herein will be described with reference to cross-sectional views, which are ideal schematic diagrams of the invention. Accordingly, the shape of the exemplary diagram may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include variations in forms generated by the manufacturing process. For example, the etched regions shown at right angles may be rounded or have a predetermined curvature. Accordingly, the regions illustrated in the figures have schematic attributes, and the shape of the regions illustrated in the figures is intended to illustrate a particular form of region of the device and not to limit the scope of the invention.

Hereinafter, an oxide thin film transistor substrate according to an exemplary embodiment will be described with reference to the accompanying drawings.

First, a structure of an oxide thin film transistor substrate according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1A to 1B. FIG. 1A is a layout diagram of an oxide thin film transistor substrate according to an exemplary embodiment, and FIG. 1B is a cross-sectional view taken along line B-B ′ of the oxide thin film transistor substrate of FIG. 1A.

The gate line 22 is formed on the substrate 10 in the horizontal direction, and the gate electrode 26 of the oxide thin film transistor formed in the form of a protrusion connected to the gate line 22 is formed. The gate line 22 and the gate electrode 26 are called gate wirings.

In addition, a storage electrode line 28 is formed on the substrate 10 and extends in the horizontal direction substantially parallel to the gate line 22 across the pixel area, and is connected to the storage electrode line 28 to have a wide width. The storage electrode 27 is formed. The storage electrode 27 overlaps the drain electrode extension 67 connected to the pixel electrode 82, which will be described later, to form a storage capacitor that improves charge preservation capability of the pixel. Such storage electrodes 27 and storage electrode lines 28 are called storage wirings.

The gate wirings 22 and 26 and the storage wirings 27 and 28 include aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper (Cu) and copper alloys, and the like. It may be made of a copper-based metal, molybdenum-based metals such as molybdenum (Mo) and molybdenum alloy, chromium (Cr), titanium (Ti), tantalum (Ta). However, the present invention is not limited thereto, and the gate wirings 22 and 26 and the storage wirings 27 and 28 may be made of various metals and conductors.

A gate insulating film 30 made of silicon nitride (SiNx) or the like is formed on the gate wirings 22 and 26 and the storage wirings 27 and 28. Oxide semiconductor patterns 42 and 44 made of an oxide including at least one material selected from O and Zn, In, Ga, or Sn are formed on the gate insulating layer 30. For example, mixed oxides such as InZnO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, GaInZnO, and the like may be used as the oxide semiconductor patterns 42 and 44. The oxide semiconductor patterns 42 and 44 have excellent semiconductor characteristics by having an effective mobility of about 2 to 100 times greater than the hydrogenated amorphous silicon and having an on / off current ratio of 10 ⁵ to 10 ⁸ . Have In the oxide semiconductors 42 and 44, since the band gap is about 3.0 to 3.5 eV, leakage photocurrent does not occur with respect to visible light. Therefore, the afterimage of the oxide thin film transistor can be prevented, and since the light blocking film is not required to be formed under the oxide thin film transistor, the aperture ratio of the liquid crystal display can be increased. In order to improve the characteristics of the oxide semiconductor, Group 3, Group 4, Group 5 or transition elements on the periodic table may be additionally included. In the case of the oxide thin film transistor, the pattern shape of the oxide semiconductor pattern and the data wiring is generally different from each other. However, when the four-mask process is applied, the oxide semiconductor patterns 42 and 44 may be patterned to have substantially the same shape as the data lines 62, 65, 66, and 67 to be described later except for the channel region of the oxide thin film transistor. Can be. This is because the oxide semiconductor patterns 42 and 44 and the data lines 62, 65, 66, and 67 are patterned by using an etching mask, which will be described in detail when the manufacturing method is described. In addition, although FIGS. 1A and 1B illustrate a structure manufactured by a four mask process, the main core content of the present invention is not limited thereto, and a process different from the four mask process, for example, a five mask process is used. It is obvious to those skilled in the art to apply the core idea of the present invention. Data wires 62, 65, 66, 67 are formed on the oxide semiconductor patterns 42, 44 and the gate insulating film 30. The data lines 62, 65, 66, and 67 are formed in the vertical direction and branched from the data line 62 and the data line 62 defining the pixel by crossing the gate line 22. A source electrode 65 extending to an upper portion of the oxide semiconductor pattern 44 and separated from the source electrode 65 so as to face the source electrode 65 with respect to the channel portion of the gate electrode 26 or the oxide thin film transistor. A drain electrode 66 formed on the oxide semiconductor pattern 44 and a drain electrode extension 67 having a large area extending from the drain electrode 66 and overlapping the storage electrode 27 are included.

The data lines 62, 65, 66, and 67 may be formed of a material that directly contacts the oxide semiconductor patterns 42 and 44 to form ohmic contact. When the data lines 62, 65, 66, and 67 are made of a material having a work function smaller than that of the materials constituting the oxide semiconductor patterns 42 and 44, ohmic contact may be formed between the two layers. Therefore, when the work function of the material constituting the oxide semiconductor patterns 42 and 44 is about 5 eV or more, for example, about 5.1 to 5.3 eV, the work function of the data wires 62, 65, 66, 67 is weak. It may be formed of a material of 5.3 eV or less. In addition, a small difference between the work functions of the data lines 62, 65, 66, and 67 and the oxide semiconductor patterns 42 and 44 may be about 1.5 eV or less, which may be more suitable for improving contact resistance characteristics. Accordingly, in order to form ohmic contact with the oxide semiconductor patterns 42 and 44, the data lines 62, 65, 66, and 67 may include Ni, Co, Ti, Ag, Cu, Mo, Al, Be, as shown in Table 1 below. Application of a single film or a multilayer film made of, Nb, Au, Fe, Se, or Ta is possible. In addition, an alloy containing at least one element selected from Ti, Zr, W, Ta, Nb, Pt, Hf, O, and N may be applied to the metal.

Table 1 below shows a work function of a metal material used as the data lines 62, 65, 66, and 67.

TABLE 1

metal Ni Co Ti Ag Cu Mo Work function (eV) 5.01 5.0 4.7 4.73 4.7 4.5 metal Al Be Nb Au Fe Se Work function (eV) 4.08 5.0 4.3 5.1 4.5 5.11

On the other hand, when the oxide semiconductor is in direct contact with metals such as Al, Cu, and Ag, characteristics and / or pixels of oxide thin film transistors employing these metals as data wirings 62, 65, 66, and 67 due to mutual reaction or diffusion. Ohmic contact properties with ITO or IZO, which are generally used as electrodes, may be deteriorated. Therefore, the data lines 62, 65, 66, 67 can be formed in a double film or triple film structure.

When applying an alloy containing Nd, Sc, C, Ni, B, Zr, Lu, Cu, Ag, etc. to Al or Al with the data lines 62, 65, 66, 67, the upper portion of the Al or Al alloy and And / or a multilayer film in which a hetero film is stacked below. For example, Mo (Mo alloy) / Al (Al alloy), Ti (Ti alloy) / Al (Al alloy), Ta (Ta alloy) / Al (Al alloy), Ni (Ni alloy) / Al (Al alloy ), Double layers such as Co (Co alloy) / Al (Al alloy), or Ti (Ti alloy) / Al (Al alloy) / Ti (Ti alloy), Ta (Ta alloy) / Al (Al alloy) / Ta ( Ta alloy), Ti (Ti alloy) / Al (Al alloy) / TiN, Ta (Ta alloy) / Al (Al alloy) / TaN, Ni (Ni alloy) / Al (Al alloy) / Ni (Ni alloy), Triple films such as Co (Co alloy) / Al (Al alloy) / Co (Co alloy), Mo (Mo alloy) / Al (Al alloy) / Mo (Mo alloy) may be applied. Materials marked with alloys may include Mo, W, Nb, Zr, V, O, N, and the like.

On the other hand, when Cu or a Cu alloy is applied to the data wirings 62, 65, 66, 67, the ohmic contact characteristic between the data wirings 62, 65, 66, 67 and the pixel electrode is not a big problem. A double film to which a film containing Mo, Ti, or Ta is applied between the Cu or Cu alloy film and the oxide semiconductor patterns 42 and 44 may be applied to (62, 65, 66, 67). For example, a double film such as Mo (Mo alloy) / Cu, Ti (Ti alloy) / Cu, TiN (TiN alloy) / Cu, Ta (Ta alloy) / Cu, TiOx / Cu, or the like may be applied.

The source electrode 65 overlaps at least a portion of the gate electrode 26, and the drain electrode 66 overlaps at least a portion of the gate electrode 26 so as to face the source electrode 65 around the channel portion of the oxide thin film transistor. do.

The drain electrode extension 67 is formed to overlap the storage electrode 27 to form a storage capacitor with the storage electrode 27 and the gate insulating layer 30 interposed therebetween. On the other hand, the storage capacitor may be formed using a counter electrode (not shown) and a storage electrode 27 which are connected to the drain electrode through the pixel electrode and formed by the same step as the drain electrode, and formed on the storage electrode 27. The storage capacitor may be formed by overlapping the pixel electrode and the storage electrode 27.

The oxide semiconductor patterns 42 and 44 have substantially the same shape as the data lines 62, 65, 66, and 67 except for the channel portion of the oxide thin film transistor. That is, the source electrode 65 and the drain electrode 66 are separated from the channel portion of the oxide thin film transistor, and the oxide semiconductor pattern 44 for the oxide thin film transistor is connected without disconnection to form a channel of the oxide thin film transistor. .

The passivation layer 70 is formed on the data lines 62, 65, 66, 67, and the oxide semiconductor pattern 44 exposed thereby. In addition, the passivation layer 70 may be formed of an inorganic layer or an organic layer, and may have a double layer structure of a lower inorganic layer and an upper organic layer to protect the oxide semiconductor pattern 44.

In the passivation layer 70, a contact hole 77 exposing the drain electrode extension 67 is formed.

The pixel electrode 82 is formed on the passivation layer 70 along the shape of the pixel. The pixel electrode 82 is electrically connected to the drain electrode extension 67 through the contact hole 77. The pixel electrode 82 may be made of a transparent conductor such as ITO or IZO or a reflective conductor such as aluminum.

Factors affecting the electrical characteristics of the oxide thin film transistor will be described with reference to FIGS. 2A through 2C.

FIG. 2A is an enlarged view of region A of FIG. 1B and shows the thickness of the first region A (hereinafter referred to as 'a') and the thickness of the second region B (hereinafter referred to as 'b'). In the oxide thin film transistor, an appropriate thickness of the first region A and the second region B is required.

FIG. 2B shows the electrical characteristics of the oxide thin film transistor under each condition while fixing 'b' to 700 mV and changing only 'a'. According to FIG. 2B, when the thickness of the channel layer becomes less than about 160 μs while the 'a' gradually decreases, the IV characteristics of the oxide thin film transistor become worse due to uniformity, surface effect, etc., and thus cannot be used as a driving device of a display device. .

FIG. 2C shows the electrical characteristics of the oxide thin film transistor under each condition while fixing 'a' and changing only 'b'. In FIG. 2C, a first group g1 is a case where b is 1600 μs to 1700 μs, a second group g2 is a case where b is 1400 μs to 1500 μm and a third group g3 is a case where b is 1300 μs to 1400 μs, The fourth group g4 is the case where b is 1100 μs to 1200 μs, the fifth group g5 is the case where b is 1000 μs to 1100 μs and the sixth group g1 is the case where b is 900 μs to 1000 μs and the seventh group g7 ) Is the case where b is 800 mW to 900 mW. As can be seen in FIG. 2C, when the value of b increases, the threshold voltage value of the oxide thin film transistor gradually becomes negative. Therefore, in order to obtain a value of more than a threshold voltage of -20V required for driving the display element, b must have a value of 1300 kV or less.

2B and 2C, when b is larger than a, the minimum value of a is 160 ms and the maximum value of b is 1300 ms, a may be about 160 ms or more and less than about 1300 ms. Thus, b may also be greater than about 160 ms and up to about 1300 ms. This result of the oxide thin film transistor is believed to be due to the physical properties of the oxide layer. Therefore, according to the oxide thin film transistor substrate according to the embodiment of the present invention, the ratio of b / a may be less than 1 and at least 0.123. In this case, the leakage current of the oxide thin film transistor may be reduced. In addition, the current value at turn-on of the oxide thin film transistor increases, and the oxide thin film transistor may have an appropriate threshold voltage.

Hereinafter, various embodiments of a method of manufacturing an oxide thin film transistor having such an appropriate b / a ratio will be described with reference to FIGS. 3 to 8. 3 to 8 are process cross-sectional views sequentially illustrating a method of manufacturing the oxide thin film transistor substrate illustrated in FIG. 1B.

First, as shown in FIG. 3, a multilayer metal film (not shown) for gate wiring is stacked on the insulating substrate 10, and then patterned to form the gate line 22, the gate electrode 26, and the storage electrode 27. To form. At this time, the storage electrode 27 may not be formed depending on the driving method. The gate line 22, the gate electrode 26, and the storage electrode 27 may have a double layer structure in which a lower layer of aluminum or an aluminum alloy and an upper layer of molybdenum or molybdenum alloy are stacked. Subsequently, as shown in FIG. 3, the gate insulating film 30 is disposed on the substrate 10, the gate wirings 22 and 26, and the storage wirings 27 and 28, for example, by plasma enhanced CVD. , PECVD) or reactive sputtering.

The oxide semiconductor film 40 and the data wiring conductive film 60 are deposited on the gate insulating film 30 using, for example, radio frequency (RF) sputtering or direct current (DC) sputtering. In this case, when the oxide thin film transistor is manufactured using a four-sheet mask process, the oxide semiconductor film 40 and the data wiring conductive film 60 can be continuously deposited. It is possible to maintain the vacuum breaking state between the conductive film 60 deposition steps. As such, the oxide semiconductor film 40 and the data wiring conductive film 60 are continuously deposited in one vacuum chamber without breaking the vacuum, thereby preventing the oxide semiconductor film 40 from being affected by oxygen in the air and deteriorating characteristics. Therefore, the characteristics of the oxide thin film transistor can be further improved.

Next, a photosensitive film is coated on the conductive film 60 for data wiring. After irradiating light to the photoresist film through a mask, the photoresist pattern 114 is formed. The photosensitive film pattern 114 may include an exposed region C exposing the data wiring conductive film 60, and a first thickness region A and a second thickness region B overlapping the data wiring conductive film 60. do. The first thickness region A is positioned between the channel portion of the oxide thin film transistor, that is, between the source electrode 65 of FIG. 1B and the drain electrode 66 of FIG. 1B. The second thickness area B is located at both sides of the first thickness area A. FIG. The first thickness area A is thinner than the second thickness area B. FIG. In this case, the ratio of the thickness of the first thickness region A to the thickness of the second thickness region B may vary depending on the process conditions in the etching process described later.

As such, there may be various methods of varying the thickness of the photoresist film according to the position, and a mask using a slit, a grid pattern, or a semitransparent film may be mainly used to control the amount of light transmission. In addition, by using a photosensitive film made of a reflowable material, the photomask is exposed with a conventional mask that is divided into a part that can completely transmit light and a part that can't completely transmit light, and then developed and reflowed so that the photoresist film does not remain. This thin thickness first thickness region A may be formed by allowing a portion of the photosensitive film to flow down.

Referring to FIG. 4, the data wiring conductive film 60 and the oxide semiconductor film 40 are etched using the photosensitive film pattern 114 as an etching mask. As a result of etching, the conductive film patterns 62 and 64 and the oxide semiconductor film patterns 42 and 43 under the first and second thickness regions A and B remain, and the conductive portions for the data wiring of the exposed region C remain. Both the film 60 and the oxide semiconductor film 40 are removed to expose the lower gate insulating film 30. At this time, except that the source electrodes (65 in FIG. 1B) and the drain electrodes (66 in FIG. 1B) of the remaining conductive film patterns 62 and 64 are connected without being separated, the data wirings (62, 65, 66, 67).

In the method of etching the conductive film 60 and the oxide semiconductor film 40 for the data wiring using the photoresist pattern 114 as an etching mask, a wide variety of etching methods may be applied according to the types of materials constituting them and the limiting variables of the etching process. Can be.

The data wiring conductive film 60 is formed of a double film or a triple film including a Mo or Mo alloy film and an Al or Al alloy film, and the oxide semiconductor film 40 is formed of at least one element and O from Ga, In, or Zn. When formed of an oxide semiconductor film containing a variety of etching methods can be used as follows.

According to one method, the data wiring conductive film 60 and the oxide semiconductor film 40 may be continuously wet-etched in a batch using the mixed etchant under the conditions in Table 2 below. By sequentially etching the data wiring conductive film 60 and the oxide semiconductor film 40, the manufacturing process of the oxide thin film transistor can be simplified.

According to another method, the data wiring conductive film 60 may be wet etched, and the oxide semiconductor film 40 may be dry etched. In the dry etching of the oxide semiconductor film 40, an etching gas in which Ar or He is mixed may be used as the fluorine-based etching gas. CHF ₃ , CF _4, etc. may be used as the fluorine-based etching gas. In addition, the dry etching of the oxide semiconductor film 40 may be performed using a gas containing C, H, O, or the like.

According to another method, the data wiring conductive film 60 may be dry etched using a fluorine-based etching gas, a chlorine-based etching gas, or a mixture thereof, and the oxide semiconductor film 40 may be wet-etched. Dry etching of the data wiring conductive layer 60 may enable finer patterning due to the characteristics of the anisotropic etching. Examples of the fluorine-based etching gas include SF ₆ , CF ₄ , XeF ₂ , BrF ₂ , and ClF ₂ , and examples of the chlorine-based etching gas include Cl ₂ , BCl ₃ , and HCl. For example, the Mo film may use a mixed gas of Cl2 and O2, and the Al film may perform dry etching using a SF6 and Cl2 mixed gas. The wet etching of the oxide semiconductor film 40 may be performed using an etching solution obtained by mixing deionized water with hydrofluoric acid, sulfuric acid, hydrochloric acid, and a combination thereof, or a mixed etching solution under the condition 1 in Table 2 below.

According to another method, both the data wiring conductive film 60 and the oxide semiconductor film 40 can be dry etched.

Among the above methods, the method in which the data wiring conductive film 60 and the oxide semiconductor film 40 are continuously etched under the same etching conditions is effective in terms of simplifying the manufacturing process. In addition, the etching of the data wiring conductive layer 60 may be performed by wet etching so that the oxide semiconductor film 40 may not be damaged by dry etching.

TABLE 2

division One 3 2 Etching method Wet etching Wet etching Dry etching Furtherance Phosphoric Acid (60 ~ 80wt%) Nitric Acid (3 ~ 15wt%) Acetic Acid (3 ~ 20wt%) Pure Water (0 ~ 10wt%) Other Additives Ethylene Glycol (0.1 ~ 30wt%) HNO3 (0.1 ~ 20wt%) H2SO4 (0.01 ~ 5wt%) Pure Water (Remaining) Other additives. O2, Cl2 (O2 / Cl2 = 0.1 ~ 10 (sccm / sccm) Etch rate for data wiring conductive film (Mo, Al, Cu, Ti, Ta) 60 ~ 150Å / sec 0.5 ~ 2Å / sec 900 ~ 5400 Å / min Oxide Semiconductor Film (Ga, In, Zn, Sn, O) Etch Rate 10 ~ 30 Å / sec 10 ~ 30 Å / sec 30 ~ 300 Å / sec Etch selectivity of conductive film for data wiring to oxide semiconductor film 2: 1-15: 1 0.017: 1 to 0.2: 1 3: 1 to 18: 1

The data wiring conductive film 60 is formed to include a film made of Mo, Ti, Ta or their respective alloy films and a film made of Cu or Cu alloy films, and the oxide semiconductor film 40 is formed of Ga, In, or Zn. When formed of an oxide semiconductor film containing at least one element and O, various etching methods may be used as follows.

According to one method, the conductive wiring 60 and the oxide semiconductor film 40 for the data wiring are mixed with H ₂ O ₂ , HF (1-2%) and additives, phosphoric acid, nitric acid (1-5 wt%), acetic acid, Batch wet etching may be performed continuously using a mixed etchant of sulfuric acid and an additive, or a mixed etchant under the condition 1 in Table 2. By sequentially etching the data wiring conductive film 60 and the oxide semiconductor film 40, the manufacturing process of the oxide thin film transistor can be simplified. This method can be applied more effectively in the case of the data wiring conductive film 60 composed of a double film of Mo (Mo alloy) / Cu (Cu alloy).

According to another method, the data wiring conductive film 60 may be wet etched, and the oxide semiconductor film 40 may be dry etched.

According to another method, when the data wiring conductive film 60 is made of a double film of Ti (Ti alloy) / Cu (Cu alloy) or a double film of Ta (Ta alloy) / Cu (Cu alloy), Cu (Cu Alloy) film may be wet etched using an etchant that does not contain H ₂ O ₂ , and dry etching of the lower Ti (Ti alloy) film or Ta (Ta alloy) film may be advantageous in terms of process stability. Dry etching of the Ti (Ti alloy) film or the Ta (Ta alloy) film may be performed using Cl ₂ , O ₂ , SF ₆ as the main etching gas. In this case, the lower oxide semiconductor film 40 may be used by either a dry or wet etching method.

Subsequently, referring to FIG. 5, the photoresist pattern 114 ′ which exposes the conductive layer pattern 64 on the channel part is etched back to remove the first thickness region A of the photoresist pattern 114. Form. The photoresist residue remaining on the exposed surface of the conductive layer pattern 64 may be removed by an ashing process.

Next, as shown in FIG. 6, the conductive film pattern 64 exposed by the etch back removing step is removed by wet etching, dry etching, or mixed wet and dry etching. At this time, the wet etching selectivity of the conductive film pattern 64 with respect to the oxide semiconductor film 40 is appropriately 2: 1 to 15: 1, and the dry etching selectivity is appropriately at least 3: 1 or more. Do.

Wet etching may be performed using a mixed etchant in Table 1 above. Wet etching may also be performed using an etchant in which deionized water is mixed with hydrofluoric acid, sulfuric acid, hydrochloric acid and combinations thereof. Dry etching may be performed using a mixed etching gas under the two conditions of Table 2, or may be performed using the aforementioned various dry etching methods. When the conductive film pattern 64 is formed of a double film of Ti (Ti alloy) / Cu (Cu alloy) or a double film of Ta (Ta alloy) / Cu (Cu alloy), the wet-dry method described above is performed. You may.

When the conductive film pattern 64 is etched, a part of the oxide semiconductor film pattern 44 in the channel portion is etched according to the selectivity during etching, so that the b / a ratio has a value of less than one. In this way, the data wirings 62, 65, 66, and 67 are completed while the source electrode 65 and the drain electrode 66 are separated.

Subsequently, as illustrated in FIG. 7, the photoresist pattern 114 ′ is removed to complete the data lines 62, 65, 66, and 67.

Subsequently, as shown in FIG. 8, the passivation layer 70 is formed on the resultant, and the passivation layer 70 is etched to form the contact hole 77 exposing the drain electrode extension 67. In this case, when the passivation layer 70 is a photosensitive material, the contact hole 77 pattern is formed by using a photolithography method, and when the passivation layer 70 is not a photosensitive material, the contact hole 77 pattern is formed through an additional photomask process. .

Finally, as illustrated in FIG. 1B, a transparent or reflective conductor such as ITO, IZO, or the like is deposited and photo-etched to form the pixel electrode 82 connected to the drain electrode extension 67.

3 to 8 illustrate a method of using a four-sheet mask process, but an oxide thin film transistor according to example embodiments may be manufactured by applying a five-mask process.

In the case of applying the five-sheet mask process, only the oxide semiconductor film 40 is deposited first, and then etched by the oxide semiconductor film pattern 43. Etching may be etched using the etchant of 1 or 2 conditions of Table 2.

The conductive film 60 for data wiring is formed on the entire surface of the substrate on which the oxide semiconductor film pattern 43 is formed, and the conductive film pattern 64 is formed by etching it. Thereafter, the conductive layer pattern 64 of the channel portion is removed by wet etching, dry etching, or a mixed etching method of wet and dry. In this case, the wet etching selectivity of the conductive film pattern 64 with respect to the oxide semiconductor film pattern 43 may be 2: 1 to 15: 1, and the dry etching selectivity may be at least 3: 1 or more. proper.

A portion of the oxide semiconductor film pattern 44 in the channel portion is etched according to the selectivity at the time of etching, so that the b / a ratio has a value of less than one. In this way, the data wirings 62, 65, 66, and 67 are completed while the source electrode 65 and the drain electrode 66 are separated.

Since the process is substantially the same as the four-sheet mask process, a detailed description thereof will be omitted.

The method for manufacturing an oxide thin film transistor substrate according to the present invention is, in addition to the above embodiments, a color filter on array (COA) structure for forming a color filter on the oxide thin film transistor array or an AOC for forming a color filter before forming the oxide thin film transistor array. (Array on Color filter) can be easily applied to the structure.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments but may be manufactured in various forms, and having ordinary skill in the art to which the present invention pertains. It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

1A is a layout view of an oxide thin film transistor substrate according to an exemplary embodiment.

FIG. 1B is a cross-sectional view of the oxide thin film transistor substrate of FIG. 1A taken along line BB ′.

FIG. 2A is an enlarged view of region A of FIG. 1B.

2B is an electrical characteristic diagram of an oxide thin film transistor according to an exemplary embodiment of the present invention.

2C is yet another electrical characteristic diagram of the oxide thin film transistor according to the exemplary embodiment of the present invention.

3 to 8 are process cross-sectional views sequentially illustrating a method of manufacturing the oxide thin film transistor substrate illustrated in FIG. 1B.

<Description of the symbols for the main parts of the drawings>

10: substrate 22: gate wiring

26: gate electrode 27: storage electrode

28: storage electrode line 30: gate insulating film

40: oxide semiconductor film 42, 44: oxide semiconductor film pattern

60: conductive film for data wiring 62: data line

64: conductive film pattern 65: source electrode

66: drain electrode 67: drain electrode extension

70: shield 77: contact hole

82: pixel electrode 114: photosensitive film pattern

Claims (19)

Forming a gate wiring on an insulating substrate, A stacked structure of an oxide semiconductor layer pattern and a data line is formed on the gate line, wherein the oxide semiconductor layer pattern is divided into a first region and a second region, and the thickness of the first region is thinner than the thickness of the second region. And the data line is formed on the second region. According to claim 1, The thickness ratio of the said 1st area | region and the thickness of said 2nd area | region is 0.123 or more and less than 1 The manufacturing method of the oxide thin film transistor substrate. The method of claim 2, A method of manufacturing an oxide thin film transistor substrate having a thickness of the first region of 160 kPa or more and less than 1300 kPa. The method of claim 3 Forming a laminated structure of the oxide semiconductor film pattern and data wiring, Forming an oxide semiconductor film and a conductive film for data wiring on the gate wiring; Forming an etch mask pattern having a first thickness region corresponding to the first region, a second thickness region corresponding to the second region and thicker than the first thickness region, and an exposure region exposing the conductive layer for data wiring; Etching the data wiring conductive film and the oxide semiconductor film exposed by the exposed region of the etch mask pattern, Removing the first thickness area of the etching mask pattern, And etching the conductive film for data wiring exposed by the removal. The method of claim 4, wherein Forming the oxide semiconductor film and the conductive film for data wiring is a method of manufacturing an oxide thin film transistor substrate that is deposited continuously by sputtering in one vacuum chamber. The method of claim 5, The data wiring conductive film includes at least one element of Al, Cu, Ti, Ta, and Mo, And the oxide semiconductor film comprises at least one element of Ga, In, Zn and Sn and O. The method of claim 6, And etching the data wiring conductive film and the oxide semiconductor film exposed by the exposed region of the etch mask pattern are continuously etched under the same etching conditions. The method of claim 7, wherein And etching the data wiring conductive layer by wet etching. The method of manufacturing an oxide thin film transistor substrate according to claim 8, wherein the conductive film for data wiring is a multilayer film of a film containing Mo and a film containing Al, or a multilayer film of a film containing Mo and a film containing Cu. The method of claim 6, The data wiring conductive film is formed of a lower film including Ti or Ta and an upper film containing Cu, Etching the conductive film for data wiring includes etching the upper layer by wet etching and etching the lower layer by dry etching. The method of claim 2, Forming a laminated structure of the oxide semiconductor pattern and data wiring, Forming an oxide semiconductor film pattern on the gate wiring, A conductive film for data wiring is formed on the oxide semiconductor film pattern, The data wiring conductive film is etched to form a conductive film pattern, And removing the conductive film pattern on the first region. The method of claim 2, The work function of the data wiring is about 5.3 eV or less. The method of claim 2, The band gap of the oxide semiconductor film pattern is a method of manufacturing an oxide thin film transistor substrate of 3.2 ~ 3.4 eV. The method of claim 13, The difference between the work function value of the data line and the oxide semiconductor film pattern is about 1.5 eV or less. According to claim 1, The data wiring is Mo (Mo alloy) / Al (Al alloy), Ti (Ti alloy) / Al (Al alloy), Ta (Ta alloy) / Al (Al alloy), Ni (Ni alloy) / Al (Al alloy) ), Co (Co alloy) / Al (Al alloy), Mo (Mo alloy) / Cu, Ti (Ti alloy) / Cu, TiN (TiN alloy) / Cu, Ta (Ta alloy) / Cu, and TiOx / Cu Any one of the double layer or Ti (Ti alloy) / Al (Al alloy) / Ti (Ti alloy), Ta (Ta alloy) / Al (Al alloy) / Ta (Ta alloy), Ti (Ti alloy) / Al (Al alloy) / TiN, Ta (Ta alloy) / Al (Al alloy) / TaN, Ni (Ni alloy) / Al (Al alloy) / Ni (Ni alloy), Co (Co alloy) / Al (Al alloy) A method of manufacturing an oxide thin film transistor substrate comprising a triple film of any one of / Co (Co alloy) and Mo (Mo alloy) / Al (Al alloy) / Mo (Mo alloy). A gate wiring formed on the insulating substrate; An oxide semiconductor pattern formed on the gate wiring, the oxide semiconductor pattern being divided into a first region and a second region, the thickness of the first region being thinner than the thickness of the second region; And An oxide thin film transistor substrate comprising a data line formed on the second region. The method of claim 16, And a thickness ratio of the first region to the second region is greater than or equal to 0.123 and less than one. The method of claim 17, An oxide thin film transistor substrate, wherein the first region has a thickness of 160 kPa or more and less than 1300 kPa. The method of claim 17, wherein the data line comprises at least one element of Al, Cu, Ti, Ta and Mo, The oxide semiconductor pattern is an oxide thin film transistor substrate comprising at least one element and O of Ga, In, Zn and Sn.

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