KR20080036679A - Method for forming nonvolatile memory device - Google Patents

Abstract

In a method of forming a nonvolatile memory device including a gate having excellent step coverage, a device isolation pattern recessed from a substrate surface is formed to define an active region. A tunnel insulating film, a charge trap film, and a blocking dielectric film are sequentially stacked on the device isolation pattern and the substrate. A tungsten nitride film is formed on the blocking dielectric film, and a tungsten film is formed on the tungsten nitride film by using a pulsed nucleation layer (PNL) deposition process. Thus, by forming the tungsten film in the pulsed nuclear layer deposition process, it is possible to form a gate having excellent step coverage and low resistance.

Description

Method of forming a non-volatile memory device

1 is a SEM photograph illustrating a conventional floating trap type nonvolatile memory device.

2 to 8 are schematic cross-sectional views illustrating a method of forming a nonvolatile memory device according to an embodiment of the present invention.

FIG. 9 is a SEM photograph of a memory cell of the nonvolatile memory device shown in FIG. 8.

10 is a table showing resistance of a gate electrode according to a method of forming a tungsten nitride film and a tungsten film.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 102 pad oxide film

104: mask film pattern 106: pad oxide film pattern

108: trench 110: preliminary device separator pattern

112: device isolation layer pattern 114: opening

116 Tunnel oxide film 118 Charge trap film

120: blocking dielectric film 122: tungsten nitride film

124: tungsten film

The present invention relates to a method of forming a nonvolatile memory device. More specifically, the present invention relates to a method of forming a nonvolatile memory device including a charge trap film.

In general, a nonvolatile memory device may be a floating gate type nonvolatile memory device or a floating trap type nonvolatile memory device according to a unit cell structure. Can be divided.

The floating gate type nonvolatile memory device includes a tunnel insulating film, a floating gate, a dielectric film, and a control gate formed on a semiconductor substrate as a unit cell. In addition, programming or erasing may be performed by storing charges in the form of free carriers or extracting stored charges in the floating gate. In particular, in the floating gate type nonvolatile memory device, when a defect occurs in the tunnel insulating film interposed between the floating gate and the semiconductor substrate, all of the charge stored in the floating gate may be lost, thereby making the tunnel insulating film relatively thick. Should be formed. However, when the tunnel insulating film is formed somewhat thick, a high operating voltage is required, resulting in a complicated structure of the peripheral circuit. Therefore, there is a limit to high integration of the floating gate type nonvolatile memory device.

Meanwhile, the floating trap type nonvolatile memory device includes a tunnel insulating film of silicon oxide, a charge trap film of silicon nitride, a blocking dielectric film of silicon oxide, and a gate electrode of a conductive material formed on a semiconductor substrate as a unit cell. The floating trap type nonvolatile memory device stores an electron (e) in a trap formed on the charge trap layer interposed between the gate electrode and the semiconductor substrate to perform programming, and a trap formed on the charge trap layer. Holes (h) can be stored at the site to perform erasure. In particular, since the electrons or holes are stored at the trap site of the charge trap film, the tunnel insulating film can be formed relatively thin. As described above, when the tunnel insulating film is formed to be somewhat thin, the drive can be performed even at a low operating voltage, thereby simplifying the structure of the peripheral circuit. Therefore, the floating trap type nonvolatile memory device can easily implement high integration.

In recent years, as the degree of integration of semiconductor devices increases, the device isolation pattern of the floating trap type nonvolatile memory device has a lower structure than the active region.

A tunnel insulating film, a charge trap film, a blocking dielectric film, and a barrier film are sequentially stacked on the recessed device isolation pattern according to the profile of the device isolation pattern. Next, a metal nitride film and a metal film are formed on the barrier film.

However, conventionally, by depositing the metal nitride film and the metal film by a physical vapor deposition process, the thickness of the metal film formed in the recess and the metal film formed on the upper surface of the device isolation pattern is formed differently.

1 is a SEM photograph illustrating a conventional floating trap type nonvolatile memory device.

Referring to FIG. 1, the metal film formed inside the recess has a thickness of 12.10 nm (B) or 15.13 nm (C), while the metal film formed on the top surface of the device isolation pattern has a thickness of about 35.98 nm (A).

That is, when the metal film is deposited on the metal nitride film by a physical vapor deposition process, the step coverage of the metal film is very low as shown.

As described above, when the thickness difference of the metal film is large for each part, the resistance is different for each part. Therefore, the reliability of the nonvolatile memory device using the metal film as the floating gate is very low.

Therefore, in order to improve the step coverage, a metal film may be deposited on the metal nitride film by a chemical vapor deposition method. However, due to the characteristics of the chemical vapor deposition process, only the pure metal film is not formed inside the metal film formed by the chemical vapor deposition process, and a large amount of contaminants may be added. For this reason, the metal film formed by the chemical vapor deposition process has a much higher resistance than the metal film formed by the physical vapor deposition process. Thus, when the metal film formed by the chemical vapor deposition process is used as a gate, there is a problem that the resistance of the gate is high.

An object of the present invention for solving the above problems is to provide a method of forming a nonvolatile memory device having a low resistance and a good step coverage gate.

According to an aspect of the present invention for achieving the above object, in the method of forming a nonvolatile memory device, an active isolation pattern is defined by forming a recessed device isolation pattern from the surface of the substrate. A tunnel insulating layer, a charge trap layer, and a blocking dielectric layer are sequentially formed on the device isolation pattern and the active region. A tungsten nitride film WN is formed on the blocking dielectric film. The tungsten film W is formed on the tungsten nitride film by using a pulsed nucleation layer (PNL) deposition process.

According to an embodiment of the present invention, the tungsten nitride film may be formed by a physical vapor deposition process. The pulsed nuclear layer deposition process may be performed at a temperature of 200 to 400 ℃ under 100 to 400 Torr pressure. The tunnel insulating film is silicon oxide (SixOy), the charge trap film is silicon nitride (SixNy), the blocking dielectric film is aluminum oxide (AlxOy), the barrier film is titanium nitride (TiN), tantalum carbide nitride (TaCN) or tantalum nitride (TaN) may be included. The tungsten film may be formed by performing a pulsed nuclear layer deposition process using SiH ₄ or B ₂ H ₆ as a nucleator source and using WF ₆ as a reactor source. After forming the barrier layer, a polysilicon layer doped with impurities may be formed on the barrier layer, and an ohmic layer may be further formed on the polysilicon layer. The ohmic layer may include tungsten silicide (WxSiy). The device isolation pattern may sequentially form a pad oxide film and a mask on the substrate, etch the pad oxide film and the substrate by using the mask to form a pad oxide pattern and a trench, and fill the trench on the mask. The device isolation layer may be formed, and the upper portion of the device isolation layer may be removed to expose the upper side surface of the active region.

According to the present invention as described above, by forming the metal nitride film by the pulsed nuclear layer deposition process, and the metal film by the physical vapor deposition process, it is possible to form a gate having excellent step coverage and low resistance.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and those skilled in the art will appreciate the technical spirit of the present invention. The present invention may be embodied in various other forms without departing from the scope of the present invention. In the accompanying drawings, the dimensions of the substrate, film, region, pad or patterns are shown to be larger than the actual for clarity of the invention. In the present invention, when each film, region, pad or pattern is referred to as being formed "on", "upper" or "top surface" of a substrate, each film, region or pad, each film, region, Meaning that the pad or patterns are formed directly on the substrate, each film, region, pad or patterns, or another film, another region, another pad or other patterns may be additionally formed on the substrate.

Hereinafter, a method of forming a nonvolatile memory device according to an embodiment of the present invention will be described in detail.

2 to 8 are schematic cross-sectional views illustrating a method of forming a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 2, a pad oxide film 102 and a mask film (not shown) are formed on the semiconductor substrate 100.

The pad oxide layer 102 may include silicon oxide and may be thinly formed on the semiconductor substrate 100 by thermal oxidation or chemical vapor deposition. The mask layer includes silicon nitride and may be formed by a chemical vapor deposition process.

A photoresist pattern (not shown) is formed on the mask film to partially expose the mask film. The portion exposed by the photoresist pattern is a portion where the device isolation pattern is to be formed, and the masked portion is an active region.

Although not shown, before forming the photoresist pattern, an amorphous carbon layer (ACL) and an anti-reflection layer (ARL) may be sequentially formed on the nitride layer. . The amorphous carbon film and the organic antireflective film are provided to prevent the photoresist pattern sidewall profile from being poor due to diffuse reflection in a subsequent photographic process. In particular, the organic anti-reflection film may be a silicon oxynitride layer (SiON), and may be removed while the photoresist pattern is removed.

Subsequently, the mask layer is etched using the photoresist pattern as an etching mask to form a mask layer pattern 104 on the pad oxide layer 102. After the mask layer pattern 104 is formed, the photoresist pattern is removed by an ashing or strip process.

Referring to FIG. 3, the pad oxide layer 102 and the semiconductor substrate 100 are etched using the mask layer pattern 104 as an etch mask to form the pad oxide layer pattern 106 and the trench 108.

Meanwhile, after the trench 108 is formed, a thermal oxide film (not shown) and an insulating film liner (not shown) are optionally formed inside the trench 108.

In more detail, first, the thermal oxide layer thermally oxidizes the surface of the trench 108 to heal the damage of the trench 108 surface that occurred during the previous dry etching process. Is formed.

Subsequently, an insulating film liner is formed to a thickness of several hundred micrometers on the inner surface and the bottom surface of the trench 108 where the thermal oxide film is formed and the surface of the mask film pattern 104. The insulating film liner is formed to reduce stress in the silicon oxide film for device isolation embedded in the trench 108 by a subsequent process and to prevent impurity ions from penetrating into the field region. The insulating film liner should be formed of a material having a high etching selectivity with respect to a silicon oxide film, which will be described later, under specific etching conditions. For example, the insulating film liner may be formed of silicon nitride (SiN).

Referring to FIG. 4, an isolation layer (not shown) is formed on the mask layer pattern 104 to fill the trench 108. The device isolation layer may include an oxide having an excellent gap filling property, and examples of the oxide may include an undoped silicate glass (USG), an O ₃ -TEOS USG (O ₃ -Tetra Ethyl Ortho Silicate Undoped Silicate Glass), or a high density plasma (High Density). Plasma: HDP) oxide film, etc. are mentioned. The device isolation layer may be formed by a chemical vapor deposition method or the like.

Subsequently, the device isolation layer is polished by an etch back or chemical mechanical polishing (CMP) method to form a preliminary device isolation layer pattern 110 in the trench 108.

Referring to FIG. 5, an upper portion of the preliminary device isolation layer pattern 110 is removed to form a device isolation layer pattern 112 recessed from a surface of the semiconductor substrate 100. An opening 114 is formed on the device isolation layer pattern 112 by the removal process, and an active pattern is defined by the device isolation layer pattern 112.

The active pattern is formed higher than the device isolation layer pattern to have a fin shape. In this case, a portion of the upper sidewall of the active pattern is exposed by the opening 114.

Subsequently, although not shown in detail, the mask film pattern 104 and the pad oxide film pattern 106 are removed.

Referring to FIG. 6, a tunnel insulating layer 116 is formed along the profile of the device isolation layer pattern 112 and the active pattern. In this case, the tunnel insulating layer 116 may include silicon oxide, may be formed by a thermal oxidation or chemical vapor deposition process, and is formed very thin so as not to fill the opening 114.

The charge trap layer 118 is formed on the tunnel insulating layer 116. The charge trap layer 118 may include silicon nitride and serve as a trap site for electrons or holes. In this case, the charge trap layer 118 is formed along the profile of the tunnel insulating layer 116 so as not to fill the opening.

A blocking dielectric layer 120 is formed on the charge trap layer 118. The blocking dielectric layer 120 includes aluminum oxide and is formed along the profile of the charge trap layer 118 so as not to fill the opening 114.

Referring to FIG. 7, a barrier layer 122 is formed on the blocking dielectric layer 120.

In this embodiment, since the metal film is used as the gate of the nonvolatile memory device, the barrier film 122 is formed to prevent the metal in the metal film from being diffused by subsequent heat treatment.

The barrier layer 122 includes tungsten nitride (WN) titanium nitride (TiN), tantalum carbide nitride (TaCN), or tantalum nitride (TaN), and the profile of the blocking dielectric layer 120 is disposed so as not to fill the opening 114. Form along.

In this embodiment, a tungsten nitride film is formed of the barrier film 122. The tungsten nitride film is formed to a thin thickness of about 45 to 55 kPa by a physical vapor deposition process.

The physical vapor deposition process may be performed using sputtering. In more detail, the sputtering process plasma sputters a tungsten target so that tungsten atoms are separated from the tungsten target. In this case, by injecting a nitrogen source gas onto the semiconductor substrate 100 on which the blocking dielectric layer 120 is formed, the sputtering tungsten atom and the nitrogen atom combine to form a tungsten nitride layer WN 122 on the blocking dielectric layer 120. Can be.

Although not illustrated in detail, a polysilicon layer doped with impurities may be formed on the barrier layer 122, and a tungsten silicide layer may be formed on the polysilicon layer. In this case, the doped polysilicon layer may function as a gate electrode. However, since the resistance of the polysilicon film doped with the impurity is greater than that of the metal film, a metal film such as tungsten may be further formed on the polysilicon film doped with the impurity. On the other hand, the tungsten silicide film then functions as an ohmic layer with the tungsten film.

The impurity doped polysilicon film may be formed by injecting an impurity gas while the polysilicon film is formed by a chemical vapor deposition process. The heat treatment may be performed to form a tungsten silicide layer or may be formed by a chemical vapor deposition process.

 Referring to FIG. 8, a metal film 124 is formed on the barrier film 122.

In this embodiment, a tungsten film is used as the metal film 124, and the tungsten film 124 is formed to a thickness of about 300 μs through a pulsed nucleation layer deposition process.

In this case, the tungsten film 124 may be formed by a chemical vapor deposition process or an atomic layer deposition process, but the tungsten film formed by the pulsed nuclear layer deposition process has the lowest resistance. Therefore, in this embodiment, the tungsten film is formed by a pulsed nuclear layer deposition process.

The pulsed nuclear layer deposition process injects a nuclear source (nucleator source) for forming a nuclear layer, and then a reactor source for forming the tungsten film. The tungsten film may be formed on the tungsten nitride film by implanting the nuclear source and the reaction source in a pulsed manner. Here, the thickness of the tungsten film is adjustable by the number of pulses of nuclear source injection and source injection.

In addition, SiH ₄ or B ₂ H ₆ is used as the nuclear source and WF ₆ is used as the reaction source. In addition, the pulsed nuclear layer deposition process is carried out at 200 to 400 ℃ under about 100 to 500 Torr.

By forming the tungsten film 124 in the pulsed nuclear layer deposition process as described above, the tungsten film 124 having excellent step coverage and low resistance can be formed on the tungsten nitride film 122.

Although not shown, the tungsten film 124, the tungsten nitride film 122, the blocking dielectric film 120, the charge trap film 118, and the tunnel insulating film 116 are patterned to form a memory cell of a nonvolatile memory device. .

Hereinafter, the characteristics of the nonvolatile memory device illustrated in FIGS. 2 to 8 will be described.

FIG. 9 is a SEM photograph of a memory cell of the nonvolatile memory device shown in FIG. 8.

Referring to FIG. 9, it can be seen that the step coverage of the tungsten film formed on the tungsten nitride film is very excellent.

In particular, as compared with FIG. 1, the tungsten film of FIG. 1 is formed by a physical vapor deposition process, and its thickness is very uneven. More specifically, when looking at the thickness of the tungsten film formed in the opening, the tungsten film formed on the sidewall of the opening is 12.10 nm, and the tungsten film formed on the bottom is 15.13 nm. On the other hand, the tungsten film formed on the active pattern is 36.98 nm.

On the other hand, the tungsten film shown in Fig. 9 is formed by a pulsed nuclear layer deposition process, and its thickness is relatively uniform. More specifically, the thickness of the tungsten film formed on the bottom of the opening is about 54.43 nm on average, and the thickness of the tungsten film formed on the active pattern is about 46.09 nm.

As compared, the step coverage of the tungsten film formed by the pulsed nuclear layer deposition process is much superior to the tungsten film formed by the physical vapor deposition process.

10 is a table showing resistance of the gate electrode according to the method of forming the tungsten nitride film and the tungsten film.

Referring to FIG. 10, the tungsten nitride films and tungsten films described below may have different formation methods, but the thickness of each tungsten nitride film and each tungsten film is about 50 kPa and about 300 kPa, respectively.

First, the average resistance of the gate electrode including the tungsten film formed by the pulsed nuclear layer deposition process on the tungsten nitride film formed by the physical vapor deposition process is about 4.89 kPa.

The average resistance of the gate electrode including the tungsten film formed by the physical vapor deposition process on the tungsten nitride film formed by the physical vapor deposition process is about 4.91 kV. The resistance similar to that of the gate electrode is shown. However, the tungsten film formed by the physical vapor deposition process has a problem of step coverage as shown in FIG. 10.

On the other hand, it can be seen that the average resistance of the gate electrode including the tungsten film formed by the pulsed nuclear layer deposition process on the tungsten nitride film formed by the pulsed nuclear layer deposition process is about 5.75 kW, which is rather high.

Therefore, it is preferable to form a tungsten nitride film by a physical vapor deposition process and a gate electrode by forming a tungsten film by a pulsed nuclear layer deposition process in terms of resistivity and staff coverage.

As described above, according to a preferred embodiment of the present invention, by forming a tungsten film formed by the pulsed nuclear layer deposition process on the tungsten nitride film formed by the physical vapor deposition process, non-volatile including a gate electrode having a low resistance and excellent staff coverage A memory device can be formed.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (8)

Forming an isolation pattern recessed from the substrate surface to define an active area; Sequentially forming a tunnel insulating layer, a charge trap layer, and a blocking dielectric layer on the device isolation pattern and the active region; Forming a tungsten nitride film (WN) on the blocking dielectric film; And Forming a tungsten film (W) on the tungsten nitride film by using a pulsed nucleation layer (PNL) deposition process. The method of claim 1, wherein the tungsten nitride film is formed by a physical vapor deposition process. The method of claim 1, wherein the pulsed nuclear layer deposition process is performed at a temperature of 200 to 400 ° C. under a pressure of 100 to 400 Torr. The method of claim 1, wherein the tunnel insulating film is silicon oxide (SixOy), the charge trap film is silicon nitride (SixNy), the blocking dielectric film is aluminum oxide (AlxOy), the barrier film is titanium nitride (TiN), tantalum carbide A method of forming a nonvolatile memory device comprising nitride (TaCN) or tantalum nitride (TaN). The method of claim 1, wherein the tungsten film is formed by performing a pulsed nuclear layer deposition process using SiH ₄ or B ₂ H ₆ as a nucleator source and using WF ₆ as a reactor source. A method of forming a nonvolatile memory device characterized by the above-mentioned. The method of claim 1, wherein after the barrier film is formed, Forming a polysilicon film doped with impurities on the barrier film; And And forming an ohmic layer on the polysilicon layer. The method of claim 6, wherein the ohmic layer comprises tungsten silicide (WxSiy). The method of claim 1, wherein forming the device isolation pattern comprises: Sequentially forming a pad oxide film and a mask on the substrate; Etching the pad oxide layer and the substrate using the mask to form a pad oxide layer pattern and a trench; Forming an isolation layer filling the trench on the mask; And And removing an upper portion of the device isolation layer to expose an upper side surface of the active region.

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