KR20080027062A - Scan driver, method of driving scan signal and organic light emitting display device using same - Google Patents

Abstract

SUMMARY OF THE INVENTION An object of the present invention is to provide a scan driver having an effect of size and cost reduction by implementing the scan driver only with a P MOS transistor or an N MOS transistor, and an organic light emitting display device using the same.

A plurality of stages are connected in series and each stage is operated by receiving a clock signal, a sub clock signal, and an input signal, wherein each stage is a voltage of a first voltage and the input signal by the clock signal and the sub clock signal. And a first signal processor which stores a second voltage and generates a first output signal outputting the first voltage for a predetermined time by the sub-clock signal and the second voltage.

Description

SCAN DRIVER, EMISSION CONTROL SIGNAL DRIVING METHOD AND ORGANIC ELECTRO LUMINESCENCE DISPLAY THEREOF}

1 is a structural diagram illustrating a general organic light emitting display device.

FIG. 2 is a circuit diagram illustrating a pixel employed in the organic light emitting display device illustrated in FIG. 1.

3 is a structural diagram illustrating a structure of an organic light emitting display device according to an exemplary embodiment of the present invention.

FIG. 4 is a structural diagram illustrating a scan driver employed in the organic light emitting display device illustrated in FIG. 3.

FIG. 5 is a circuit diagram illustrating a part of a stage employed in the scan driver shown in FIG. 4.

FIG. 6 is a timing diagram illustrating an operation of the stage illustrated in FIG. 5.

FIG. 7 is a circuit diagram illustrating a second embodiment of the stage employed in the scanning driver shown in FIG. 3.

FIG. 8 is a timing diagram illustrating an operation of the stage illustrated in FIG. 7.

The present invention relates to a light emitting control driver, a light emitting control signal driving method, and an organic light emitting display device using the same. More specifically, the light emitting control driver is formed of a PMOS transistor or an N MOS transistor to reduce the size, weight, and cost. The present invention relates to a light emission control driver for obtaining a light emitting device, a light emission control signal driving method, and an organic light emitting display device using the same.

 In a flat panel display, a plurality of pixels are arranged on a substrate to form a display area, and a scan line and a data line are connected to each pixel to selectively apply a data signal to the pixel for display.

The flat panel display is classified into a passive matrix type light emitting display device and an active matrix type light emitting display device according to the driving method of a pixel, and is selected and lit for each unit pixel in view of resolution, contrast, and operation speed. Matrix type is the mainstream.

Such a flat panel display is used as a display device such as a personal information terminal such as a personal computer, a mobile phone, a PDA, or a monitor of various information devices. An organic light emitting display device using a liquid crystal panel, an organic light emitting diode, or a plasma is used. PDPs using panels are known.

Recently, various light emitting display devices having a smaller weight and volume than the cathode ray tube have been developed. In particular, organic light emitting display devices having excellent luminous efficiency, brightness, viewing angle, and fast response speed have been attracting attention.

1 is a structural diagram illustrating a general organic light emitting display device. Referring to FIG. 1, the organic light emitting display device includes a pixel unit 10, a data driver 20, and a scan driver 30.

In the pixel unit 10, a plurality of pixels 11 are arranged and a light emitting element (not shown) is connected to each pixel 11. And n scan lines S1, S2, ... Sn-1, Sn formed in the row direction and transmitting the scan signal, and m data lines D1, D2, forming the column direction and transmitting the data signal. M m power supplies for transmitting the first power supply (Dm-1, Dm) and the first power supply (not shown) and the second power supply ELVss having a lower potential than the first power supply (ELVdd). 2 power supply lines (not shown) are arranged. The pixel unit 10 emits light by the scan signal, the data signal, the first power source ELVdd, and the second power source ELVss to display an image.

The data driver 20 is a means for applying a data signal to the pixel unit 10. The data driver 20 is connected to the data lines D1, D2,... Dm-1, Dm of the pixel unit 10. Connected to apply a data signal to the pixel portion 10.

The scan driver 30 is a means for sequentially outputting scan signals. The scan driver 30 is connected to the scan lines S1, S2,... Pass in a line. A data signal input from the data driver 20 is applied to a specific row of the pixel unit 10 to which the scan signal is transmitted to display an image. When all rows are sequentially selected, one frame is completed.

FIG. 2 is a circuit diagram illustrating a pixel employed in the organic light emitting display device illustrated in FIG. 1. Referring to FIG. 1, the pixel 11 is connected to the data line Dm, the scan line Sn, and the pixel power line ELVdd, and includes the first transistor T1, the second transistor T2, and the capacitor Cst. ) And an organic light emitting diode (OLED).

The first transistor T1 has a source connected to the pixel power line ELVdd, a drain connected to the organic light emitting diode OLED, and a gate connected to the first node N1. The second transistor T2 has a source connected to the data line Dm, a drain connected to the first node N1, and a gate connected to the scan line Sn. The capacitor Cst is connected between the first node N1 and the pixel power line ELVdd to maintain a voltage between the first node N1 and the pixel power line ELVdd for a predetermined time. The organic light emitting diode OLED includes an anode electrode, a cathode electrode, and a light emitting layer, and the anode electrode is connected to the drain of the first transistor T1, and the cathode electrode is connected to the low potential power source ELVSS so that the anode electrode is connected to the cathode electrode. When the current flows, the light emitting layer emits light, and the brightness is adjusted according to the amount of current.

The organic light emitting display device configured as described above simultaneously generates a pixel portion and a scan driver on a substrate in order to reduce manufacturing costs. However, pixels of the organic light emitting display device are generally formed using only P-MOS transistors or are formed using only N-MOS transistors. However, in general, the scan driver uses a P-MOS transistor and an N-MOS transistor together to easily configure a circuit to form the scan driver as a separate external driver or require an additional process, thereby increasing the size of the organic light emitting display device. There is a problem that becomes heavy and the process is complicated.

Therefore, the present invention was created to solve the problems of the prior art, an object of the present invention is to implement a scan driving unit only with a P MOS transistor or N MOS transistor to simplify the process of the scan driver having the effect of size and cost reduction And an organic light emitting display device using the same.

A first aspect of the present invention for achieving the above object, a plurality of stages are configured in series, each stage is operated by receiving a clock signal, a sub-clock signal and an input signal, the clock signal and the sub Generating a first output signal for storing a first voltage and a second voltage as a voltage of the input signal by a clock signal, and outputting the first voltage for a predetermined time by the sub-clock signal and the second voltage; A scan driver including a first signal processor is provided.

In order to achieve the above object, a second aspect of the present invention provides a data line, a pixel portion representing an image by pixels formed in a region defined by a scanning line, a data driver transferring a data signal to the data line, and the scanning line. A scan driver for transmitting a scan signal to the scan driver, wherein the scan driver includes a plurality of stages connected in series, and each stage operates by receiving a clock signal, a sub-clock signal, and an input signal. And a first output signal configured to store a first voltage and a second voltage which is a voltage of the input signal by the subclock signal, and output the first voltage for a predetermined time by the subclock signal and the second voltage. It is to provide an organic light emitting display device comprising a first signal processing unit for generating a.

In order to achieve the above object, a third aspect of the present invention includes a plurality of stages, each of which sequentially drives a scanning signal in each stage, wherein the first voltage and the second voltage are driven by a clock signal and a sub-clock signal. And storing a first output signal based on the stored first voltage, the second voltage, and the sub-clock signal.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

3 is a structural diagram illustrating a structure of an organic light emitting display device according to an exemplary embodiment of the present invention. Referring to FIG. 3, the organic light emitting display device includes a pixel unit 100, a data driver 200, and a scan driver 300.

The pixel unit 100 includes a plurality of data lines D1, D2... Dm-1, Dm and a plurality of scanning lines S1, S2 ... Sn-1, Sn, and a plurality of data lines D1. And a plurality of pixels formed in a region defined by D2 ... Dm-1, Dm and a plurality of scan lines S1, S2 ... Sn-1, Sn. The pixel 101 includes a pixel circuit and an organic light emitting element, and a data signal and a plurality of scan lines S1 and S2 transmitted through a plurality of data lines D1, D2... The pixel current flowing through the pixel is generated by the scan signal transmitted through the Sn-1, Sn) and flows to the organic light emitting device. In this case, each pixel includes a plurality of thin film transistors, and each thin film transistor is formed of only a P MOS transistor or an N MOS transistor.

The data driver 200 is connected to the plurality of data lines D1, D2 ... Dm-1, Dm, and generates a data signal to sequentially convert the data signals of one row into the plurality of data lines D1, D2 .. To .Dm-1, Dm).

The scan driver 300 is connected to the plurality of scan lines S1, S2 ... Sn-1, Sn, and generates a scan signal and transmits the scan signal to the plurality of scan lines S1, S2 ... Sn-1, Sn. A specific row is selected by the scan signal, and a data signal is transmitted to the pixel 101 positioned in the selected row, so that a current corresponding to the data signal is generated in the pixel. In this case, the scan driver 300 is formed of a P MOS transistor when the thin film transistor of the pixel unit 100 is formed of a P MOS transistor, and is formed of only an N MOS transistor when the pixel unit 100 is formed of an N MOS transistor. It is formed through the same process.

FIG. 4 is a structural diagram illustrating a scan driver employed in the organic light emitting display device illustrated in FIG. 3. Referring to FIG. 4, the scan driver 300 has a plurality of stages 301.302... 30n-1,30n connected in series, and the first stage 301 of each stage has a clock signal CLK and a subclock. The stages 302, 303, ... 30n-1, 30n except for the first stage 301 after receiving the signal CLKB and the start pulse SP are included in the clock signal CLK, the sub-clock signal CLKB, and the previous stage. Scan signals S1, S2 ... Sn-1 as output signals are input.

FIG. 5 is a circuit diagram illustrating a part of a stage employed in the scan driver shown in FIG. 4. Referring to FIG. 5, a first stage and a second stage are shown, and the first stage 301 includes a first signal processor, a second signal processor, and a third signal processor, and the second stage 302 includes a fourth signal processor. And a fifth signal processor and a sixth signal processor.

The first signal processor includes a first transistor M1 having a source connected to a first power supply Vpos, a gate connected to a clock terminal CLK, and a drain connected to a first node N1, and a source connected to a first node. The second transistor M2 and the source are connected to the second node N2, the gate is connected to the second node N2, the drain is connected to the subclock terminal CLKB, and the source is connected to the second node N2, and the gate is connected to the clock terminal (N1). The drain includes a third transistor M3 connected to the start pulse input terminal and a first capacitor C1 connected between the first node N1 and the second node N2.

The second signal processor includes a fourth transistor M4 and a source connected to a first power source Vpos, a gate connected to a first node N1, a drain connected to a third node N3, and a source connected to a third node. A fifth transistor M5 and a source connected to N3, a gate connected to a first node N1, a drain connected to a fourth node N4, and a source connected to a third node N3, and a gate connected to a fourth node N3. The sixth transistor M6 and the source connected to the node N4 and the drain connected to the first power source Vneg having a voltage lower than the first power source Vpos and the source connected to the fourth node N4 and the gate are clocked. A seventh transistor M7 connected to the terminal CLK and a drain connected to the first power source Vneg and a second capacitor C2 connected between the third node N3 and the fourth node N4. It includes.

The third signal processor includes an eighth transistor M8 having a source connected to a first power supply Vpos, a gate connected to a fourth node N4, a drain connected to a fifth node N5, and a source connected to a fifth node. A ninth transistor M9 and a source connected to N5 and a gate connected to a fourth node N4, a drain connected to a sixth node N6, and a source connected to a fifth node N5, and a gate connected to a sixth node N4. An eleventh transistor connected to the node N6, a drain connected to the first power source Vneg, a source connected to the sixth node N6, and a gate connected to the third node N3. And a third capacitor C3 connected between the fifth node N5 and the sixth node N6. The fifth node N5 is used as an output terminal OUT.

The fourth signal processor is connected to the first power source Vpos, the source is input to the clock terminal, the drain is connected to the seventh node N7, and the source is connected to the seventh node N7. The twelfth transistor M12 and the source connected to the eighth node N8, the gate connected to the eighth node N8, the drain connected to the subclock terminal CLKB, and the gate connected to the eighth node N8, and the gate connected to the clock terminal CLK. The drain includes a thirteenth transistor M13 connected to an output terminal OUT of the first stage 301 and a fourth capacitor C4 connected between the seventh node N7 and the eighth node N8. do.

The fifth signal processor includes a fourteenth transistor M14 having a source connected to a first power supply Vpos, a gate connected to a seventh node N7, a drain connected to a ninth node N9, and a source connected to a ninth node. A fifteenth transistor M15 and a source connected to a N9 node, a gate connected to a seventh node N7, a drain connected to a tenth node N10, a source connected to a ninth node N9, and a gate connected to a tenth node N9; A sixteenth transistor M16 and a source connected to the node N10 and a drain connected to the first power supply Vneg having a voltage lower than the first power supply Vpos and a source connected to the tenth node N10 and a gate of the clock are connected. The drain includes a seventeenth transistor M17 connected to the terminal CLK and a fifth capacitor C5 connected between the ninth node N9 and the tenth node N10. do.

The sixth signal processor is an eighteenth transistor M18 having a source connected to a first power supply Vpos, a gate connected to a tenth node N10, a drain connected to an eleventh node N11, and a source connected to an eleventh node. A nineteenth transistor M19 connected to an N11, a gate connected to a tenth node N10, a drain connected to a twelfth node N12, and a source connected to an eleventh node N11, and a gate connected to a twelfth node N12; An eleventh transistor connected to a node N12, a drain connected to a first power source Vneg, a source connected to a twelfth node N12, and a gate connected to a ninth node N9; M6 and a sixth capacitor C6 connected between the eleventh node N11 and the twelfth node N12. The eleventh node N11 is used as an output terminal OUT.

The first through twentieth transistors included in the first signal processor, the second signal processor, the third signal processor, the fourth signal processor, the fifth signal processor, and the sixth signal processor are implemented as P MOS transistors.

FIG. 6 is a timing diagram illustrating an operation of the stage illustrated in FIG. 5. Referring to FIG. 6, the operation of the stage of FIG. 5 will be described. The first signal processor receives the clock signal CLK, the sub clock signal CLKB, and the start pulse SP, and the second signal processor operates the clock. A signal CLK and an output signal of the first signal processor, that is, a voltage of the first node N1 are received and operated, and the third signal processor is an output signal of the first signal processor, that is, a voltage of the first node N1. And an output signal of the second signal processor, that is, a voltage of the third node N3. The fourth signal processor receives the clock signal CLK, the sub clock signal CLKB, and the start pulse SP. The fourth signal processor operates the clock signal CLK and the output signal of the fourth signal processor, that is, the first signal. The sixth signal processor is operated by receiving the voltage of the seventh node N7, and the sixth signal processor is an output signal of the fourth signal processor, that is, the voltage of the seventh node N7 and the output signal of the second signal processor, that is, the ninth node N9. It operates in response to the voltage of.

When the clock signal CLK is low, the start pulse SP is high, and the sub clock signal CLKB is high, the first signal processor is turned on. In this state, the first node N1 is transferred to the high state by transmitting the first power supply Vpos, and the second node N2 is also transferred to the high state by the start pulse SP. The voltage of the first node N1 and the voltage of the second node N2 are maintained by the first capacitor C1. In addition, the voltage of the second node N2 becomes high so that the second transistor M2 is kept off. Therefore, the voltage of the first node N1 maintains the voltage of the first power source Vpos.

When the clock signal CLK is in a high state, the start pulse SP is in a high state, and the sub clock signal CLKB is in a low state, the first transistor M1 and the third transistor M3 are turned off. Both ends of the first capacitor C1 are in a floating state. Therefore, the first node N1 maintains the voltage of the first power supply Vpos by the first capacitor C1 and the gate voltage of the second transistor M2 also remains high by the first capacitor C1. To remain off.

When the clock signal CLK is low, the start pulse SP is low, and the sub clock signal CLKB is high, the first transistor M1 and the third transistor M3 are turned on. The first node N1 is supplied with the first power source Vpos and the second node N2 is turned low by the start pulse SP. At this time, the drain of the second transistor M2 becomes high by the sub clock signal CLKB, so that current does not flow in the direction of the drain from the source of the second transistor M2. Therefore, the voltage of the first node N1 maintains the voltage of the first power source Vpos.

When the clock signal CLK is high, the start pulse SP is high, and the sub clock signal CLKB is low, the first transistor M1 and the third transistor M3 are turned off. Both ends of the first capacitor C1 are in a floating state, and the second node N2 is kept low. Therefore, the gate voltage of the second transistor M2 is kept low, so that a current path is formed in the drain direction of the source of the second transistor M2, thereby lowering the voltage of the first node N1. At this time, the voltage of the first node N1 is kept low by the first capacitor C1 so that the voltage of the first node N1 can be lowered by the voltage Vneg of the second power supply. Signal characteristics are improved.

The second signal processing unit maintains the voltage of the third node N3 when the clock signal CLK is high and maintains the voltage of the first power supply Vpos and the voltage of the third node N3 when the clock signal CLK is high. The voltage of the first power source Vneg is set.

In addition, when the voltage of the first node N1 is high and the voltage of the third node N3 is low, the third signal processing unit has a high voltage of the fifth node N5, that is, the voltage of the output terminal OUT. Is maintained, and when the voltage of the first node N1 is low and the voltage of the third node N3 is high, the voltage at the voltage output terminal of the fifth node N5 is kept low.

The second stage 301 performs the same operation as the first stage 301, but receives the voltage of the output terminal OUT of the first stage 301, that is, the first scan signal S1, instead of the start pulse SP. It works.

FIG. 7 is a circuit diagram illustrating a second embodiment of the stage employed in the scan driver illustrated in FIG. 3, and FIG. 8 is a timing diagram illustrating the operation of the stage illustrated in FIG. 7. The stage is composed of a first signal processor, a second signal processor, and a third signal processor. A difference from FIGS. 4 and 5 is that the thin film transistors included in each signal processor are implemented with N MOS transistors.

According to the present invention, a scan driver, a scan signal driving method, and an organic light emitting display device using the same can be implemented using a P MOS transistor or an N MOS transistor. Since the scan driver may be implemented using only a P MOS transistor or an N MOS transistor, the scan driver may be formed on the substrate simultaneously with the pixel unit, thereby simplifying the process and reducing the size and weight of the organic light emitting display device. In addition, cost savings are also seen.

In addition, it is possible to improve the signal characteristics of the scan signal by allowing the scan signal to have the voltage of the second power supply.

While preferred embodiments of the present invention have been described using specific terms, such descriptions are for illustrative purposes only and it is understood that various changes and modifications may be made without departing from the spirit and scope of the following claims. You must lose.

Claims (23)

A plurality of stages are connected in series, and each stage operates by receiving a clock signal, a sub clock signal, and an input signal. A second voltage which is a voltage of a first voltage and the input signal is stored by the clock signal and the subclock signal, and outputs the first voltage for a predetermined time by the subclock signal and the second voltage. 1. A scan driver including a first signal processor configured to generate an output signal. The method of claim 1, It is connected to the output terminal of the first signal processor, A second signal processor configured to receive the first output signal and the clock signal to generate a second output signal; And And a third signal processor configured to receive the first output signal and the second output signal and generate a third output signal which is a sub-signal of the second output signal. The method of claim 1, And the input signal is a start pulse when the stage is the first stage. The method of claim 1, And the input signal is an output terminal signal of a previous stage when the stage is not the first stage. The method of claim 1, The first signal processor, A first transistor selectively transferring the driving power to a first node by the clock signal; A second transistor configured to selectively adjust a voltage of the first node in response to a voltage of a second node; A third transistor configured to transfer a voltage of the input signal to the second node in response to the clock signal; And A first capacitor connected between the first node and the second node to store a voltage of the driving power source and the input signal, And the voltage of the first node is the first output signal. The method of claim 2, The second signal processor A fourth transistor configured to transfer driving power to a third node in response to the first output signal; A fifth transistor for selectively equalizing voltages of the third node and a fourth node in response to the first output signal; A sixth transistor configured to adjust the voltage of the third node in response to the voltage of the fourth node; A seventh transistor configured to adjust a voltage of the fourth node in response to the clock signal; And A second capacitor connected between the third node and the fourth node, And the voltage of the third node is the second output signal. The method of claim 2, The third signal processor An eighth transistor configured to transfer driving power to a fifth node in response to the second output signal; A ninth transistor selectively equalizing voltages of the fifth node and the sixth node corresponding to the second output signal; A tenth transistor configured to adjust a voltage of the fifth node corresponding to the voltage of the sixth node; An eleventh transistor configured to adjust a voltage of the sixth node in response to the first output signal; And A third capacitor connected between the fifth node and the sixth node, And the voltage of the fifth node is the third output signal. The method according to any one of claims 6 to 8, The transistor is a scan driver consisting of only one transistor of the P MOS transistor or N MOS transistor. The method of claim 1, The odd-numbered stage and the even-numbered stage of the plurality of stages are the scan driving unit to which the clock signal and the sub-clock signal cross each other. A pixel portion expressing an image by pixels formed in regions defined by data lines and scanning lines; A data driver for transmitting a data signal to the data line; And Including a scan driver for transmitting a scan signal to the scan line, The scan driving unit, A plurality of stages are connected in series, and each stage operates by receiving a clock signal, a sub clock signal, and an input signal. A second voltage which is a voltage of a first voltage and the input signal is stored by the clock signal and the subclock signal, and outputs the first voltage for a predetermined time by the subclock signal and the second voltage. 1. An organic light emitting display device comprising a first signal processor configured to generate an output signal. The method of claim 10, It is connected to the output terminal of the first signal processor, A second signal processor configured to receive the first output signal and the clock signal to generate a second output signal; And And a third signal processor configured to receive the first output signal and the second output signal and generate a third output signal which is a sub-signal of the second output signal. The method of claim 10, And the input signal is a start pulse when the stage is a first stage. The method of claim 10, And the input signal is an output terminal signal of a previous stage when the stage is not the first stage. The method of claim 10, The first signal processor, A first transistor selectively transferring the driving power to a first node by the clock signal; A second transistor configured to selectively adjust a voltage of the first node in response to a voltage of a second node; A third transistor configured to transfer a voltage of the input signal to the second node in response to the clock signal; And A first capacitor connected between the first node and the second node to store a voltage of the driving power source and the input signal, The organic light emitting display device of claim 1, wherein the voltage at the first node is the first output signal. The method of claim 11, The second signal processor A fourth transistor configured to transfer driving power to a third node in response to the first output signal; A fifth transistor for selectively equalizing voltages of the third node and a fourth node in response to the first output signal; A sixth transistor configured to adjust the voltage of the third node in response to the voltage of the fourth node; A seventh transistor configured to adjust a voltage of the fourth node in response to the clock signal; And A second capacitor connected between the third node and the fourth node, And the voltage at the third node is the second output signal. The method of claim 11, The third signal processor An eighth transistor configured to transfer driving power to a fifth node in response to the second output signal; A ninth transistor selectively equalizing voltages of the fifth node and the sixth node corresponding to the second output signal; A tenth transistor configured to adjust a voltage of the fifth node corresponding to the voltage of the sixth node; An eleventh transistor configured to adjust a voltage of the sixth node in response to the first output signal; And A third capacitor connected between the fifth node and the sixth node, And a voltage at the fifth node is the third output signal. The method according to any one of claims 14 to 16, And the transistor comprises only one of a P-MOS transistor and an N-MOS transistor. The method of claim 10, The odd numbered stage and the even numbered stage of the plurality of stages are configured such that a clock signal and a sub clock signal cross each other and are transmitted. In the method comprising a plurality of stages and sequentially driving the scanning signal in each stage, Storing the first voltage and the second voltage by the clock signal and the sub clock signal; And And generating a first output signal based on the stored first voltage, the second voltage, and the sub-clock signal. The method of claim 19, And the input signal is a start pulse when the stage is the first stage. The method of claim 19, And the input signal is an output terminal signal of a previous stage when the stage is not the first stage. The method of claim 19, And the first output signal is inverted and output. The method of claim 19, The odd numbered stage and the even numbered stage of the plurality of stages are configured to drive a scan signal in which a clock signal and a sub clock signal cross each other.

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