KR20080004305A - Method of manufacturing a flash memory device - Google Patents

Abstract

A method for manufacturing a flash memory device is provided to reduce interference effect between cells by gap-filling a region between gate patterns with a conductive material to block electric field formed between floating gates. Gate patterns of plural memory cells are formed on a semiconductor substrate(100). A dielectric(106) is formed on the whole structure including gate patterns of the memory cells. A space between gate patterns of memory cells is not perfectly gap-filled. A conductive GAP(Ground Assistance plate) layer(107) is formed on the semiconductor substrate including the dielectric. The space between the gate patterns of the memory cells is gap-filled. A contact and a metal wire are formed on the GAP layer so that a ground voltage is applied. The gate patterns of the memory cells are comprised of a laminated structure of a tunnel oxide layer(101), a conductive layer(102) for a floating gate, a dielectric(103), and a conductive layer(104) for a control gate. The conductive layers for a floating gate and a control gate are formed with a poly silicon. Further, the dielectric layer is formed by laminating in order of a first oxidation layer, a nitrification layer and a second oxidation layer.

Description

Method of manufacturing a flash memory device

1 is a cross-sectional view of a device for explaining a method of manufacturing a flash memory device according to the prior art.

2 is a graph illustrating a relationship between an interference ratio and a coupling ratio according to a height of a floating gate and a distance between floating gates of a flash memory device.

3 to 7 are cross-sectional views of devices for describing a method of manufacturing a flash memory device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 101 tunnel oxide film

102 conductive film for floating gate 103 dielectric film

104: conductive film for control gate 105: hard mask layer

106: insulating film 107: GAP layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device that reduces the interference between floating gates and increases the coupling ratio.

In a NAND type flash memory device, a plurality of cells for storing data are connected in series to form a string, and a drain select transistor and a source select transistor are formed between the cell string and the drain and the cell string and the source, respectively. A cell of such a NAND flash memory device is formed by forming a gate in which a tunnel oxide film, a floating gate, a dielectric film, and a control gate are stacked in a predetermined region on a semiconductor substrate, and forming junctions on both sides of the gate.

In such a NAND flash memory device, it is very important to keep the cell state constant because the state of the cell is affected by the operation of adjacent neighboring cells. The change of the state of the cell due to the operation of adjacent neighboring cells, in particular the program operation, is called an interference effect. That is, the interference effect means that when the second cell adjacent to the first cell to be read is programmed, the threshold voltage of the first cell is higher than the threshold voltage of the first cell when the first cell is read due to the capacitance action caused by the charge change of the floating gate of the second cell. This refers to a phenomenon in which the threshold voltage is read, and refers to a phenomenon in which the state of the actual cell is distorted by the change of the state of the adjacent cell, although the charge of the floating gate of the read cell does not change. This interference effect causes the state of the cell to change, which results in an increase in the defective rate resulting in a lower yield. Therefore, minimizing the interference effect can be said to be effective to keep the state of the cell constant.

Meanwhile, a part of the device isolation layer and the floating gate are formed by using a self-aligned shallow trench isolation (SA-STI) process in a manufacturing process of a general NAND flash memory device. Referring to FIG. Is the same as

After the tunnel oxide film 11 and the first polysilicon film 12 are formed on the semiconductor substrate 10, predetermined regions of the first polysilicon film 12 and the tunnel oxide film 11 are etched to form a semiconductor substrate 10. ) To form a trench by etching to a predetermined depth, then the insulating film is embedded and the polishing process is performed to form the device isolation film (13). Thereafter, the second polysilicon layer 14 is formed and etched to form floating gates 12 and 14. The dielectric film 15 and the polysilicon film 16 for the control gate are formed on the floating gates 12 and 14.

When the flash memory device is manufactured using the SA-STI process as described above, since the device isolation layer is formed between the first polysilicon film 12 serving as the floating gate and the adjacent first polysilicon film 12, Interference may occur between the 1 polysilicon layers 12.

2 is a graph showing the interference effect and the coupling ratio according to the height and distance between the floating gates.

Referring to FIG. 2, the gate-to-gate interface is proportional to the distance between the floating gates and the height of the floating gates. That is, when the distance between the floating gates is far and the height of the floating gate decreases, the interference decreases. On the contrary, when the height of the floating gate is decreased, the interface area between the floating gate and the control gate is decreased, thereby reducing the coupling ratio.

The technical problem to be achieved by the present invention is to prevent the area between the gate pattern is completely filled with an insulating film, and then completely fill the area between the gate pattern with a conductive material, and the ground voltage is applied to the conductive material, the inter-cell interference effect It is to provide a method of manufacturing a flash memory device that can reduce the.

A method of manufacturing a flash memory device according to an embodiment of the present invention includes performing a wall forming ion implantation process and an ion implantation process for adjusting a threshold voltage on a semiconductor substrate, and a plurality of gates of memory cells on the semiconductor substrate. Forming patterns, forming an insulating film on the entire structure including the gate patterns of the plurality of memory cells, and forming a space between the gate patterns of the plurality of memory cells so as not to completely fill the space; Forming a GAP layer, which is a conductive material, on the semiconductor substrate, wherein the spaces between gate patterns of the plurality of memory cells are completely filled; and contacting and metal wiring to apply a ground voltage to the GAP layer. Forming a step.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

3 to 7 are cross-sectional views of devices for describing a method of manufacturing a flash memory device according to an embodiment of the present invention.

Referring to FIG. 3, a wall forming ion implantation process and an ion implantation process for adjusting the threshold voltage are performed on the semiconductor substrate 100.

Referring to FIG. 4, a tunnel oxide film 101, a floating gate conductive film 102, a dielectric film 103, a control gate conductive film 104, and a hard mask layer 105 are formed on a semiconductor substrate 100. Form sequentially. The floating gate conductive film 102 and the control gate conductive film 104 may be formed of a polysilicon layer. The dielectric film 103 may be formed in an ONO structure in which a first oxide film, a nitride film, and a second oxide film are sequentially stacked.

Referring to FIG. 5, a hard mask pattern 105 is formed by etching a hard mask layer by an etching process using a mask, and a conductive gate 104 and a dielectric film for the control gate are formed by an etching process using the hard mask pattern 105. The gate pattern is formed by sequentially etching the 103, the floating gate conductive film 102, and the tunnel oxide film 101. In this case, the gate pattern includes a memory cell gate pattern in which memory cells are formed and a source and drain select transistor gate pattern in which source and drain select transistors are formed.

Referring to FIG. 6, an insulating film 106 is formed on the entire structure including the gate pattern. In this case, the insulating layer 106 is preferably formed so that the space between the gate patterns is not completely filled. The insulating film 106 is preferably formed of an oxide film or a nitride film. In addition, the insulating film 106 may be formed in a double structure of an oxide film and a nitride film. The process of forming the insulating film 106 is a process of depositing an oxide film and a nitride film sequentially, and then removing the spacers deposited on the contact portion of the peripheral circuit (not shown), selectively opening the cell region after the dry etching process to the nitride film By selectively removing the space between the gate patterns can be formed. At this time, the thickness of the oxide film is preferably 10 kPa to 1000 kPa. Moreover, it is preferable that the thickness of a nitride film is 10 kPa-1000 kPa.

Referring to FIG. 7, a GAP layer (Ground Assistance Plate) 107 is formed on the entire structure including the insulating layer 106. The GAP layer 107 is preferably formed so that the empty space between the gate patterns is completely filled. The GAP layer 107 is preferably formed of a conductive material. Instead of the GAP layer 107, polycrystalline silicon into which impurities are implanted may be used so that the empty spaces between the gate patterns may be completely filled. In addition, a metal layer may be used instead of the GAP layer 107, and polycrystalline silicon and a metal layer may be used as the composite layer.

Thereafter, although not shown in the drawings, the GAP layer 107 formed in the peripheral circuit region is removed through a photo process and an etching process. Thereafter, a ground voltage (0V) may be applied to the GAP layer 107 through a contact forming process and a metal wiring forming process. At this time, the GAP layer 107 is preferably formed with an insulating film having a predetermined thickness as a layer without being bonded to the junction of the cell. In addition, the GAP layer 107 is preferably connected to a common source line of the string so that the ground voltage is applied. By the GAP layer 107 to which the ground voltage is applied, the memory cell gate may block an electric field with an adjacent memory cell gate. As a result, the interference effect between adjacent cells can be reduced.

As described above, a method of reading a flash memory device according to an exemplary embodiment of the present invention will be described below.

A read voltage is applied to a gate of a selected memory cell to be read among the plurality of memory cells. As a result, a channel may or may not be formed according to the program state of the selected memory cell. At this time, a passing voltage is applied to the gates of the unselected memory cells, so that channels are formed in all of the unselected memory cells. In addition, a power supply voltage Vcc is applied to the gates of the source and drain select transistors to be turned on.

In the read operation, capacitance between both cells is blocked by a GAP layer connected to a ground voltage in a space between a plurality of memory cells and a space between a memory cell and a source or drain select transistor. Therefore, the interference effect can be blocked during the read operation. This has the same effect in the erase operation and the program operation.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to an embodiment of the present invention, after the regions between the gate patterns are not completely filled with the insulating layer, the regions between the gate patterns are completely filled with the conductive material and a ground voltage is applied to the conductive material. As a result, the interference effect between the cells may be reduced by blocking an electric field formed between the floating gates.

Claims (11)

Forming gate patterns of a plurality of memory cells on a semiconductor substrate; Forming an insulating layer on the entire structure including the gate patterns of the plurality of memory cells, wherein the spaces between the gate patterns of the plurality of memory cells are not completely filled; Forming a GAP layer of a conductive material on the semiconductor substrate including the insulating layer, and forming a gap between the gate patterns of the plurality of memory cells; And Forming a contact and a metal wire to apply a ground voltage to the GAP layer. The method of claim 1, wherein the gate patterns of the memory cell are formed. A method of manufacturing a flash memory device having a structure in which a tunnel oxide film, a floating gate conductive film, a dielectric film, and a control gate conductive film are sequentially stacked. The method of claim 2, wherein the floating gate conductive film and the control gate conductive film are made of polysilicon. The method of claim 2, wherein the dielectric film is formed in an ONO structure in which a first oxide film, a nitride film, and a second oxide film are sequentially stacked. The method of manufacturing a flash memory device according to claim 1, wherein the insulating film can be formed by an oxide film, a nitride film, or a double composition of an oxide film and a nitride film. The method of claim 1, wherein the insulating film Sequentially depositing an oxide film and a nitride film; And Forming a space between the gate patterns of the memory cells by selectively opening the cell region and selectively removing the nitride layer after the dry etching process in the process of removing the spacers deposited on the contact portion of the peripheral circuit region. Method of manufacturing a flash memory device. The method of claim 6, wherein each of the oxide film and the nitride film A method of manufacturing a flash memory device, which is formed to a thickness of 10 ns to 1000 ns. The method of claim 1, A method of manufacturing a flash memory device, which is formed of polycrystalline silicon, a metal layer, or a composite layer of silicon and a metal layer into which impurities are implanted instead of the GAP layer. The method of claim 1, And the GAP layer is connected to a common source line of a string. Forming gate patterns of a plurality of memory cells and source and drain select transistors on the semiconductor substrate; Forming an insulating film on the entire structure including the gate patterns, wherein the space between the gate patterns is not completely filled; Forming a GAP layer of a conductive material on the semiconductor substrate including the insulating layer, wherein the space between the plurality of gate patterns is completely filled; And Forming a contact and a metal wire to apply a ground voltage to the GAP layer. A method of reading a flash memory device including a GAP layer connected to a ground voltage in a space between a plurality of memory cells and a plurality of source and drain select transistors. Applying a read voltage to a gate of a selected memory cell of the plurality of memory cells; Blocking capacitance between adjacent memory cells by a GAP layer connected to the ground voltage; And And applying a power supply voltage to gates of the source and drain select transistors to read program data of the selected memory cell.

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