KR20070081416A - Method of manufacturing thin film transistor array substrate - Google Patents

Abstract

A method of manufacturing a thin film transistor array substrate having improved process reliability is provided. A method of manufacturing a thin film transistor array substrate includes forming a protective film on an insulating substrate on which a thin film transistor including a gate electrode, a source electrode, and a drain electrode and a sustain electrode are formed, applying an organic film on the entire surface of the protective film; Face the organic film and press an imprint mold defining a contact hole region, the first protrusion protruding from the surface by a first height, and a second protrusion defining the sustain electrode region, and protruding from the surface by a second height Transferring the pattern of the imprint mold, and separating the imprint mold from the organic layer, the contact recess transferred from the first protrusion and the sustain electrode transferred from the second protrusion and positioned on the contact recess transferred from the first protrusion. And a minimum distance between the contact recess and the passivation layer, wherein the contact electrode recess and the passivation layer And in comprising the step of forming an organic film pattern smaller than the minimum distance.

Description

Method for fabricating thin flim transistor array substrate

1 is a schematic plan view of a thin film transistor array substrate fabricated by a method according to an embodiment of the present invention.

FIG. 2 is a plan view of a pixel structure of the thin film transistor array substrate of FIG. 1.

3 is a cross-sectional view taken along line III-III ′ of FIG. 2.

4 through 17 are cross-sectional views illustrating the process steps of a method of manufacturing a thin film transistor array substrate in accordance with an embodiment of the present invention.

18 is a cross-sectional view of a thin film transistor array substrate manufactured by a method according to another embodiment of the present invention.

19 to 24 are cross-sectional views illustrating process steps of a method of manufacturing a thin film transistor array substrate according to another exemplary embodiment of the present invention.

25 is a cross-sectional view of a thin film transistor array substrate manufactured by a method according to another embodiment of the present invention.

26 to 31 are cross-sectional views of steps in a method of manufacturing a thin film transistor array substrate according to still another embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10: insulating substrate 24: gate electrode

30: gate insulating film 44: semiconductor layer

55, 56: ohmic contact 65: source electrode

66: drain electrode 70: protective film

72: organic film 82: reflective electrode

85: dummy reflective electrode 92: pixel electrode

95: thin film transistor array substrate 200: imprint mold

The present invention relates to a method of manufacturing a thin film transistor array substrate, and more particularly, to a method of manufacturing a thin film transistor array substrate with improved process reliability.

In today's information society, the role of electronic display devices becomes more and more important, and various electronic display devices are widely used in various industrial fields. In addition, due to the rapid advancement of semiconductor technology, electronic display devices suitable for a new environment, that is, thin and light, low driving voltage, and low power consumption, are becoming more solid due to the solidification, low voltage, and low power of various electronic devices, as well as the small size and light weight of electronic devices. The demand for a flat panel type display device with a rapidly increasing number.

Among the various flat panel display devices currently developed, liquid crystal displays are thinner and lighter than other display devices, have low power consumption and low driving voltage, and are widely used in various electronic devices because they are capable of displaying images close to cathode ray tubes. Is being used.

Such a liquid crystal display includes a thin film transistor array substrate, an opposing substrate opposing thereto, and a liquid crystal layer interposed between the substrates, and by adjusting the arrangement direction of the liquid crystal molecules for each pixel, thereby controlling the transmittance of light incident from the backlight. To display the gradation.

Here, the thin film transistor array substrate includes various types of fine patterns in order to form an electric field for adjusting the arrangement direction of the liquid crystal molecules. Conventionally, a photolithography method has been widely used as a pattern transfer technique for forming such fine patterns. However, while the finer the pattern, the more the pattern size is limited by the wavelength of the light used for exposure, and a mechanism for precisely controlling the mask position is required. Formation method is required.

An object of the present invention is to provide a method for manufacturing a thin film transistor array substrate with improved process reliability.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to another aspect of the present invention, a method of manufacturing a thin film transistor array substrate includes forming a protective film on an insulating substrate on which a thin film transistor including a gate electrode, a source electrode, and a drain electrode and a sustain electrode are formed. And applying an organic film to the entire surface of the protective film, defining a contact hole region, defining a first protrusion projecting from the surface by a first height, and a sustain electrode region, and protruding from the surface by a second height. Transferring the pattern of the imprint mold by pressing an imprint mold including the second protrusion on the organic layer and pressing the imprint mold; and separating the imprint mold from the organic layer and positioned above the drain electrode. A contact concave transferred from the upper portion of the sustain electrode and the sustain electrode; Forming an organic layer pattern including a sustain electrode recessed portion transferred from the portion, wherein a minimum distance between the contact recess and the passivation layer is smaller than a minimum distance between the sustain electrode recess and the passivation layer.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array substrate, including forming a protective film on an insulating substrate on which a thin film transistor including a gate electrode, a source electrode, and a drain electrode is formed; And applying a photoresist film on the passivation layer and relatively between the first concave portion having a first depth, the second concave portion having a second depth smaller than the first depth, and the first and second concave portions. The imprint mold including the protrusions is aligned with the photoresist film such that the first recess is located in the thin film transistor region, the second recess is located in the pixel electrode region, and the protrusion is located in the drain electrode region. And pressing the imprint mold against the photoresist film and pressing the imprint mold. And transferring the imprint mold from the photoresist layer to the first region transferred from the first recessed portion and the pixel region located at the pixel region. And a third region on the drain electrode and transferred from the protrusion, wherein the thickness of the second region is less than the thickness of the first region and is greater than the thickness of the third region. Forming a step.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array substrate, including forming a protective film on an insulating substrate on which a thin film transistor including a gate electrode, a source electrode, and a drain electrode is formed. And a step of coating a photoresist film on the passivation layer, and forming an imprint mold made of a soft polymer resin, the first recess being formed of a soft polymer resin, the first recess being narrower than the width of the upper sidewall. Aligning the photoresist layer so as to be positioned; transferring the pattern of the imprint mold by pressing and pressing the imprint mold against the photoresist film; and separating the imprint mold from the photoresist film to separate the thin film transistor region. Located in the first concave portion And forming a photoresist pattern including a first transfer area.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

As used herein, the term "thin film transistor array substrate" refers to a substrate including at least one thin film transistor, and does not exclude a case where another structure is interposed between the thin film transistor and the substrate or another structure is formed thereon. Do not.

Hereinafter, a thin film transistor array substrate according to an embodiment of the present invention will be described with reference to the accompanying drawings. 1 is a schematic plan view of a thin film transistor array substrate according to an embodiment of the present invention.

Referring to FIG. 1, the thin film transistor array substrate 95 includes a plurality of thin film transistors Q arranged on the insulating substrate 10 based on the insulating substrate 10. One thin film transistor Q is disposed for each pixel arranged in a matrix, and an output terminal of the thin film transistor Q is connected to the pixel electrode 92. In addition, the pixel electrode 92 covers most of the region of each pixel. The control terminal of the thin film transistor Q is connected to the gate line 22 extending in the first direction, and the input terminal of the thin film transistor Q is connected to the data line 62 extending in the second direction. . The storage electrode line 28 extends along the gate line 22, and is branched along the data line 62 for each pixel to form the storage electrode 29. The gate line 22 and the data line 62 are arranged in parallel with each other, and the gate line 22 and the data line 62 are insulated from each other and cross each other in the region where the thin film transistor Q is formed.

Each pixel of the thin film transistor array substrate 95 basically has the same structure. The pixel structure of the thin film transistor array substrate will be described in more detail.

FIG. 2 is a plan view of a pixel structure of the thin film transistor array substrate of FIG. 1. 3 is a cross-sectional view taken along line III-III ′ of FIG. 2.

2 and 3, the gate line 22 is adjacent to the gate line 22 and the gate line 22 extending in the first direction on an insulating substrate 10 made of a transparent material such as glass. The storage electrode lines 29 extending in parallel are formed. The gate electrode 24 is formed to extend from the gate line 22, and the sustain electrode 29 is branched from the sustain electrode line 28 to extend along the data line 62. The gate line 22, the gate electrode 24, the storage electrode line 28, and the storage electrode 29 are, for example, aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), and chromium. (Cr), titanium (Ti), tantalum (Ta), or an alloy thereof.

The gate line 22 and the gate electrode 24 are covered with the gate insulating film 30 made of silicon nitride or the like.

On the gate insulating film 30, a semiconductor layer 44 made of a semiconductor such as hydrogenated amorphous silicon is formed. The semiconductor layer 44 is positioned to overlap the gate electrode 24 and forms a channel portion of the thin film transistor.

On the semiconductor layer 44, ohmic contacts 55 and 56 made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of n-type impurities are formed. The ohmic contacts 55 and 56 are interposed between the semiconductor layer 44 and the upper source electrode 65 and the drain electrode 66 to reduce the contact resistance therebetween.

On the ohmic contacts 55 and 56, a data line 62, a source electrode 65 branched from the data line 62, and a drain electrode 66 are formed. The drain electrode 66 is separated from the source electrode 65 and positioned to overlap at least a portion of the lower gate electrode 24.

The source electrode 65 and the drain electrode 66 constitute a thin film transistor together with the gate electrode 24 and the semiconductor layer 44. The source electrode 65 is connected to a data line 62 which transmits a data signal to receive a data voltage. The gate electrode 24 receives a gate signal to turn the thin film transistor on or off. When the gate-on signal is applied to the gate electrode 24 and the thin film transistor is turned on, the data voltage provided to the source electrode 65 is transferred to the drain electrode 66 via the semiconductor layer 44.

On the data line 62, the source electrode 65 and the drain electrode 66, a protective film 70 made of an inorganic material such as silicon oxide or silicon nitride and an organic film pattern 82 made of an organic material are sequentially formed. .

Contact holes 86 are formed in the passivation layer 70 and the organic layer pattern 82 to expose the lower drain electrode 66 therethrough. In the intermediate region of the organic film 72 surrounding the contact hole 86, a stepped portion 72a is formed to prevent the inner inclination of the contact hole 86 from becoming excessively large. As a modification of the present embodiment, the stepped portion 72a may be omitted.

In addition, the organic layer pattern 82 is formed with a recess 89 that exposes the lower passivation layer 70 in the region where the sustain electrode 29 is formed.

A pixel electrode 92 made of a transparent conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed on the organic layer pattern 82. The pixel electrode 92 is electrically connected to the drain electrode 66 through the contact hole 86 to receive a data voltage. In addition, the pixel electrode 92 overlaps the storage electrode 29 to form a storage capacitor. In this case, since the pixel electrode 92 is formed directly on the passivation layer 70 along the sustain electrode recess 89 where the organic layer pattern 82 is removed, the organic capacitor pattern 82 is included in the sustain capacitor. It doesn't work.

Hereinafter, a method of manufacturing the thin film transistor array substrate as described above will be described. In the present embodiment, a cross-sectional view of the pixel structure in each process step is referred to for convenience of description, but the planar structure of each step may be easily inferred from the relationship of FIGS. 2 and 3.

4 to 10 are cross-sectional views illustrating the process steps of a method of manufacturing a thin film transistor array substrate in accordance with an embodiment of the present invention.

Referring to FIG. 4, first, aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), and titanium are used by sputtering on the entire surface of the insulating substrate 10 made of glass or the like. A conductive layer made of (Ti), tantalum (Ta) or an alloy thereof is deposited. Subsequently, a photolithography process is performed to form the gate line, the gate electrode 24, the storage electrode line, and the storage electrode 29.

4 and 5, for example, n + hydrogenated amorphous silicon doped with high concentrations of silicon nitride, hydrogenated amorphous silicon, and n-type impurities on the entire surface of the resultant of FIG. 4 may be chemical vapor deposition (Chemical Vapor Deposition); CVD) to form a gate insulating film 30, an intrinsic amorphous silicon layer 40, and a doped amorphous silicon layer 50.

Next, referring to FIGS. 5 and 6, aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), titanium ( A conductive metal made of Ti), tantalum (Ta) or an alloy thereof is deposited.

6 and 7, the photoresist film 100 is coated on the entire surface of the resultant product of FIG. 6.

At the same time, an imprint mold 200 including a first concave pattern 201 defining a data region and a second concave pattern 202 defining a channel region is prepared. Here, the depth d11 from the surface of the first concave pattern 201 is greater than the depth d12 from the surface of the second concave pattern 202, preferably from the surface of the second concave pattern 202. The depth d12 may be equal to or less than one half of the depth d11 from the surface of the first concave pattern 201. As the imprint mold 200, a hard mold or a soft mold may be used according to the hardness of the mold. Preferably, the soft mold may be in close contact with the surface of the imprint mold 200. Can be used.

Subsequently, the concave patterns 201 and 202 of the imprint mold 200 are disposed to face the photoresist film 100.

Next, referring to FIGS. 7 and 8, the imprint mold 200 is pressed toward the insulating substrate 10. Preferably, the surface of the imprint mold 200 is pressed to contact the data conductive layer 60. As a result, the photoresist film 100 is deformed according to the pattern of the imprint mold 200 as shown in FIG. 8.

Subsequently, the photoresist film 100 is heat-treated, or is cured by performing ultraviolet irradiation or the like.

8 and 9, the imprint mold 200 is removed from the photoresist film 100. As a result, as shown in FIG. 9, photoresist patterns 101 and 102 to which the pattern of the imprint mold 200 is transferred are formed. That is, since the photoresist pattern 101 of the data region is transferred from the first concave pattern 201 of the imprint mold 200, the photoresist pattern 101 has a thickness corresponding to the depth d11 of the first concave pattern 201, Since the photoresist pattern 102 of the channel region is transferred from the second concave pattern 202 of the imprint mold 200, the photoresist pattern 102 has a thickness corresponding to the depth d12 of the second concave pattern 202. Therefore, the photoresist pattern 101 of the data region is thicker than the thickness of the photoresist pattern 102 of the channel region.

If the photoresist film remains in the pixel electrode region after the above steps, the photoresist layer of the pixel electrode region is removed by performing etch back, so that the photoresist patterns 101 and 102 are positioned only in the data region and the channel region. do.

Meanwhile, the steps of FIGS. 7 to 9 forming the photoresist patterns 101 and 102 may be replaced by an exposure and development process using a slit mask. Since the slit mask process is known to those skilled in the art, a detailed description thereof will be omitted.

9 and 10, the lower data conductive layer 60 is etched using the photoresist patterns 101 and 102 as etching masks. As a result, the data conductive pattern 64 is formed.

Subsequently, the doped amorphous silicon layer 50 and the amorphous silicon layer 40 which are exposed using the photoresist patterns 101 and 102 as etching masks are sequentially etched. As a result, the ohmic contact layer 54 and the semiconductor layer 44 are formed. Meanwhile, the doped amorphous silicon layer 50 and the amorphous silicon layer 40 are etched, for example, by dry etching. In the process, the photoresist patterns 101 and 102 are also partially etched to reduce the overall thickness.

Next, the resultant is etched back to remove the photoresist pattern 102 of the channel region. When the photoresist pattern 102 of the channel region is removed in the dry etching process, the etch back process is omitted. As a result, as shown in FIG. 10, the data conductive layer pattern 64 of the channel region is exposed.

9 and 11, the exposed data conductive layer pattern 64 is etched using the photoresist pattern 101 of the data region as an etching mask to expose the lower ohmic contact layer 54. Let's do it. This completes the source electrode 65 and the drain electrode 66 which are separated from each other in the channel region.

Subsequently, the lower ohmic contact layer 54 is etched and separated to expose the semiconductor layer 44. This completes the ohmic contact layer 55 interposed between the semiconductor layer 44 and the source electrode 65 and the ohmic contact layer 56 interposed between the semiconductor layer 44 and the drain electrode 66.

Next, referring to FIGS. 11 and 12, the photoresist pattern 101 is removed. Subsequently, silicon nitride or the like is deposited on the entire surface of the resultant to form a protective film 70. Next, an organic material is coated on the protective film 70.

Next, referring to FIGS. 12 and 13, an imprint mold 300 including a first protrusion 310 defining a contact hole region and a second protrusion 320 defining a sustain electrode region is prepared. Here, the height h1 from the surface of the first protrusion 310 and the height h2 from the surface of the second protrusion 320 are the first when the imprint mold 300 is pressed against the organic layer 70. The distance from the protrusion 310 to the passivation layer 70 on the drain electrode 66 may be adjusted to be smaller than the distance from the second protrusion 320 to the passivation layer 70 on the sustain electrode 29. . As one example, the height h1 of the first protrusion 310 may be greater than the height h2 of the second protrusion 320.

In addition, the first protrusion 310 may further include a stepped pattern 311 as shown in FIG. 13. The height h3 from the surface of the step pattern 311 is a distance from the step pattern 311 to the protective film 70 on the drain electrode 66 when the imprint mold 300 is pressed against the organic film 70. The distance from the second protrusion 320 to the passivation layer 70 on the sustain electrode 29 may be adjusted within a range. As one example, the height h3 of the stepped portion may be smaller than the height h2 of the second protrusion.

In addition, in the case of the imprint mold 300, a hard mold or a soft mold may be used, and preferably a soft mold may be used.

Subsequently, the protrusions 310 and 320 of the imprint mold 300 are disposed to face the organic layer 80.

13 and 14, the imprint mold 300 is pressed toward the insulating substrate 10. Preferably, the second protrusion 320 of the imprint mold 300 is pressed close to the passivation layer 70 in the sustain electrode 29 region. In this case, the first protrusion 310 may contact the passivation layer 70 on the drain electrode 66, and the height of the first protrusion 310 may be shortened depending on the degree of pressure. As a result, the organic layer 70 is deformed according to the pattern of the imprint mold 300 as shown in FIG. 14.

Subsequently, the organic film 70 is irradiated with ultraviolet rays or subjected to heat treatment or the like for curing.

14 and 15, the imprint mold 300 is removed from the organic layer 70. As a result, the organic film pattern 82 to which the pattern of the imprint mold 300 is transferred is formed. That is, the contact recess 85 is formed to expose the protective film 70 on the drain electrode 66 by the transfer from the first protrusion 310 of the imprint mold 300. A stepped portion 72a is formed in an intermediate region of the organic layer 72 surrounding the contact hole 85 by the stepped pattern 311 of the first protrusion 310. Meanwhile, the storage electrode recess 88 is formed in the region of the storage electrode 29 to which the second protrusion 320 of the imprint mold 300 is transferred. At this time, the shortest distance from the contact recess 85 to the protective film 70 is shorter than the shortest distance from the sustain electrode recess 88 to the protective film 70.

Next, the organic layer pattern 82 is etched back to expose the passivation layer 70 under the contact recess 85. At this time, the passivation layer 70 under the sustain electrode recess 88 is not exposed.

15 and 16, the protective film 70 exposed by the contact recess 85 is etched. As a result, the contact hole 86 penetrating the organic layer pattern 82 and the passivation layer 70 is completed.

Next, referring to FIGS. 16 and 17, the resultant of FIG. 16 is etched back to expose the passivation layer 70 under the sustain electrode recess 88. Thereby, the recessed part 89 in which the protective film 70 on the sustain electrode 29 is exposed is completed. On the other hand, the height of the other region of the organic film pattern 82 is also lowered in the etch back process, in this case, it is preferable to adjust the step portion 82a to remain.

17 and 3, a transparent conductive oxide such as ITO or IZO is deposited and patterned on the resultant material of FIG. 17 to form the pixel electrode 92.

This completes the thin film transistor array substrate as shown in FIG. If necessary, an alignment layer or a light emitting layer may be stacked on the thin film transistor array substrate of FIG. 3.

As described above, in the present embodiment, the contact hole and the sustain electrode recesses are formed using an imprint mold, thereby replacing the exposure and development processes using a mask. Thus, the reliability of the process is increased, and the process efficiency can be improved.

Hereinafter, a method of manufacturing a thin film transistor array substrate according to another embodiment of the present invention will be described. Hereinafter, a description of the configuration having the same structure and function as the embodiment of the present invention described above will be omitted or simplified.

18 is a cross-sectional view of a thin film transistor array substrate manufactured by a method according to another embodiment of the present invention. In FIG. 18, a thin film transistor array substrate on which the organic layer is not stacked on the passivation layer 70 is illustrated. Therefore, it is natural that the concave portion provided in the organic film of the thin film transistor array substrate of FIG. 3 is not formed. The contact hole 76 is formed to penetrate the passivation layer 70, and the pixel electrode 92 is connected to the drain electrode 66 through the contact hole 76 in the same manner as the thin film transistor array substrate of FIG. 3. Do.

19 to 24 are cross-sectional views illustrating process steps of a method of manufacturing a thin film transistor array substrate according to another exemplary embodiment of the present invention.

Referring to FIG. 19, the steps up to forming the passivation layer 70 are the same as in the embodiment of the present invention. That is, the steps of FIGS. 4 to 11 may be applied in the same manner.

Subsequently, the photoresist film 110 is coated on the protective film 70.

Next, referring to FIGS. 19 and 20, an imprint mold 400 including a first recess 401 and a second recess 402 is prepared at the same time. Here, the protrusion 410 is positioned between the first recess 401 and the second recess 402 of the imprint mold 400. The end of the protrusion 410 constitutes the surface of the imprint mold 400, but because it is located between the recesses 401 and 402, it appears to be relatively protruding.

Also, the depth d21 from the surface of the first recess 401 may be greater than the depth d22 from the surface of the second recess 402. As the imprint mold 400, a hard mold or a soft mold may be used. Preferably, the soft mold may be used so that the surface may be completely adhered along the step of the lower structure to be pressed.

Subsequently, the photoresist such that the first recess 401 of the imprint mold 400 is positioned in the thin film transistor region, the second recess 402 is positioned in the pixel electrode region, and the protrusion is positioned in the drain electrode region. Aligned to membrane 110. Next, the imprint mold 400 is disposed to face the photoresist film 110.

Next, referring to FIGS. 20 and 21, the imprint mold 400 is pressed toward the insulating substrate 10. Preferably, the surface of the imprint mold 200 is pressed to contact the protective film 70. As a result, the photoresist film 110 is deformed according to the pattern of the imprint mold 200 as shown in FIG. 21.

Subsequently, the photoresist film 110 is hardened by heat treatment or ultraviolet irradiation or the like.

Next, referring to FIGS. 21 and 22, the imprint mold 400 is removed from the photoresist film 110. As a result, as shown in FIG. 22, photoresist patterns 111 and 112 to which the pattern of the imprint mold 400 is transferred are formed. That is, since the first region 111 of the photoresist pattern, which is the thin film transistor region, is transferred from the first recess 401 of the imprint mold 400, it corresponds to the depth d21 of the first recess 401. The second region 112 of the photoresist pattern, which is a pixel region, is transferred from the second recess 402 of the imprint mold 400, so that the second region 112 of the photoresist pattern is a depth d22 of the second recess 402. It will have a corresponding thickness. In addition, the photoresist pattern may include a third region (not shown) transferred from the protrusion 410 of the imprint mold 400. Here, the thickness of the second region 112 is smaller than the thickness of the first region 111 and larger than the thickness of the third region.

When the third region is included as described above, the photoresist pattern is etched back to remove the third region, and the lower passivation layer 70 is exposed.

Next, referring to FIGS. 22 and 23, the protective layer is etched using the photoresist patterns 111 and 112 as an etching mask to expose the lower drain electrode 66. As a result, the contact hole 76 is completed.

Next, the photoresist patterns 111 and 112 are etched back to remove the second region 112. At this time, the first region 112 also has a small thickness.

Next, referring to FIGS. 23 and 24, a transparent conductive oxide such as ITO, IZO, or the like is deposited on the resultant of FIG. 23 using sputtering or the like.

Next, referring to FIGS. 24 and 18, the first region 111 of the photoresist pattern and the conductive oxide layer 90 deposited thereon are removed. The removal step is carried out by a lift off method. That is, when the photoresist stripper including, for example, an amine, glycol, or the like is brought into contact with the photoresist pattern 111 by a spray method or a dip method, the photoresist stripper dissolves the photoresist pattern 111 to form a protective film 70. The photoresist pattern 111 is peeled from the film. At this time, the conductive oxide layer 90 deposited on the photoresist pattern 111 is also removed. In this step, the pixel electrode 92 is completed.

This completes the thin film transistor array substrate as shown in FIG.

As described above, in the present embodiment, the contact hole is formed using an imprint mold, thereby replacing the exposure and development processes using a mask. Therefore, the reliability of the process is increased and the process efficiency can be improved. In addition, in this embodiment, unlike the embodiment of the present invention, since the pixel electrode is formed by the lift-off method, the number of photolithography processes is reduced. Therefore, the process speed is increased, and the process efficiency can be further improved.

Hereinafter, a method of manufacturing a thin film transistor array substrate according to still another embodiment of the present invention will be described. Hereinafter, a description of the configuration having the same structure and function as the embodiment of the present invention described above will be omitted or simplified.

25 is a cross-sectional view of a thin film transistor array substrate manufactured by a method according to another embodiment of the present invention.

The insulating substrate 10 of the present embodiment may be made of transparent glass or plastic, which is a material having heat resistance and light transmittance, and a flexible plastic is preferable so that the insulating substrate 10 may be applied to a flexible image display device or the like.

The pixel electrode 92 of the present exemplary embodiment may be formed to directly contact the insulating substrate 10 in the pixel region.

26 to 31 are cross-sectional views of steps in a method of manufacturing a thin film transistor array substrate according to still another embodiment of the present invention.

The manufacturing method of this embodiment is the same as another embodiment of the present invention until the step of forming the photoresist film 110. That is, the steps of FIGS. 4 to 11 and 19 may be applied in the same manner.

Referring to FIG. 26, an imprint mold 500 including a first recessed portion 501 is prepared. The first concave portion 501 is deposited so that the transparent conductive oxide (see 90 in FIG. 31) deposited on the photoresist pattern (see 121 in FIG. 28) is not connected and deposited to have an incision, and in a later step The width w _{1 of the} lower sidewall is narrower than the width w _{3 of the} upper sidewall so that the photoresist pattern can be easily lifted off. That is, the first concave portion 501 includes a first reverse slope portion 501_1 such that a reverse taper is formed on the photoresist pattern transferred and formed by the imprint mold 500. The first reverse inclined portion 501_1 may have an inverted triangular shape in which the width thereof gradually increases from the lower side of the sidewall of the first concave portion 501 toward the upper sidewall. In addition, the first reverse slope 501_1 has the same width w ₁ of the lower sidewall of the first concave portion 501 and the width w _{2 of the} sidewall central portion, and increases in width from the sidewall center portion toward the upper sidewall. It may have a shape. That is, the width from the bottom sidewall to the center of the sidewall may be formed to be the same, and the width from the sidewall center to the top of the sidewall may be formed to have a reverse slope.

The imprint mold 500 may be made of a soft polymer resin so as to be easily separated after transferring the photoresist pattern. That is, the photoresist pattern is preferably a soft mold such that the imprint mold 500 is separated without causing collapse of the photoresist pattern even after the transfer of the photoresist pattern.

The imprint mold 500 may further include a second recess 502 and a protrusion 510 formed between the first recess 501 and the second recess 502. In this case, the depth d ₃₁ from the surface of the first recess 501 may be greater than the depth d ₃₂ from the surface of the second recess 502. The second recess 502 may also include a second reverse slope 502_1 like the first recess 501. In this case, the second reverse slope 502_1 may also have a wider width than the lower sidewall. In addition, the imprint mold 500 may further include a third recess (not shown), which is aligned on the sustain electrode (not shown) in a later step.

Subsequently, the first recess 501 of the imprint mold 500 is aligned with the photoresist film 110 such that the first recess 501 is located in the thin film transistor region. When the imprint mold 500 includes the second recess 502 and the protrusion 510, the second recess 502 aligns the imprint mold 500 so that the second recess 502 is in the pixel region and the protrusion is in the drain region. do. Next, the imprint mold 500 is disposed to face the photoresist film 110.

Next, referring to FIGS. 26 and 27, the imprint mold 500 is pressed toward the insulating substrate 10. Preferably, the surface of the imprint mold 500 is pressed to contact the protective film 70. As a result, the photoresist film 110 is deformed according to the pattern of the imprint mold 500 as shown in FIG. 27. In other words, the photoresist film 110 is formed to have a reverse tapered taper in a subsequent process. Subsequently, the photoresist film 110 is cured by heat treatment or ultraviolet irradiation or the like.

Next, referring to FIGS. 27 and 28, the imprint mold 500 is removed from the photoresist film 110. As a result, as shown in FIG. 28, photoresist patterns 121 and 122 to which the pattern of the imprint mold 500 is transferred are formed. That is, the first region 121 of the photoresist patterns 121 and 122 is formed to have the first reverse slope taper 121_1. That is, the width of the lower portion of the side wall of the first region 121 is narrower than the width of the upper portion, the width from one end to the other end of the first region 121 may gradually increase from the lower side to the upper side. . In addition, the width may be the same from the lower side to the middle of the sidewall of the first region 121, and the width may gradually increase from the middle of the sidewall to the upper side. Accordingly, when the transparent conductive oxide (see 90 in FIG. 31) is deposited on the photoresist patterns 121 and 122 in the subsequent process, the transparent conductive oxide is not deposited on the first reverse slope taper 121_1, so that the lift-off process is performed. It can be done easily. The photoresist patterns 121 and 122 may further include a second region 122 and a protrusion 510, and the second region 122 may also include a second reverse slope taper 122_1 to increase efficiency of the lift-off process. ) In addition, since the photoresist patterns 121 and 122 are arranged at the correct positions as compared with the case in which the photoresist patterns 121 and 12 are formed by using a mask, the possibility of misalignment is reduced. Since the photoresist patterns 121 and 122 are formed using the imprint mold as in the present embodiment, misalignment can be reduced, and therefore, it is particularly useful for a flexible image display apparatus using a plastic substrate as the insulating substrate 10.

In addition, since the first region 121 of the photoresist patterns 121 and 122, which are thin film transistor regions, is transferred from the first recess 501 of the imprint mold 500, the depth of the first recess 501 is increased. The second region 122 of the photoresist patterns 121 and 122, which is a pixel region and has a thickness corresponding to (d ₃₁ ), is transferred from the second recess 502 of the imprint mold 500. It has a thickness corresponding to the depth d ₃₂ of the recess 502. In addition, the photoresist patterns 121 and 122 may include a third region (not shown) transferred from the protrusion 510 of the imprint mold 500. Here, the thickness of the second region 122 is smaller than the thickness of the first region 121 and larger than the thickness of the third region. When the third region is included as described above, the photoresist pattern is etched back to remove the third region, and the lower passivation layer 70 is exposed. In order to protect the passivation layer 70 on the storage electrode, the photoresist patterns 121 and 122 may further include a fourth region (not shown) formed on the storage electrode.

28 and 29, the protective layer 70 is etched using the photoresist patterns 121 and 122 as an etching mask to form the protective layer pattern 72 and expose the lower drain electrode 66. Let's do it. In this case, since the photoresist patterns 121 and 122 include the first reverse slope taper portion 121_1 and / or the second reverse slope taper portion 122_1, the passivation layer pattern 72 may not be over-etched. . In other words, when the first and second reverse slope taper portions 121_1 and 121_2 are not formed in the photoresist patterns 121 and 122, the conductive oxides (see 90 in FIG. 31) are deposited so as not to include an incision, thereby forming a photo. In order to prevent contact between the resist patterns 121 and 122 with the stripper, it is necessary to overetch the passivation layer 70 to form an overetched passivation layer pattern. As the photoresist patterns 121 and 122 are formed, there is no need to form an overetched passivation layer, and multi-step etching for overetching is not required, thereby reducing process time and cost.

Subsequently, the gate insulating layer 30 exposed by the protective layer pattern 72 may be etched to form the gate insulating layer pattern 32, and the insulating substrate 10 may be exposed. In this case, the passivation layer 70 and the gate insulating layer 30 on the sustain electrode are not etched by the fourth regions of the photoresist patterns 121 and 122. When the photoresist patterns 121 and 122 do not include the second region 122, all of the passivation layer 70 and the gate insulating layer 30 except for the lower portion of the first region 121 and the upper portion of the storage electrode are etched and removed. Of course.

Next, referring to FIGS. 29 and 30, the photoresist patterns 121 and 122 may be etched back to remove the second region 122 and the fourth region. At this time, the thickness of the first region 121 also becomes small, and only a part of the first reverse slope taper 121_1 remains. If the second region 122 is not included, the etch back process of this step is omitted.

30 and 31, a transparent conductive oxide 90 such as, for example, ITO, IZO, ZAO, or the like is deposited on the resultant of FIG. 30 using sputtering or the like.

Since the imprint mold (see 500 in FIG. 26) of the present embodiment includes the first reverse slope portion (501_1 in FIG. 26) in the first recessed portion (501 in FIG. 26), the transparent conductive oxide 90 is formed in the first region ( Deposited to have an incision between 121 and second region 122. Therefore, in a subsequent lift-off process, the stripper may penetrate through the cutout formed between the conductive oxide 90 layers to easily contact the first regions 121 of the photoresist patterns 121 and 122.

31 and 25, the first region 121 of the photoresist pattern and the conductive oxide layer 90 deposited thereon are removed. The removal step is carried out by a lift off method. That is, when the photoresist stripper including, for example, an amine, glycol, or the like is brought into contact with the photoresist pattern 121 by a spray method or a dip method, the photoresist stripper dissolves the photoresist pattern 121 to protect the protective film 70. The photoresist pattern 121 is peeled from the film. At this time, the conductive oxide 90 deposited on the photoresist pattern 121 is also removed. In this step, the pixel electrode 92 is completed.

Accordingly, the thin film transistor array substrate is completed as shown in FIG. 25. Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments, but in various forms. Those skilled in the art to which the present invention pertains may understand that the present invention may be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, according to the method of manufacturing the thin film transistor array substrate according to the embodiments of the present invention, since the contact holes and / or the sustain electrode recesses are formed using the imprint mold, the reliability of the process is increased and the process efficiency is improved. Can be.

Claims (17)

Forming a protective film on an insulating substrate on which a thin film transistor including a gate electrode, a source electrode, and a drain electrode and a sustain electrode are formed; Applying an organic film on the entire surface of the protective film; Facing the organic layer an imprint mold defining a contact hole region, a first protrusion protruding from a surface by a first height, and a second protrusion defining a sustain electrode region, and protruding from a surface by a second height; Pressing to transfer the pattern of the imprint mold; And Separating the imprint mold from the organic layer, the contact recess positioned on the drain electrode and transferred from the first protrusion, and the sustain electrode recess positioned on the sustain electrode and transferred from the second protrusion, And forming an organic layer pattern having a minimum distance between the contact recess and the passivation layer smaller than a minimum distance between the sustain electrode recess and the passivation layer. According to claim 1, And hardening the organic pattern after the pressing of the imprint mold. According to claim 1, After forming the organic layer pattern, etching the organic layer pattern to expose the passivation layer under the contact recess. The method of claim 3, wherein After exposing the protective film under the contact recess, Etching the exposed passivation layer to expose the lower drain electrode; And And etching back the organic layer pattern to expose the protective layer under the sustain electrode recess. According to claim 1, And a first height of the first protrusion is greater than a second height of the second protrusion. The method of claim 5, And the first protrusion further comprises a stepped portion, wherein a height of the stepped portion from the surface of the imprint mold is smaller than the second height. Forming a protective film on an insulating substrate on which a thin film transistor including a gate electrode, a source electrode, and a drain electrode is formed; Applying a photoresist film on the protective film; A first imprint mold including a first recess of a first depth, a second recess of a second depth smaller than the first depth, and a protrusion protruding relatively between the first and second recesses Aligning the photoresist film such that the concave portion is located in the thin film transistor region, the second concave portion is located in the pixel electrode region, and the protrusion is located in the drain electrode region; Transferring the pattern of the imprint mold by pressing the imprint mold against the photoresist film and pressing the imprint mold; And Separating the imprint mold from the photoresist film, wherein the imprint mold is positioned in a thin film transistor region, and is located in a first region transferred from the first recess, a pixel region, and a second region transferred from the second recess and the drain electrode. And forming a photoresist pattern at a location, the third region being transferred from the protrusion, wherein the thickness of the second region is less than the thickness of the first region and is greater than the thickness of the third region. Method of manufacturing a thin film transistor array substrate. The method of claim 7, wherein And hardening the organic layer after pressing the imprint mold. The method of claim 7, wherein After the forming of the photoresist pattern, etching the photoresist pattern to remove the third region and to expose the drain electrode. The method of claim 9, After the step of forming the photoresist pattern, Etching the passivation layer to expose the drain electrode; Etching back the photoresist pattern to remove the second region of the photoresist pattern; Depositing a transparent conductive oxide on the entire surface of the resultant product; And Stripping the photoresist pattern to remove the first region of the photoresist pattern and the conductive oxide deposited thereon. Forming a protective film on an insulating substrate on which a thin film transistor including a gate electrode, a source electrode, and a drain electrode is formed; Applying a photoresist film on the protective film; Aligning an imprint mold made of a soft polymer resin to the photoresist film such that the first recess is located in the thin film transistor region, the imprint mold comprising a first recess having a width smaller than the width of the upper sidewall; Transferring the pattern of the imprint mold by pressing the imprint mold against the photoresist film and pressing the imprint mold; And Separating the imprint mold from the photoresist film to form a photoresist pattern positioned in a thin film transistor region and including a first region transferred from the first concave portion. The method of claim 11, wherein The insulating substrate is a method of manufacturing a thin film transistor array substrate made of plastic. The method of claim 11, wherein And the first concave portion has the same width from the lower side of the sidewall to the central sidewall, and the width from the sidewall central portion to the upper sidewall gradually increases. The method of claim 11, wherein And hardening the photoresist film after the pressing of the imprint mold. The method of claim 11, wherein After forming the photoresist pattern, Etching the passivation layer to expose the drain electrode and the insulating substrate in the pixel region; Depositing a transparent conductive oxide on the entire surface of the resultant product; And Removing the photoresist pattern to remove the first region of the photoresist pattern and the conductive oxide deposited thereon. The method of claim 11, wherein The imprint mold includes a second recess having a depth smaller than a depth of the first recess and a protrusion protruding relatively between the first and second recesses, The photoresist pattern may further include a second region located in the pixel region and transferred from the second concave portion and a third region located on the drain electrode and transferred from the protrusion, wherein the thickness of the second region Is smaller than the thickness of the first region and larger than the thickness of the third region. The method of claim 16, After the step of forming the photoresist pattern, Etching the passivation layer to expose the drain electrode and the insulating substrate in the pixel region; Etching back the photoresist pattern to remove the second region of the photoresist pattern; Depositing a transparent conductive oxide on the entire surface of the resultant product; And Removing the photoresist pattern to remove the first region of the photoresist pattern and the conductive oxide deposited thereon.

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