KR20070081255A - Shift register - Google Patents

Abstract

A shift register is provided that can improve the driving ability of the gate driving circuit to improve the display quality of the liquid crystal panel. The shift register may include a first gate electrode pattern disposed in a non-display area on an insulating substrate, a semiconductor layer disposed on the first gate electrode pattern, and a source electrode line and a drain electrode line disposed in a cross-finger shape on the semiconductor layer. And a dual gate transistor disposed on the drain electrode line and the source electrode line and including a second gate electrode pattern electrically connected to the first gate electrode pattern.

Description

Shift Register

1 is a view for explaining a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a diagram for explaining a general shift register.

FIG. 3 is an equivalent circuit diagram of the shift register shown in FIG. 2.

4 is a diagram illustrating a dual gate transistor according to an exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view taken along line IIa-IIa 'of FIG. 4.

FIG. 6 is a cross-sectional view taken along line IIb-IIb ′ of FIG. 4.

FIG. 7 is a cross-sectional view taken along line IIc-IIc ′ of FIG. 4.

(Explanation of symbols for the main parts of the drawing)

100: liquid crystal panel 200L, 200R: gate driver

300: data driver 400: gray voltage generator

500: timing controller 600: voltage generator

105: insulating substrate 110: first gate electrode pattern

112: gate insulating film 113: contact hole

116: semiconductor layer 130: drain electrode line

140: source electrode line 150: protective film

160: second gate electrode pattern 210: shift register

211: SR latch 212: AND gate

The present invention relates to a shift register, and more particularly, to a shift register capable of improving the display quality of a liquid crystal panel by improving the driving capability of the gate driving circuit.

In general, a liquid crystal display includes a liquid crystal panel having a plurality of gate lines and a plurality of data lines, a gate driving circuit that outputs a gate driving signal to the plurality of gate lines, and an image signal to the plurality of data lines. It consists of a data drive circuit to output.

The gate driving circuit and the data driving circuit have an IC form and are mounted on the liquid crystal panel. However, in recent years, in order to increase productivity while reducing the overall size of the liquid crystal display, a structure in which a gate driver circuit is integrated and formed in a predetermined region of the liquid crystal panel rather than manufactured in an IC form has been developed.

The gate driving circuit formed in a predetermined region of the liquid crystal panel includes one shift register having a plurality of stages cascaded with each other. Each stage also includes a plurality of thin film transistors (hereinafter referred to as TFTs) and capacitors that generate gate driving signals for driving the gate lines. At this time, in the case of forming the shift register using amorphous silicon, the ratio of W / L of the transistor is required to be 1000 or more, thereby increasing the area for forming the transistor. In addition, the capacitance of the liquid crystal capacitor is changed according to the driving ability of the transistor, which affects the display quality of the liquid crystal panel.

It is an object of the present invention to provide a shift register capable of improving the display quality of a liquid crystal panel by improving the driving ability of the gate driving circuit.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to one or more exemplary embodiments, a shift register includes a first gate electrode pattern disposed on a non-display area on an insulating substrate, a semiconductor layer disposed on the first gate electrode pattern, and the semiconductor layer. A dual gate including a source electrode line and a drain electrode line disposed in a cross-finger shape and a second gate electrode pattern disposed on the drain electrode line and the source electrode line and electrically connected to the first gate electrode pattern. It includes a transistor.

Specific details of other embodiments are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various forms, and the present embodiments are merely provided to make the disclosure of the present invention complete and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, the invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention;

1 is a view for explaining a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, in the liquid crystal display according to the exemplary embodiment, a gray voltage is connected to the liquid crystal panel 100 and the gate drivers 200L and 200R, the data driver 300, and the data driver 300 connected thereto. The unit 400 includes a timing controller 500 and a voltage generator 600 for controlling them.

The liquid crystal panel 100 is connected to a plurality of display signal lines G1-Gn and D1-Dm as viewed in an equivalent circuit, and includes a plurality of unit pixels arranged in a matrix form.

Here, the display signal lines G1-Gn and D1-Dm include a plurality of gate lines G1-Gn transferring gate signals and data lines D1-Dm transferring data signals. The gate lines G1-Gn extend in the row direction and are substantially parallel to each other, and the data lines D1-Dm extend in the column direction and are substantially parallel to each other.

Each unit pixel includes a switching element Q connected to the display signal lines G1-Gn, D1-Dm, a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. The sustain capacitor Cst may be omitted as necessary.

The switching element Q is provided on the first display panel (not shown), and the control terminal and the input terminal thereof are connected to the gate lines G1-Gn and the data lines D1-Dm, respectively. The output terminal is connected to the liquid crystal capacitor Clc and the sustain capacitor Cst.

The liquid crystal capacitor Clc has a pixel electrode of the first display panel and a common electrode of a second display panel (not shown) as two terminals, and the liquid crystal layer between the two electrodes functions as a dielectric. The pixel electrode is connected to the switching element Q, and the common electrode is formed on the front surface of the second display panel and receives the common voltage Vcom. In addition, a common electrode may be provided in the first display panel, and both electrodes may be made in a linear or bar shape.

The storage capacitor Cst is formed by overlapping a separate signal line (not shown) and a pixel electrode included in the first display panel, and a predetermined voltage such as a common voltage Vcom is applied to the separate signal line (independent wiring method). However, the sustain capacitor Cst may be formed such that the pixel electrode overlaps the front-end gate line directly above the insulator (shear gate method).

On the other hand, in order to implement color display, each unit pixel should be able to display color, which is possible by providing a red, green, or blue color filter in a region corresponding to the pixel electrode. In addition, although the color filter is formed in a predetermined region of the second display panel, the color filter may be formed above or below the pixel electrode of the first display panel.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the first display panel and the second display panel of the liquid crystal panel 100.

The gray voltage generator 400 may generate two sets of gray voltages related to transmittance of a unit pixel. That is, one of the two sets is the positive voltage, and the other is the negative voltage. The positive voltage and the negative voltage mean voltages whose polarities of the data voltages are opposite to the common voltage Vcom, and are alternately provided to the liquid crystal panel during inversion driving.

The gate drivers 200L and 200R are disposed on the left and right sides of the liquid crystal panel 100, are connected to the respective gate lines G1 -Gn, and the combination of the gate on voltage Von and the gate off voltage Voff. The gate clock signal consisting of the same is applied to the gate lines G1-Gn. In addition, the gate drivers 200R and 200L are formed of a transistor having a dual gate. Detailed description thereof will be described with reference to FIG. 4.

The data driver 300 is connected to the data lines D1-Dm of the liquid crystal panel 100, generates a plurality of gray voltages based on voltages provided from the gray voltage generator 400, and generates the generated gray voltages. It is selected and applied to a unit pixel as a data signal, and is usually composed of a plurality of integrated circuits.

The timing controller 500 generates control signals for controlling operations of the gate drivers 200L and 200R and the data driver 300, and transmits corresponding control signals to the gate drivers 200L and 200R and the data driver 300. To provide.

The voltage generator 600 generates a plurality of driving voltages. For example, the driving voltage generation circuit (not shown) provides the gate on voltage Von and the gate off voltage Voff to the gate drivers 200L and 200R, and the common voltage Vcom to the liquid crystal panel 100. Output

FIG. 2 is a diagram for explaining a general shift register, and FIG. 3 is an equivalent circuit diagram of the shift register shown in FIG. Here, the gate driver 200L of FIG. 1 will be described for convenience of description.

Referring to FIG. 2, the gate driver 200L includes a plurality of shift registers 210 arranged in a line. Here, the shift register 210 may be formed together when the switching element of the pixel is formed and integrated on the same substrate. In other words, the liquid crystal panel 100 may be formed together, instead of being mounted on a substrate by using a separate gate driving chip.

The shift register 210 may be equivalently represented as the SR latch 211 and the AND gate 212 as shown in FIG. 2.

The gate driver 200L starts outputting the gate clock signal CKV according to the vertical synchronization start signal STV from the timing controller 500, and sequentially turns on the gate-on voltages to the gate lines G1 -Gn arranged in a line. Von) is applied.

The first shift register 210 starts outputting the gate-on voltage Von in synchronization with the vertical synchronizing start signal STV and the gate clock signal CKV. From the second shift register, the output voltage and gate of the previous shift register are started. The output of the gate-on voltage Von is started in synchronization with the clock signal CKVB. The operation of the shift register 210 will be described in more detail.

The SR latch 211 has a set input terminal S to which the front gate output Gout (N-1), that is, the output of the front shift register is input, and the rear gate output Gout (N + 1), i.e., the rear shift register. Has a reset input terminal R to which an output of the input signal is input. The AND gate 212 generates and outputs a gate signal using the output of the SR latch 211 and the gate clock signal CKV as two inputs.

The front gate output Gout (N-1) input to the set terminal S and the rear gate output Gout (N + 1) input to the reset terminal R are both low level ('0'). In the initial state, the output of the SR latch 211 is also low level. If the front gate output Gout (N-1) changes to the high level '1' while the rear gate output Gout (N + 1) is kept at the low level, the output Q of the SR latch 211 is Change to high level. The output of the SR latch 211 remains unchanged even though the front gate output Gout (N-1) is turned back to the low level while the rear gate output Gout (N + 1) is kept at the low level. If the rear gate output Gout (N + 1) changes to a high level while the front gate output Gout (N-1) remains at a low level, the output Q of the SR latch 211 is at a low level from a high level. Changes to The output Q of the SR latch 211 is the point at which the rear gate output Gout (N + 1) goes from the low level to the high level from the time when the front gate output Gout (N-1) changes from the low level to the high level. The high level is maintained until the change point, and the low level is otherwise.

The AND gate 212 generates a gate output Gout (N) that is at a high level only when both the output Q and the gate clock signal CKV of the SR latch 211 are at a high level. In detail, the gate output Gout (N) becomes a high level when the gate clock signal CKV changes from a low level to a high level while the output Q of the SR latch 211 is at a high level. When the signal CKV becomes low level or the output Q of the SR latch 211 becomes low level, the signal CKV changes to low level.

In this manner, each shift register 410 is based on the front gate output Gout (N-1) and the rear gate output Gout (N + 1) and in synchronism with the gate clock signal CKV. (N)].

FIG. 4 is a diagram illustrating a dual gate transistor according to an exemplary embodiment of the present invention. In particular, FIG. 4 illustrates a dual gate transistor of a shift register used in a gate driving circuit of a liquid crystal display.

Referring to FIG. 4, a dual gate transistor according to an exemplary embodiment of the present invention is formed in a non-display area on the transparent insulating substrate 105, and includes a first gate electrode pattern 110 defining a predetermined area and a first gate. A drain electrode line 130 extending from an outer side of the electrode pattern 110 and formed in a plurality of finger shapes on the gate electrode pattern 100, and extending from an outer side of the drain electrode line 130 to form a first gate electrode pattern ( The source electrode line 140 is disposed on the 110 and spaced apart from the drain electrode line 130 and formed in a plurality of finger shapes. For convenience of description, only the metal electrode part is shown, and descriptions of the gate insulating film, the semiconductor layer, etc. formed on the first gate electrode pattern 110 are omitted.

In this case, the first gate electrode pattern 110 formed on the transparent insulating substrate 105 has a box shape, and the drain electrode line 130 and the source electrode line 140 formed on the first gate electrode pattern 110. ) Are staggered with each other. In view of the observer, the source electrode line 140 is formed to surround the drain electrode line 130.

In detail, the drain electrode line 130 includes a body-drain line 132 and finger-drain lines 134a and 34b branched from the body-drain line 132. In this case, the body-drain line 132 and the finger-drain lines 134a and 34b are formed in the region where the first gate electrode pattern 110 is formed.

Meanwhile, the source electrode line 140 includes body-source lines 142a and 142b and finger-source lines 144a and 144b branched from the body-source lines 142a and 142b. In this case, the body-source lines 142a and 142b are formed in a region where the first gate electrode pattern 110 is not formed, and a portion of the finger-source lines 144a and 144b is formed by the first gate electrode pattern 110. It is formed in the formed area.

Further, the finger-drain lines 134a and 134b are formed in an I shape on the first gate electrode pattern 110, and the finger-source lines 144a and 144b are formed on the first gate electrode pattern 110. It is formed in a shape of a child and is formed in a shape surrounding the finger-drain lines 134a and 134b.

The second gate is electrically connected to the first gate electrode pattern 110 through contact holes on the body-drain line 132, the finger-drain lines 134a and 134, and the finger-source lines 144a and 144b. The electrode pattern 160 is formed. In this case, the second gate electrode pattern 160 is formed to cover the first gate electrode pattern 110.

5 to 7 are cross-sectional views of the dual gate transistor of FIG. 4, FIG. 5 is a cross-sectional view taken along line IIa-IIa ′ of FIG. 4, and FIG. 6 is a cross-sectional view taken along line IIb-IIb ′ of FIG. 4. FIG. 7 is a cross-sectional view taken along line IIc-IIc ′ of FIG. 4.

4 to 7, the first gate electrode pattern 110 is formed in the non-display area on the transparent insulating substrate 105. In this case, the first gate electrode pattern 110 may be formed of aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper-based metals such as copper (Cu) and copper alloys, It may be made of molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys, chromium (Cr), titanium (Ti), tantalum (Ta). In addition, the first gate electrode pattern 110 may have a multilayer structure including two conductive layers (not shown) having different physical properties. One of the conductive layers may be formed of a low resistivity metal such as an aluminum-based metal, a silver-based metal, a copper-based metal, etc. to reduce the signal delay or voltage drop of the first gate electrode pattern 110. In contrast, the other conductive layer is made of a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, titanium, tantalum and the like. A good example of such a combination is a chromium bottom film and an aluminum top film, and an aluminum bottom film and a molybdenum top film. However, the present invention is not limited thereto, and the first gate electrode pattern 110 may be made of various metals and conductors.

A gate insulating layer 112 such as silicon oxide or silicon nitride is formed on the substrate 105 including the first gate electrode pattern 110. In this case, the gate insulating layer 112 has a contact hole 113 exposing a portion of the first gate electrode pattern 110.

On the gate insulating layer 112, a semiconductor layer 116 made of hydrogenated amorphous silicon, polycrystalline silicon, or the like is formed. The semiconductor layer 116 may have various shapes such as an island shape and a linear shape, and may be formed in an island shape on the first gate electrode pattern 110 as in the present invention.

Although not shown in the drawings, an island-type ohmic contact layer and a linear ohmic contact layer made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration on the semiconductor layer 40. Is formed. Here, the ohmic contact layer is an island-type ohmic contact layer, and is located under the drain line 130 and the source line 140.

The drain electrode line 130 and the source line 140 are formed on the semiconductor layer 116. In detail, a drain electrode line 130 including a body-drain line 132 and finger-drain lines 134a and 34b branched from the body-drain line 132 is formed on the semiconductor layer 116. At this time, the body-drain line 132 and the finger-drain lines 134a and 34b are formed in the region where the first gate electrode pattern 110 is formed. Further, on the semiconductor layer 116, a source electrode line 140 including body-source lines 142a and 142b and finger-source lines 144a and 144b branched from the body-source lines 142a and 142b is formed. In this case, the body-source lines 142a and 142b are formed in a region where the first gate electrode pattern 110 is not formed, and a part of the finger-source lines 144a and 144b is formed in the first gate electrode. It is formed in the region where the pattern 110 is formed.

At this time, the drain electrode line 130 and the source electrode line 140 is preferably made of a refractory metal such as chromium, molybdenum-based metal, tantalum and titanium, and a lower layer (not shown) such as refractory metal and a low layer disposed thereon. It may have a multilayer structure consisting of a resistive material upper layer (not shown). Examples of the multilayer film structure include a triple film of molybdenum film, aluminum film, and molybdenum film in addition to the above-described double film of chromium lower film and aluminum upper film or aluminum lower film and molybdenum upper film.

The passivation layer 150 is formed on the drain electrode line 130 and the source electrode line 140. Here, the protective film 150 is an inorganic material made of silicon nitride or silicon oxide, an organic material having excellent planarization characteristics and photosensitivity or a-Si: C formed by plasma enhanced chemical vapor deposition (PECVD). It consists of low dielectric constant insulating materials, such as: O and a-Si: O: F. In addition, the passivation layer 150 may have a double layer structure of a lower inorganic layer and an upper organic layer to protect the exposed portion of the semiconductor layer 116 while maintaining excellent characteristics of the organic layer.

The second gate electrode pattern 160, which is physically and electrically connected to the first gate electrode pattern 110 through the contact hole 113, is formed on the passivation layer 150. In this case, the second gate electrode pattern 160 may be formed of the same material as the pixel electrode. For example, it may be formed of a transparent conductive oxide (TCO) such as ITO or IZO or a reflective conductor such as aluminum.

As described above, as shown in FIG. 5, the second gate electrode pattern 160 is formed on the drain line 130 and the source line 140 to form a dual gate transistor, thereby forming the drain line 130 in the source line 140. Electrons move to form a first channel region A at an interface between the gate insulating layer 112 and the semiconductor layer 116, and a second channel region at an interface between the semiconductor layer 116 and the passivation layer 150. (B) is formed. As a result, twice the amount of current can be obtained in the same area without increasing the W / L of the transistor. Therefore, the integration degree and driving capability of the gate driving circuit can be increased. In addition, since the second gate electrode pattern may be formed by simply changing a mask when forming the pixel electrode in the existing thin film transistor process, a separate process may not be added.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive.

According to the shift register according to the present invention as described above, it is possible to obtain a double gate transistor to obtain a double amount of current in the same area without increasing the W / L of the transistor. Therefore, the integration degree and driving capability of the gate driving circuit can be increased.

Claims (7)

A first gate electrode pattern disposed in the non-display area on the insulating substrate; A semiconductor layer disposed on the first gate electrode pattern; Source and drain electrode lines disposed on the semiconductor layer in a cross-finger shape; And And a dual gate transistor disposed on the drain electrode line and the source electrode line, the dual gate transistor including a second gate electrode pattern electrically connected to the first gate electrode pattern. The method of claim 1, The source electrode line may be formed to surround the drain electrode line, and may be branched from the first body line and the first body line extending from the outside of the first gate electrode pattern on the semiconductor layer. A shift register comprising a first finger line. The method of claim 1, The drain electrode line includes a second body line extending from the outside of the first gate electrode pattern on the semiconductor layer and a second finger line branched from the second body line and formed on the first gate electrode pattern. The method of claim 1, The first finger line may have a U-shape on the first gate electrode pattern. The method of claim 1, The second finger line has an I-shape formed on the first gate electrode pattern. The method of claim 1, The second gate electrode pattern is formed to cover the first gate electrode pattern. The method of claim 1, And the second gate electrode pattern is formed of a transparent conductive oxide film.

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