KR20070079994A - Display substrate and display panel having same - Google Patents

Abstract

Disclosed are a display substrate for eliminating vertical line defects and a display panel having the same. The display substrate on which the plurality of gate lines and the plurality of source lines intersecting the gate lines are formed includes a first pixel portion and a second pixel portion. The first pixel portion is electrically connected to a first switching element connected to an arbitrary source line and an n-1 (n is a natural number) gate line, and includes a first pixel electrode including a first transparent electrode and a first reflective electrode. do. The second pixel portion is electrically connected to a second switching element connected to the source line and the n-th gate line, and a second pixel electrode including a second transparent electrode and a second reflective electrode larger than the first reflective electrode is formed. Accordingly, vertical line defects can be improved by eliminating luminance variations between the pixel portions by adjusting the transmission region between adjacent pixel portions sharing the source wiring.

Description

DISPLAY SUBSTRATE AND DISPLAY PANEL HAVING THE SAME}

1 is a plan view of a display substrate according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the display panel taken along the line II ′ of FIG. 1.

3A to 3C are diagrams for describing luminance characteristics of the display panel of the comparative example.

4A to 4C are diagrams for describing luminance characteristics of the display panel of the present invention.

<Description of the symbols for the main parts of the drawings>

TFT1, TFT2: first and second switching elements

CST1, CST2: first and second storage capacitors

P1, P2: first and second pixel portions PE1, PE2: first and second pixel electrodes

117 and 127: first and second reflective electrodes 118 and 128: first and second transparent electrodes

R1, R2: first and second reflection areas T2, T2: first and second transmission areas

The present invention relates to a display substrate and a display panel having the same, and more particularly, to a display substrate for removing vertical line defects and a display panel having the same.

In general, a liquid crystal display device includes a liquid crystal display panel and a backlight unit for providing light to the liquid crystal display panel. The liquid crystal display panel includes a plurality of source wirings and a plurality of gate wirings crossing the source wirings, and a plurality of pixel portions are defined by the source wirings and the gate wirings.

Recently, a reflection-transmissive liquid crystal display device using reflected light is used to realize a liquid crystal display device capable of high quality display with low power consumption. In addition, in order to halve the number of source wires, one source wire is shared and left. The half-life structure for applying the data voltage to the right pixel portion is used.

In the half-half structure as described above, even when the same voltage is applied between adjacent pixel portions sharing the source wiring, a voltage difference is generated due to the coupling capacitance. As described above, a flicker phenomenon in the form of a vertical line occurs on the entire display panel due to the variation in charging voltage between adjacent pixel parts.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a display substrate for improving vertical line defects.

Another object of the present invention is to provide a display panel including the display substrate.

A display substrate in which a plurality of gate lines and a plurality of source lines intersecting the gate lines are formed includes a first pixel portion and a second pixel portion. The first pixel unit may be electrically connected to a first switching element connected to an arbitrary source line and an n−1 (n is a natural number) gate line. The first pixel electrode may include a first transparent electrode and a first reflective electrode. Is formed. The second pixel portion is electrically connected to a second switching element connected to the source line and the n-th gate line, and a second pixel electrode including a second transparent electrode and a second reflective electrode larger than the first reflective electrode is formed. do.

A display panel according to an exemplary embodiment for realizing another object of the present invention includes an array substrate, a liquid crystal layer, and an opposing substrate. The array substrate includes a first pixel portion including a first reflection region and a first transmission region, and a second transmission region sharing a source wiring with the first pixel portion and larger than the second reflection region and the first transmission region. It includes a second pixel portion. It includes a counter substrate coupled to the array substrate to accommodate the liquid crystal layer.

According to the display substrate and the display panel having the same, vertical line defects can be improved by eliminating luminance variations between the pixel portions by adjusting the transmission region between adjacent pixel portions sharing the source wiring.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a plan view of a display substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 1, 2N gate lines extending in a first direction and M / 2 source lines extending in a second direction crossing the first direction are formed on the display substrate. N x M pixel portions defined by the wirings. Where N and M are natural numbers. The display substrate is formed adjacent to each other, and includes a first pixel portion P1 and a second pixel portion P2 that share an arbitrary source wiring DLm.

The first pixel portion P1 includes a first switching element TFT1, a first storage capacitor CST1, and a first pixel electrode PE1 electrically connected to the first switching element TFT1. The first switching element TFT1 may include a first gate electrode 111 connected to a first gate line GLn-1 formed in a first direction, a first source electrode 113 connected to a source line DLm, The first drain electrode 114 is connected to the first pixel electrode PE1.

The first storage capacitor CST1 is defined by a first storage electrode 115 and the first drain electrode 114 formed to overlap the first storage electrode 115.

The first pixel electrode PE1 defines a first reflective electrode 117 that defines a first reflective region R1 that reflects first light, and a first transmissive region T1 that transmits second light. The first transparent electrode 118 is included. Here, the first light is natural light, and the second light is backlight.

The second pixel portion P2 shares the source wiring DLm with the first pixel portion P1. In detail, the second pixel portion P2 includes a second switching element TFT2, a second storage capacitor CST2, and a second pixel electrode PE2 electrically connected to the second switching element TFT2. do. The second switching element TFT2 may include a second gate electrode 121 connected to a second gate line GLn formed in a first direction, a second source electrode 123 connected to the source line DLm, and A second drain electrode 124 connected to the second pixel electrode PE2 is included.

The second storage capacitor CST2 is defined by the second storage electrode 125 and the second drain electrode 124 formed to overlap the second storage electrode 125.

The second pixel electrode PE2 includes a second reflective electrode 127 defining a second reflective region R2 reflecting the first light, and a second transmission region T2 transmitting the second light. A second transparent electrode 128 is defined.

The size ratio R1: T1 of the first reflective region R1 of the first pixel portion P1 and the first transmission region T1 may be equal to the second reflective region R2 of the second pixel portion P2. It is different from the size ratio R2: T2 of the second transmission region T2. Preferably, the size of the first transmission region T1 of the first pixel portion P1 to which the data voltage is first applied through the source wiring DLm is greater than that of the second pixel portion P2 to which the data voltage is applied later. It is formed smaller than the size of the second transmission region (T2). Accordingly, the first reflective region R1 of the first pixel portion P1 is larger than the second reflective region R2 of the second pixel portion P2 ((T1 <T2, R1> R2, T1). + R1 = T2 + R2).

On the other hand, the ratio of the sum of the sum of the first reflection region R1 and the second reflection region R2 and the sum of the sum of the first transmission region T1 and the second transmission region T2 (R1 + R2: T1 + T2) is equal to the ratio of the size ER of the total reflection area and the size ET of the total transmission area of the display substrate (R1 + R2: T1 + T2 = ER: ET).

FIG. 2 is a cross-sectional view of the display panel taken along the line II ′ of FIG. 1.

1 and 2, the liquid crystal display panel includes an array substrate 100, an opposing substrate 200, and a liquid crystal layer 300 formed between the array substrate 100 and the opposing substrate 200.

The array substrate 100 includes a first base substrate 101, and a gate pattern is formed on the first base substrate 101 as a gate metal layer. The gate pattern includes the gate lines GLn-1 and GLn, the first and second storage electrodes 115 and 125, and the first and second gate electrodes 111 and 121.

The gate insulating layer 102 is formed on the first base substrate 101 on which the gate pattern is formed. The channel layer 112 is formed on the gate insulating layer 102 corresponding to the first gate electrode 111. The channel layer 112 includes an active layer 112a and an ohmic contact layer 112b.

A source pattern is formed of a source metal layer on the first base substrate 101 on which the channel layer 112 is formed. The source pattern may include the source wiring DLm, the first source and drain electrodes 113 and 114 of the first switching element TFT1, and the second source and drain electrodes 123 of the second switching element TFT2. 124).

The passivation layer 103 and the insulating layer 104 are formed on the first base substrate 101 on which the source pattern is formed. The insulating layer 104 is patterned and formed in the first reflective region R1. That is, the insulating layer 104 is removed in the first transmission region T1. In addition, a contact hole 116 is formed in the insulating layer 104 of the first reflective region R1. Preferably, the surface of the insulating layer 104 formed in the first reflective region R1 is patterned into an uneven shape to improve reflection efficiency.

The transparent electrode layer is formed on the first base substrate 101 on which the contact hole 116 is formed and patterned to form the transparent electrode 118. The transparent electrode layer is a kind of transmission electrode that transmits light, and indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO) is used.

The transparent electrode 118 is connected to the drain electrode 114 through the contact hole 116. The first reflective electrode 117 is formed in the first reflective region R1 on the transparent electrode 118.

The opposing substrate 200 includes a second base substrate 201, and a black matrix layer 210 defining the pixel area is formed on the second base substrate 201. The color filter pattern 220 is formed in the pixel area defined by the black matrix layer 210. An overcoat layer 230 for protection and planarization is formed on the black matrix layer 210 and the color filter pattern 220. The common electrode layer 240 is formed on the overcoat layer 230. A light hole 221 is formed in the color filter pattern 220 corresponding to the first reflective region R1. In addition, the color filter pattern 220 may be formed thicker with respect to the first transmission region T1 than the first reflection region R1.

The liquid crystal layer 300 is interposed between the array substrate 100 and the opposing substrate 200 so that the voltage applied to the first pixel electrode PE1 of the array substrate 100 and the opposing substrate 200 are common. An array angle of the liquid crystal layer 300 is changed in response to a voltage applied to an electrode layer (not shown). The liquid crystal layer 300 has a different cell gap between the first reflection region R1 and the liquid crystal layer corresponding to the first transmission region T1, and the liquid crystal layer 300 has a normally white mode. to be.

Optimal cell gaps for the first reflective region R1 and the first transmission region T1 may be determined by the conditions of the liquid crystal molecules forming the liquid crystal layer 300 or the optical films provided on both upper and lower sides of the liquid crystal layer 300. Depends. The cell gap d1 corresponding to the first reflective region R1 is smaller than the cell gap d2 corresponding to the first transmission region T1. Preferably, the cell gap d1 corresponding to the first reflective region R1 is about 1/2 of the cell gap d2 corresponding to the first transmission region T1.

3A to 3C are diagrams for describing luminance characteristics of the display panel of the comparative example.

Referring to FIG. 3A, the display panel according to the comparative example has a half-sensitive structure, and the first pixel portion P11 and the second pixel portion 12 share the source wiring DL1. That is, the first pixel portion P11 is driven by the first gate wiring GL1 and the first source wiring DL1, and the first pixel wiring P11 is driven by the second gate wiring GL2 and the first source wiring DL1. It becomes the second pixel portion P12.

The first pixel portion P11 is divided into a first reflection region R11 and a first transmission region T11, and the second pixel portion P12 also includes a second reflection region R12 and a second transmission region. Divided by (T12). The size ratio R11: T11 of the first reflection region R11 and the first transmission region T11 is the size ratio R12: T12 of the second reflection region R12 and the second transmission region T12. Same as each other (R11: T11 = R12: T12)

3A and 3B, when the first gate line GL1 is activated, the odd-numbered pixel portions P11, P13, and P15 connected to the first gate line GL1 may have respective source lines DL1, The data voltages + D delivered by the DL2 and DL3 are charged. For example, the first pixel portion P11 is charged with the first data voltage + D transferred through the first source wiring DL1.

Subsequently, when the second gate line GL2 is activated, the source gates DL1, DL2, and DL3 are transferred to even-numbered pixel parts P12, P14, and P16 connected to the second gate line GL2. Data voltages + D are charged.

As such, as the first source wiring DL1 is shared, the effective charge time of the data voltage is charged in the second pixel portion P12 rather than the effective charge time of charging the data voltage in the first pixel portion P11. Long charging time That is, the voltage difference caused by the coupling capacitance of the charging voltages charged in the first and second pixel units P11 and P12 is generated.

Accordingly, the first pixel portion P11 among the first and second pixel portions P11 and P12 sharing the first source wiring DL1 has a low charge rate and displays a relatively bright gray level. In this case, the display panel is in a normally white mode.

Accordingly, as shown in FIG. 3C, the luminance L of the pixel units P11, P12, P13,... P16 arranged in the same horizontal column is an even number of pixels than the odd pixel units P11, P13, P15. Greater than of the parts P12, P14, P16.

As a result, the display panel of the comparative example has a vertical line due to the luminance difference between the pixel portions of the odd-numbered vertical columns (eg, P11, P21, P31, ..) and the pixel portions of the even-numbered vertical columns (eg, P12, P22, P32,. Flickering of the pattern occurs.

4A to 4C are diagrams for describing luminance characteristics of the display panel of the present invention.

 Referring to FIG. 4A, the display panel according to the exemplary embodiment of the present invention has a half-sensitive structure, and the first pixel portion P11 and the second pixel portion 12 share the source wiring DL1. That is, the first pixel portion P11 is driven by the first gate wiring GL1 and the first source wiring DL1, and the first pixel wiring P11 is driven by the second gate wiring GL2 and the first source wiring DL1. It becomes the second pixel portion P12.

The first pixel portion P11 is divided into a first reflection region R11 and a first transmission region T11, and the second pixel portion P12 also includes a second reflection region R12 and a second transmission region. Divided by (T12). The size ratio R11: T11 of the first reflection region R11 and the first transmission region T11 is the size ratio R12: T12 of the second reflection region R12 and the second transmission region T12. Different from each other (R11: T11 ≠ R12: T12). Preferably, the size of the first transmission region T11 of the first pixel portion P11 is smaller than the size of the second transmission region T12 of the second pixel portion P12. Accordingly, the first reflective region R11 of the first pixel portion P11 is larger than the second reflective region R12 of the second pixel portion P12.

4A and 4B, when the first gate line GL1 is activated, the odd-numbered pixel portions P11, P13, and P15 connected to the first gate line GL1 may have respective source lines DL1, The data voltages + D delivered by the DL2 and DL3 are charged. For example, the first pixel portion P11 is charged with the first data voltage + D transferred through the first source wiring DL1.

Subsequently, when the second gate line GL2 is activated, the even-numbered pixel parts P12, P14, and P16 connected to the second gate line GL2 may be formed by the source lines DL1, DL2, and DL3, respectively. The transferred data voltages + D are charged.

As such, as the first source wiring DL1 is shared, the effective charge time of the data voltage is charged in the second pixel portion P12 rather than the effective charge time of charging the data voltage in the first pixel portion P11. Long charging time That is, the voltage difference caused by the coupling capacitance of the charging voltages charged in the first and second pixel units P11 and P12 is generated.

Meanwhile, as the first transmission region T11 of the first pixel portion P11 is formed smaller than the second transmission region T12 of the second pixel portion P12, the first and second pixel portions P11, Visually compensate for the luminance difference of P12). The display panel is in a normally white mode.

As a result, as shown in FIG. 4C, the luminance L of the pixel portions P11, P12, P13,... P16 arranged in the same horizontal column has substantially the same brightness. Therefore, it is possible to prevent the flicker phenomenon of the vertical stripes as in the comparative example.

As described above, according to the present invention, the vertical line defects can be visually eliminated by forming different transmission regions between adjacent pixel portions sharing the source wiring in the reflection-transmissive display panel having the half-sensitive structure of the source wiring.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (8)

In a display substrate on which a plurality of gate lines and a plurality of source lines crossing the gate lines are formed, A first pixel portion electrically connected to a first switching element connected to an arbitrary source line and an n-1 (n is a natural number) gate line, and including a first pixel electrode including a first transparent electrode and a first reflective electrode ; And A second pixel part electrically connected to a second switching element connected to the source line and the n-th gate line and having a second pixel electrode including a second transparent electrode and a second reflecting electrode smaller than the first reflecting electrode; Display substrate. The display substrate of claim 1, wherein the first pixel portion and the second pixel portion have substantially the same size. The display device of claim 1, wherein the first reflective electrode is formed on the first transparent electrode to divide the first pixel portion into a first transmission region and a first reflection region. The second reflective electrode is formed on the second transparent electrode to divide the second pixel portion into a second transmission region and a second reflection region, The second transmission region is larger than the first transmission region. The display device of claim 3, further comprising a plurality of pixel portions defined by the gate lines and the source lines. The ratio of the size of the total reflection area to the total transmission area of the plurality of pixel parts is substantially equal to the sum of the sizes of the first and second reflection areas and the sum of the sizes of the first and second transmission areas. Display substrate, characterized in that. The method of claim 3, wherein the first reflective region of the first pixel portion and the second transmissive region of the second pixel portion are adjacent to each other. And a first reflective region of the first pixel portion and a second reflective region of the second pixel portion are adjacent to each other. A first pixel portion including a first reflection region and a first transmission region, and a second pixel portion including a second reflection region and a second transmission region larger than the first transmission region and sharing a source wiring with the first pixel portion; An array substrate comprising; Liquid crystal layer; And And a counter substrate coupled to the array substrate to accommodate the liquid crystal layer. The display panel of claim 6, wherein the opposing substrate further comprises a color filter pattern formed to correspond to each pixel portion. The display panel of claim 6, wherein the liquid crystal layer is in a normally white mode.

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