KR20070058114A - Manufacturing method of semiconductor device - Google Patents

Abstract

The present invention discloses a method for manufacturing a semiconductor device. The disclosed method comprises the steps of: forming a first interlayer insulating film on a front surface of a semiconductor substrate divided into cell regions and peripheral regions, each of which has several gates and junction regions, and a first formed in the cell region; Etching the interlayer insulating film to form a first contact hole for exposing several gates and junction regions at the same time; forming a contact plug on the junction region between the gates by embedding a conductive film in the first contact hole; Forming a second interlayer insulating film of a BPSG film on the substrate resultant; forming an etch blocking nitride film on the second interlayer insulating film; and etching the nitride film and the second and first interlayer insulating films. Forming a second contact hole exposing the junction region of the peripheral region, performing ion implantation to reduce contact resistance in the exposed region of the junction region; Cleaning a surface of the junction region of the exposed peripheral region and forming a bit line on the second interlayer insulating layer to contact the junction region of the peripheral region through a second contact hole, wherein the peripheral region junction region is formed. In cleaning the surface, the nitride film blocks unwanted etching of the second interlayer insulating film made of the BPSG film.

Description

Method of manufacturing semiconductor device

1 is a cross-sectional view illustrating a method of forming a bit line of a conventional semiconductor device.

2A to 2D are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to the present invention.

Explanation of symbols on the main parts of the drawings

21: semiconductor substrate 22: gate

23: spacer 24: first interlayer insulating film

25: first contact hole 26: contact plug

27: second interlayer insulating film 28: etching prevention nitride film

29: second contact hole 30: barrier film

31: metal film 32: bit line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing process margins and deterioration of device characteristics caused by a BPSG film, which is an interlayer insulating film material.

BACKGROUND ART In accordance with high integration of semiconductor devices, in most semiconductor manufacturing processes, BPSG (Boron Phosphorous Silicate Glass) films having good gap-fill and planarization characteristics are used as interlayer insulating films.

Hereinafter, a bit line forming method according to the prior art will be described with reference to FIG. 1.

Referring to FIG. 1, several gates 2 and spacers 3 are formed on a semiconductor substrate 1 having a cell region and a peripheral region, and a source is formed in the substrate surface on both sides of the gate including the spacers 3. / Drain region (not shown) is formed. Then, after the first interlayer insulating film 4 is deposited on the entire area of the substrate for electrical separation between the gates, the first interlayer insulating film 4 formed in the cell region is etched to form the gate 2 and the junction region. A landing plug contact 5 for simultaneously exposing the same, and filling a landing plug conductive film in the landing plug contact 5 to form a landing plug on the junction region between the gates; 6) form.

Next, after depositing a BPSG film 7 as a second interlayer insulating film on the substrate resultant, and then the second interlayer insulating film 7 and the first interlayer insulating film 4 below it is etched to A bit line contact 8 is formed to expose the junction region (not shown).

Subsequently, although not shown, a barrier film and a metal film are sequentially deposited on the substrate including the bit line contact, and then patterned to form a bit line.

Herein, reference numeral a denotes a gate oxide film, b denotes a gate conductive film, and c denotes a gate hard mask film.

However, as described above, when the BPSG film is used as the interlayer insulating film in forming the bit line, the following problem occurs.

First of all, the BPSG film needs to be subjected to high temperature annealing after deposition for its densification due to the characteristics of the film. In this high temperature annealing process, device characteristics may fluctuate and degrade.

In addition, the BPSG film has a faster wet etching rate than the High Density Plasma (HDP) oxide film, and the BPSG film implanted with impurity ion implantation to lower the contact resistance is undesirable for wet etching using a subsequent BOE or HF solution. Etching occurs and a step (A in FIG. 1) occurs in the BPSG film.

As a result of the step difference generated in the BPSG film, a bit line may be disconnected or shorted when a subsequent bit line is formed, resulting in a malfunction of the device.

Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing the deterioration of device characteristics caused by the BPSG film, which is an interlayer insulating film material, to solve the above problems.

In order to achieve the above object, the present invention comprises the steps of forming a first interlayer insulating film on the front surface of the semiconductor substrate is divided into a cell region and a peripheral region, each of which has several gates and junction regions; Etching a first interlayer dielectric layer formed in the cell region to form a first contact hole exposing several gates and junction regions simultaneously; Embedding a conductive film in the first contact hole to form a contact plug on the junction region between the gates; Forming a second interlayer insulating film of a BPSG film on the substrate resultant; Forming an etch blocking nitride film on the second interlayer insulating film; Etching the nitride film and the second and first interlayer insulating films to form a second contact hole exposing a junction region in a peripheral area; Performing ion implantation to reduce contact resistance in the junction region of the exposed peripheral region; Cleaning a junction surface of the exposed peripheral area; And forming a bit line on the second interlayer insulating layer, the bit line contacting the junction region of the peripheral region through a second contact hole, wherein the nitride layer is formed of a BPSG layer when the surface of the peripheral region junction region is cleaned. A method of manufacturing a semiconductor device comprising blocking unwanted etching of an interlayer dielectric film is provided.

Here, the nitride film is formed by a deposition process or a plasma treatment process.

The deposition process is characterized in that performed according to the PECVD method or LPCVD method.

The PECVD method is characterized in that it is carried out under the condition that the RF power is 100 to 2000 kW, the pressure is 0.1 to 20 Torr and the temperature is 300 to 600 ℃.

The nitride film using the deposition process is characterized in that it is formed to a thickness of 30 ~ 300Å.

The plasma treatment process may be performed using a PECVD apparatus or an HDP-CVD apparatus.

The PECVD apparatus is a Capacitive-Coupled Plasma (CCP) PEVCD apparatus having a plasma generation frequency of 13.56 MHz, and the plasma processing process using the CCP PECVD apparatus uses NH 3 and N 2 while RF power is 100 to 2000 Hz, The pressure is 0.1 to 20 Torr, the interval at which the wafer is placed is characterized in that it is carried out under the condition of 5 to 100mm.

The flow rate of the NH 3 gas is 10 to 500 sccm, and the flow rate of the N 2 gas is 1 to 5000 sccm.

The HDP-CVD apparatus may be an Inductive-Coupled Plasma (ICP) HDP-CVD apparatus having a plasma generation frequency of 1 to 4 MHz, and the plasma processing process using the ICP HDP-CVD apparatus uses N2. LF power is 100-6000 kPa, pressure is 1-100 mTorr, temperature is 300-700 degreeC, and HF bias power is 1-3000 kPa.

Here, the flow rate of the N2 gas is characterized in that 10 to 1000sccm.

The washing is characterized in that it is carried out using a BOE solution or HF solution.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention, when the BPSG film is used as an interlayer insulating film material, a thin nitride film having a slow etching rate on the BPSG film by a deposition process or a plasma treatment process, and then for contact formation Proceed with etching.

In this case, when the BPSG film is used as the interlayer insulating film material, the nitride film formed on the BPSG film serves to block unwanted etching of the BPSG film during the subsequent cleaning process using the BOE or HF solution, thereby preventing a step in the BPSG film. Do not.

That is, after the contact is formed, ion implantation is performed on a part of the BPSG film when ion implantation for reducing contact resistance is performed. As such, the surface of the ion-implanted BPSG film has a high etching rate during subsequent cleaning, so that a step is generated in the present invention. Thus, in the present invention, a nitride film having a slow etching speed is deposited or plasma treated on the BPSG film before forming the bit line contact. By vapor deposition, the step difference of the BPSG film can be prevented.

2A to 2D are cross-sectional views illustrating processes for manufacturing a semiconductor device according to the present invention, which will be described below.

Referring to FIG. 2A, a plurality of gates including a gate oxide film A, a gate conductive film B, and a gate hard mask film C may be formed on a semiconductor substrate 21 having a cell region and a peripheral region. 22) and a spacer 23 made of an oxide film or a nitride film are formed, and then source / drain ion implantation is performed on the substrate product to form a junction region (not shown) in the substrate surface on both sides of the gate 22 including the spacer 23. C).

Then, after depositing the first interlayer insulating film 24 on the substrate resultant, the first interlayer insulating film 24 formed in the cell region is etched to expose several gates 22 and the junction region at the same time to expose the first contact hole. To form 25. Next, after the plug conductive film is deposited on the entire surface of the substrate to fill the first contact hole 25, CMP is deposited until the gate 22 is exposed, and then the contact plug 26 is formed on the junction region between the gates. ).

Referring to FIG. 2B, after the second interlayer dielectric layer 27 made of the BPSG film is deposited on the substrate resultant, an etch blocking nitride layer 28 is formed on the second interlayer dielectric layer 27. Here, the nitride film 28 serves to block unwanted etching of the second interlayer insulating film during the subsequent cleaning process.

Here, the nitride film 28 is deposited to a thickness of 30 ~ 300 Pa according to the Plasma Enhanced Chemical Vapor Deposition (PECVD) method or Low Pressure CVD (LPCVD) method. At this time, the PECVD method is carried out under the condition of using a mixed gas of SiH 4 + NH 3 + N 2, RF power of 100-2000 kPa, pressure of 0.1-20 Torr, and temperature of 300-600 ° C. In addition, He or Ar may be added to change the thin film formation rate.

The nitride film 28 is formed by a plasma treatment process. Here, the plasma treatment process is performed using a PECVD apparatus or a High Density Plasma-CVD (HDP-CVD) apparatus. The PECVD apparatus is a Capacitive-Coupled Plasma (CCP) PEVCD apparatus having a plasma generation frequency of 13.56 MHz, and the HDP-CVD apparatus is an Inductive-Coupled Plasma (ICP) HDP-CVD apparatus having a plasma generation frequency of 1 to 4 MHz.

In this case, the plasma processing process using the CCP PECVD apparatus is performed using NH 3 and N 2 while the RF power is 100 to 2000 kW, the pressure is 0.1 to 20 Torr, and the interval at which the wafer is placed is 5 to 100 mm. The flow rate of the gas is 10 to 500 sccm, and the flow rate of the N2 gas is 1 to 5000 sccm. In addition, He or Ar may be added to improve treatment uniformity and to vary the treatment speed.

The plasma processing process using the ICP HDP-CVD apparatus is carried out under the condition that LF power is 100 to 6000 kW, pressure is 1 to 100 mTorr, temperature is 300 to 700 ° C., and HF bias power is 1 to 3000 kW while using N2. . The flow rate of the N2 gas is set to 10 to 1000 sccm. In addition, He or Ar may be added to improve treatment uniformity and to vary the treatment speed.

In the present invention, when the BPSG film is used as the interlayer insulating film material, a thin nitride film having a slow etching rate is formed on the BPSG film by a deposition process or a plasma treatment process, thereby preventing unwanted etching of the BPSG film during subsequent cleaning. It is possible to prevent the step of the membrane.

In other words, when ion implantation for reducing contact resistance is performed in the junction region, ion implantation also occurs in a part of the BPSG film, which is an interlayer insulating film. As a result, the surface of the ion implanted BPSG film is conventionally etched at a subsequent cleaning progress, resulting in a step due to unwanted etching. Accordingly, the present invention can prevent the step of the BPSG film by forming a nitride film having a slow etching rate on the BPSG film by a deposition process or a plasma treatment process.

Referring to FIG. 2C, the nitride layer 28, the second 27, and the first interlayer dielectric layer 24 are etched to form a second contact hole 29 exposing a junction region in a peripheral area. Then, ion implantation is performed to reduce contact resistance in the junction region of the exposed peripheral region. Next, the junction area surface of the exposed peripheral area is cleaned using BOE or HF solution. At this time, the nitride film formed on the BPSG film during the cleaning may block the etching of the BPSG film to prevent the step in the BPSG film.

Referring to FIG. 2D, the barrier layer 30 and the metal layer 31 are sequentially deposited on the second interlayer insulating layer 27, and then patterned to form a junction region in the peripheral region through the second contact hole 29. The bit line 32 in contact with is formed.

As described above, when the BPSG film is used as the interlayer insulating film material, the nitride film is formed on the BPSG film, thereby preventing the step of the BPSG film during the subsequent cleaning process. Accordingly, even in the etching process for forming the bit line contact hole, the metal residue generated by the step difference of the BPSG film is eliminated, thereby preventing the short line or the disconnection of the bit line. Therefore, the yield improvement of a device can be expected.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

Claims (13)

Forming a first interlayer insulating film on a front surface of the semiconductor substrate which is divided into a cell region and a peripheral region, and in which several gates and junction regions are formed in each region; Etching a first interlayer dielectric layer formed in the cell region to form a first contact hole exposing several gates and junction regions simultaneously; Embedding a conductive film in the first contact hole to form a contact plug on the junction region between the gates; Forming a second interlayer insulating film of a BPSG film on the substrate resultant; Forming an etch blocking nitride film on the second interlayer insulating film; Etching the nitride film and the second and first interlayer insulating films to form a second contact hole exposing a junction region in a peripheral area; Performing ion implantation to reduce contact resistance in the junction region of the exposed peripheral region; Cleaning a junction surface of the exposed peripheral area; And And forming a bit line on the second interlayer insulating layer, the bit line contacting a junction region of a peripheral region through a second contact hole. And when the surface of the peripheral region junction region is cleaned, the nitride film blocks unwanted etching of the second interlayer insulating film made of the BPSG film. The method of claim 1, wherein the nitride film is formed by a deposition process or a plasma treatment process. The method of claim 2, wherein the deposition process is performed by PECVD or LPCVD. The method of manufacturing a semiconductor device according to claim 3, wherein the PECVD method is performed under a condition that RF power is 100 to 2000 kPa, pressure is 0.1 to 20 Torr, and temperature is 300 to 600 ° C. The method for manufacturing a semiconductor device according to claim 3, wherein the nitride film using the vapor deposition process is formed to have a thickness of 30 to 300 GPa. The method of claim 2, wherein the plasma processing process is performed using a PECVD apparatus or an HDP-CVD apparatus. The method of claim 6, wherein the PECVD apparatus is a Capacitive-Coupled Plasma (VCP) PEVCD apparatus having a plasma generation frequency of 13.56 MHz. 8. The plasma processing process using the CCP PECVD apparatus according to claim 7, wherein the plasma processing process using NH3 and N2 is performed under conditions of 100-2000 kW RF power, 0.1-20 Torr pressure, and 5-100 mm spacing of wafers. A semiconductor device manufacturing method characterized by the above-mentioned. The method of manufacturing a semiconductor device according to claim 7, wherein the flow rate of the NH 3 gas is 10 to 500 sccm, and the flow rate of the N 2 gas is 1 to 5000 sccm. The method of claim 6, wherein the HDP-CVD apparatus is an Inductive-Coupled Plasma (ICP) HDP-CVD apparatus having a plasma generation frequency of 1 to 4 MHz. The plasma processing process using the ICP HDP-CVD apparatus according to claim 10, wherein the LF power is 100-6000 kPa, the pressure is 1-100 mTorr, the temperature is 300-700 ° C., and the HF bias power is 1-3000 kPa while N2 is used. A method for manufacturing a semiconductor device, characterized in that carried out under phosphorus conditions. The method of manufacturing a semiconductor device according to claim 11, wherein the flow rate of the N2 gas is 10 to 1000 sccm.  The method of claim 1, wherein the cleaning is performed using a BOE solution or an HF solution.

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