KR20070040841A - How to process data words in multiple processing cycles - Google Patents

Abstract

The present invention relates to the processing of a data word in multiple processing cycles. In order to perform the processing efficiently, the data word is divided during each cycle into a number of consecutive data blocks. Blocks are shifted by one block from one cycle to the next. In each cycle, each successive block is processed in sequence. In the first processing cycle, the processing results for consecutive data blocks of the first cycle are stored in the memory of memory addresses that vary constantly from one processing result to the next. In each next processing cycle, at a memory address that varies constantly from one processing result in the next to the next, the processing results stored in memory during the previous processing cycle and for successive data blocks of the next processing cycle. Combine the processing results.

Block, processing, cycle, memory address, data word

Description

Processing a data word in a multiple of processing cycles

The present invention relates to a method of processing data words in multiple processing cycles. The present invention relates to a processing module, an electronic device, and a system corresponding to the above processing method. Finally, it relates to a corresponding software program product.

Data words must be processed in various applications in multiple cycles, for example block correlation. Block correlation can be used to determine the phase shift between a known data word and a received data word, for example to track satellite signals at a satellite based navigation system.

In a Global Positioning System (GPS), for example, code modulated signals are transmitted by several satellites orbiting the earth and received by GPS receivers whose current position is determined. Each of the satellites transmits two microwave carrier signals. One of these carrier signals L1 is used to transmit code signals of a navigation message and a standard positioning service (SPS). The L1 carrier signal is modulated by the respective satellites into various Coarse Acqusition (C / A) codes known at the receiver. Thus, various channels are obtained for transmission by various satellites. The C / A code, which includes values of -1 and 1, and has been spread with a bandwidth of 1 MHz, is repeated every 1023 chips, and the code epoch is 1 ms. The term chip is used to establish bits of C / A code. The carrier frequency of the L1 signal is modulated with the navigation information at a bit rate of 50 bits / s. Navigation information constituting the data sequence may be calculated, for example, to determine the location of each receiver.

A receiver receiving a code modulated signal must access a synchronous replica of the modulation code used to be able to de-spread the data sequence of the signal. In particular, synchronization must be performed between the received code modulated signal and the available duplicated code. Usually, an initial synchronization called "acquisition" is followed by an elaborate synchronization called "tracking". In both synchronization processes, correlators are used to find the best match between the duplicate code sequence and the received signal, and then to find a relative shift called the code phase. During the acquisition process, the phase of the received signal as compared to the available replica code may have a possible value due to the uncertainty of the position of the satellite and the transmission time of the received signal.

As correlators, for example block correlators may be used.

1 is a diagram schematically illustrating an operation of a block correlator.

The correlator accesses known fixed data words, for example C / A codes. In an embodiment of the invention, this data word is represented by the bit string "ABCDEFGH". Also, samples are input to the correlator, where the samples are samples of the received satellite signals. In one embodiment of the invention, such a sample is represented by the bit string "abcdefghiabc ...". The correlator now determines the available data word and the input samples for each possible phase shift, and the correlation between the available data word and the received samples.

The block correlator successively divides the entire available data word into N = 3 data blocks, block 'ABC', block 'DEF' and block 'GHI', with samples having a length of L = 3, respectively. This is shown at 11 in FIG. 1. The first L = 3 incoming samples 'abc' are shown at 12 in FIG. 1.

The correlator then multiplies the bits of each block by the first L = 3 incoming samples 'abc', integrates each multiplication result, and stores each integration result in a contiguous memory address. For example, the value 'A * a + B * b + C * c' is stored at memory address '1' and the value 'D * a + E * b + F * c' is stored at memory address '2' The value 'G * a + H * b + I * c' is stored at memory address '3'. Each stored integration result represents a partial correlation value.

The same process is repeated for the input samples 'bcd' and the integration result is stored in consecutive memory addresses '4', '5' and '6', respectively. The same process is also repeated for input samples 'cde' and stored at consecutive memory addresses '7', '8' and '9'.

Now, the first three input samples 'abc' are fully processed and all N x L used at memory addresses '1' through '9' are filled with partial correlation results for a particular phase shift. This memory allocation is shown on the left side of FIG.

The block correlator continues to divide the entire available data word into N = 3 data blocks 'ABC', 'DEF' and 'GHI'. The multiplication and integration described are repeated for each of the next N x L data blocks and the next three input samples 'def'. The partial correlation values already stored at the appropriate memory addresses are added to the integration results shown to the right of 13 in FIG. 1, as indicated by the arrows in 13 to FIG. 1.

For example, the value 'A * d + B * e + C * f' is added to the current value stored at memory address '3', and the value 'D * d + E * e F * f' is added to memory address '1' In addition to the current value stored at ', the value' G * d + H * e + I * f 'is stored at the current value stored at memory address' 2'.

If the input samples 'def' are fully processed, the block correlator continues to divide the entire available data word into N = 3 data blocks 'ABC', 'DEF' and 'GHI'. The multiplication and integration described are repeated for each of the next N x L data blocks and the last three input samples 'ghi'. In order to obtain the last correlation values for each phase shift, the integration results are added to the partial correlation values already stored at the appropriate memory addresses '1' through '9'. This processing part is not shown in FIG.

Therefore, the final correlation value stored at memory address '1' is 'A * a + B * b + C * c + D * d + E * e + F * f + G * g + H * h + I * i' The final correlation value stored at memory address '2' is 'D * a + E * b + F * c + G * d + H * e + I * f + A * g + B * h + C * i' The final correlation value stored at memory address '3' is 'G * a + H * b + I * c + A * d + B * e + C * f + D * g + E * h + F * i' And so on. In total, there are nine different correlation values for nine different phase shifts, stored at memory addresses '1' through '9' between available code and incoming samples.

As shown in FIG. 1, the combination of new partial correlation values and stored partial correlation values requires a jump when accessing the memory. Thus, memory addresses must be calculated for each combination by a complex state machine.

Especially in the case of many more than nine samples belonging to a data word, the computational effort performed by the state machine is significant. For example, it is known that a GPS receiver uses N = 31 blocks with L = 66 samples in one iteration of the C / A code.

The present invention provides methods, processing modules, devices, systems and software program products that can more effectively use available resources, in particular processing resources.

A method of processing a data word in a plurality of processing cycles, the method comprising dividing the data word into a plurality of contiguous data blocks during each processing cycle, the contiguous data blocks being one Shift by one data block from processing cycle to next processing cycle. The proposed method further comprises processing, in each of said processing cycles, each of said successive data blocks in sequence. The proposed method further comprises storing, in a first processing cycle, processing results for the successive data blocks of the first cycle in a memory of memory addresses that vary constantly from one processing result to the next. . The proposed method is characterized in that in each next processing cycle, the processing results stored in the memory during the previous processing cycle and the next processing cycle are stored at a memory address that constantly varies from one processing result in the next processing cycle to the next processing result. Combining the processing results for the consecutive data blocks.

Also proposed is a processing module for processing data words in multiple processing cycles. The processing module includes a data word splitting component that divides the data word into a plurality of consecutive data blocks during each processing cycle, wherein the consecutive data blocks are shifted by one data block from one processing cycle to the next. Will be added. The proposed processing module further includes a processing component that processes each of the consecutive data blocks in sequence in each of the processing cycles. The proposed processing module stores, in the first processing cycle, processing results for the successive data blocks of the first cycle in a memory of memory addresses that constantly vary from one processing result to the next processing result, and each next In a processing cycle, at a memory address that constantly varies from one processing result in the next processing cycle to the next processing result, the processing results stored in the memory during the previous processing cycle and the successive data blocks of the next processing cycle. It further comprises a coupling component for combining the processing results for.

The processing module may be implemented in hardware, but may be implemented identically in software or in a combination of hardware and software.

Also proposed is an electronic device comprising such a processing module.

It is also proposed a system comprising such a processing module and at least one other module that exchanges the processing module and data at least uni-directionally.

Finally, a software program product is proposed, which stores software code for processing data words in multiple processing cycles. The software code implements the steps of the proposed method when running on a processing component.

The present invention is based on the fact that if blocks of data words are already processed in each processing cycle in the proper order, the need for jumping between memory addresses can be avoided. Thus, it is proposed that the order of access to the memory addresses be rearranged during each processing cycle such that the data blocks correspond to the actual order of the memory addresses involved. This is accomplished by shifting the data blocks by one block each from one processing cycle to the next.

The advantage of the present invention is that it can reduce the number of calculations required. During each processing cycle, one calculation is needed instead of many calculations to determine the memory address for each memory access. In particular, the present invention is advantageous in applications where a large number of data blocks must be processed.

It is also an advantage of the present invention that it can be implemented in a simple and flexible manner. For example, data words of different lengths and data blocks of different lengths can be readily used.

In general, all relevant memory addresses will be accessed exactly once during the processing cycle. It is obvious that during each processing cycle, a data word can be represented more than once by the data blocks. Data blocks will usually be selected so that integer data blocks represent the entire data word.

The memory addresses can be changed constantly, for example by increasing or decreasing the address by a fixed value for each processing result in one processing cycle.

In one embodiment of the invention, the access of the memory is accomplished with an address pointer that is incremented for each memory access in a round rotation manner. In other words, at the start of a new processing cycle, the pointer starts new from the initial memory address. For example, a pointer can be used as a coupling component for storing and combining processing results. Such an address pointer can be very simple and small.

Shifting a sequence of data blocks by one block means, for example, moving the first data block of the previous processing cycle last, and the sequence of data blocks moves to the previous second data block in each processing cycle. It starts to win.

In one embodiment of the invention, this is implemented by generating circularly and continuously, except that one data block is skipped at the beginning of each next processing cycle.

In one embodiment of the processing module of the present invention, the data word splitting component comprises a data word generator, a multiplexer and a counter to achieve this purpose. The data word generator generates data word blocks in a circular fashion. The counter counts the number of blocks generated and provides a control signal to the multiplexer each time the number of blocks needed during one processing cycle is generated. The multiplexer causes the data word generator to generate successive blocks of data words, unless the counter provides a control signal, and the data word generator skips one block of the data word each time the counter provides a control signal. Do it.

 It is known that conventional code correlators provide code blocks generated in a counter to enable tracking of code phase. This counter can be used by ensuring that each time the counter rotates round, it further advances one block in the circular order of known code blocks.

The present invention can be used in applications that use block-oriented algorithms. Block correlation in hardware is an example of such applications. In block correlation, the data word is correlated block by block with the samples provided. In this case the data word may be a known code, for example, and the samples provided may be samples of the received code modulated signal.

Thus, processing of data blocks involves some kind of block processing that produces intermediate results that must be stored at other memory addresses or must be combined with values already stored at other memory addresses. Depending on the application, combining the results of the new processing with the stored processing results may include any kind of combining, such as addition or multiplication, or simply storing the new processing result in already stored results.

The electronic device according to the present invention can be any device in which a data word must be processed in multiple processing cycles. This may be a mobile or fixed device. The electronic device may be, for example, but not limited to, a satellite signal receiver such as a mobile phone, a code division multiple access (CDMA) capable receiver or a CPS receiver. It may also be a device combining other functions, such as a mobile phone including a GPS receiver. In such a case, data word processing according to the present invention may be implemented in a device having one or more functions.

The system according to the present invention may be various kinds of systems, including the features described below.

The system may include a receiver as an additional module, for example, receiving signals via an air interface and providing the received signals to a processing module for calculations including block processing. The processing module may be connected directly to the receiver, via a cable, or via an air interface. For example, if the receiver is a satellite signal receiver and is part of a mobile communication device, the processing module may be part of a mobile communication network in which samples of signals are provided for calculation.

Optionally, the system may include the network components of the mobile communication network as additional modules, for example when the processing module is a mobile terminal. The network component may provide auxiliary data to the mobile terminal in order to support block-based processing.

Also optionally, the system may be a satellite based navigation system comprising, for example, at least one satellite as an additional module, and a processing module further comprising the functionality of a receiver. The processing module may receive signals transmitted from these satellites.

Other objects and features of the present invention will become apparent from the following detailed description with reference to the accompanying drawings. However, the drawings are presented for purposes of illustration only, and the scope of the present invention is not limited thereto. The scope of the present invention is defined by the appended claims. In addition, regardless of the size shown in the drawings for the purpose of illustrating the configuration and process described below.

1 is a diagram illustrating a conventional memory allocation.

2 is a schematic system block diagram according to an embodiment of the present invention.

3 is a block diagram of a correlator of the system of FIG.

4 is a flowchart for describing an operation of the correlator of FIG. 3.

FIG. 5 is a diagram for explaining a principle of memory allocation of the correlator of FIG. 3.

<Explanation of symbols for the main parts of the drawings>

20: mobile device 21: GPS module

22: Receive component 23: Correlator

24: Compute Component 29: GPS Satellite

2 is a schematic block diagram of a GPS positioning system implemented with data word processing according to an embodiment of the present invention.

The positioning system includes a mobile device 20 and a number of GPS satellites 29.

Mobile device 200 can be any mobile device including GPS module 21. For example, mobile device 20 may be a cellular terminal that includes the essential components of a cellular terminal capable of communicating over a cellular network. Optionally, the mobile device 20 may be a portable digital assistant (PDA), for example. Also optionally, it may be a pure GPS device.

The GPS module 21 comprises a receiving component, a correlator implemented in hardware (HW) and / or software (SW), and a computing component 24. Here, the computing component 24 is a different component of the mobile device 20. It may be or part of the processor used for the functions.

The correlator 23 is shown in more detail in the block diagram of FIG. 3.

In the correlator 23, the code generator 30 receives control signals from the multiplexer 31. The output of the code generator 30 is fed back to the control input of the multiplexer 31 via the counter 32. The multiplexer 31 forwards one of the two control signals to the code generator 30 in accordance with the signal at the control input. The first control signal indicates the command 'increase by L chip', while the second control signal '�' indicates 'increase by 2L chip'.

The output of the code generator 30 is also connected to the input of a bit-wise multiplier 34 via a code shift register 33 that can store L chips.

In addition, a sample shift register 35, which can store L samples, is connected to the input of the multiplier 34 in units of bits. The sample shift register 35 receives input samples from the receiving component 22 of the GPS module 21.

The output of the bitwise multiplier 34 is connected to the memory 38 through the integrator 36 and the coupling component 37. The memory 38 is again coupled to the second input of the coupling component 37. The bitwise multiplier 34, integrator 36 and coupling component 37 form an adder tree.

The operation of the correlator 23 will now be described with reference to the flowcharts of FIGS. 4 and 5. The diagram of FIG. 5 illustrates the principle of operation by brief illustration.

When the GPS module 21 receives a signal from the GPS satellites 29, the GPS module 21 must determine the code phase of the signal and the satellite that sent the signal. To this end, the receiving component 22 forwards the samples of the received signal to the correlator 23 at a known sampling rate.

In the correlator 23, the first L samples are stored in the sample shift register 35 (step 401). In the schematic example shown in FIG. 5, L is 3 and the first stored in the sample shift register 35 Three samples are 'abc' and are shown at 12.

At the same time, code generator 30 generates the first block of C / A code (step 402). C / A codes are known to be used by particular GPS satellites, satellites 29 which transmit possible signals. The generated block contains L subsequent chips of the code and is stored in the code register 33. In the schematic example shown in FIG. 5, the first L = 3 samples stored in the code register 33 are 'ABC' and are shown at 11.

The multiplier 34 then multiplies the samples from the sample shift register 35 and the chips of the code register 33 bit by bit. Integrator 36 integrates the multiplication results, and combining component 37 stores the integration results as a partial correlation value in the first memory address of memory 38 (step 403). Unless the memory 38 includes any partial correlation values in the associated memory address, the coupling component 37 has no summation tasks.

In the example of FIG. 5, the partial correlation value 'A * a + B * b + C * c' is stored at memory address '1' of the memory 38, which is shown at 13.

Each time, the code generator 30 outputs a block and also provides a corresponding indication to the counter 32. Starting with a zero counter value, the counter 32 receives a signal from the code generator 30 and increments the counter value by one until the N x L counter value is reached. Only when the N × L counter value is reached, the counter provides the control signal to the multiplexer 31.

As long as N blocks or less are processed (step 404), the L samples in the sample shift register 34 remain the same. N blocks contain all samples of the code exactly once. The code generator 30 generates the next block with L chips at regular intervals because the multiplexer 31 provides the code generator 30 with an instruction 'increment by L chips' (step 402). No signal is provided to the counter 32. The new block is generated by the code generator 30 at a frequency that is N times greater than the sampling frequency. Each next block is correlated with the samples stored in the sample shift register 35, as described for the first block, and the resulting partial correlation value is stored in the memory of the memory address incremented by one for the new partial correlation value. (Step 403). In the example shown in FIG. 5, the second code block is 'DEF' and the second correlation result 'D * a + E * b + F * c' is stored at the memory address '2'. The third code block is 'GHI', and the third correlation result 'G * a + H * b + I * c' is stored at the memory address '3'.

After the input samples of the sample shift register 35 are provided to the multiplier 34 for N times to process the Nth block output by the code generator 30 (step 404), another input sample is sent to the sample shift register 35. Is stored in step 405. This is achievable by allowing the entire correlator 23 as well as the code generator 30 to be operated at a frequency that is N times greater than the sampling frequency. In the example shown in FIG. 5, the three samples stored in the sample shift register are now 'bcd'.

As long as the counter 32 does not reach the value 'N x L' (step 406), the code generator 30 generates the next block of code, determines each partial correlation value, and increments the memory address by one. Continue storing the results in memory 38 (steps 402, 403, 404). After each N partial correlation values have been determined, or after the Nth partial correlation value has been determined, a new sample is input to the sample shift register 35 for the next N partial correlation values (steps 404, 405).

In the example of FIG. 5, the fourth block is again 'ABC', the fifth block is 'DEF' and the sixth block is 'GHI'. The fourth partial correlation value 'A * b + B * c + C * d' is stored in memory address' 4 ', and the fifth partial correlation value' D * b + E * c + F * d 'is stored in memory address' 5 'and the sixth partial correlation value' G * b + H * c + I * d 'is stored in memory address' 6'. The next three samples stored in the sample shift register 35 are 'cde', the seventh block is 'ABC' again, the eighth block is 'DEF', and the ninth block is 'GHI'. The seventh partial correlation value 'A * c + B * d + C * e' is stored in memory address' 7 'and the eighth partial correlation value' D * c + E * d + F * e 'is stored in memory address' 8 'and the ninth partial correlation value' G * c + H * d + I * e 'is stored in memory address' 9'.

When the counter 32 reaches the value 'N x L' (step 406), all blocks for the first processing cycle are provided by the code generator 30. The resulting partial correlation values are stored in N × L available memory addresses, each belonging to a different phase shift between the received samples and the known code. In the example of FIG. 5, correlation values are stored at nine available memory addresses '1' through '9' after the first processing cycle.

During the next processing cycle, the counter 32 provides a control signal to the multiplexer 31, and the multiplexer 31 provides the code generator 30 with an instruction 'increment by 2L chips'. As a result of the control signal from the multiplexer 31, the code generator 30 generates the next 2L chips, but outputs the last L chips to the code register 33. That is, one block having the length of the L chips is skipped at the output of the code generator 30 (steps 407 and 408). In the example of FIG. 5, as in the case of the conventional block correlator, the ninth block 'GHI' follows the tenth block 'DEF' in place of the block 'ABC'. Samples in the sample register 35 are automatically updated to 'def'.

The multiplier 34 then multiplies the blocks from the code register 33 by the bits from the sample shift register 35 again. Integrator 36 integrates the multiplication results. The value stored at the first memory address of the memory 38 by the coupling component 37 is added to the integration result forming another partial correlation value (step 409). In the example of FIG. 5, the value 'A * a + B * b + C * c stored at the first memory address' 1' of the memory 38 at the partial correlation value 'D * d + E * e + F * f' 'Is added.

This process is repeated for the next N-1 blocks (steps 410, 408, 409). In the example of FIG. 5, the partial correlation value 'G * d + H * e + I * f' has a value 'D * a + E * b + F * c' stored at the memory address '2' of the memory 38. Is added. After that, the value 'G * a + H * b + I * c' stored at the memory address '3' of the memory 38 is added to the partial correlation value 'A * d + B * e + C * f'.

After that, a new sample is input again to the sample shift register 35 (steps 410 and 411). In the example of FIG. 5, this results in the register value of the sample shift register 24 of 'efg'.

As before (steps 408, 409, 410), partial correlation values are determined for these register values with successively generated blocks. In the example of FIG. 5, the generated blocks are again blocks' DEF ', GHI' and 'ABC'. The partial correlation value 'D * e + E * f + F * g' is added with the value 'A * b + B * c + C * d' stored at the memory address '4' of the memory 38. The partial correlation value 'G * e + H * f + I * g' is added with the value 'D * b + E * c + F * d' stored at the memory address '5' of the memory 38. The partial correlation value 'A * e + B * f + C * g' is added to the value 'G * b + H * c + I * d' stored at the memory address '6' of the memory 38.

Also, each new sample is input into the sample shift register 35 after each N new blocks are generated until the next N x L blocks are processed. In the example of FIG. 5, the last input sample in this cycle results in the value 'fgh' of the sample shift register 36.

Partial correlations are performed at respective values in the sample shift register 35 for successively generated blocks (steps 408-412). Each determined partial correlation value is combined with the values stored at each next memory address. In the example of FIG. 5, the last blocks during the second processing cycle are again blocks 'DEF', 'GHI' and 'ABC'. The partial correlation value 'D * f + E * g + F * h' is added with the value 'A * c + B * d + C * e' stored at the memory address '7' of the memory 38. The partial correlation value 'G * f + H * g + I * h' is added with the value 'D * c + E * d + F * e' stored at the memory address '8' of the memory 38. The partial correlation value 'A * f + B * g + C * h' is added with the value 'G * c + H * d + I * e' stored at the memory address '9' of the memory 38.

Steps 407-412 continue until all N x L x N processing cycles are completed. At the beginning of each processing cycle, if the next block is generated (step 408), one block is skipped (step 407).

In the example of FIG. 5, the last value of the memory at memory address' 1 'is, for example,' A * a + B * b + C * c + D * d + E * e + F * f + G * g + H * h + I * i '. This value is the correlation value for the zero phase shift between the received signal and a known C / A code. At the remaining eight memory addresses '2' through '9', the last correlation values for the eight possible different phase shifts are stored.

Due to a shift by one block at the beginning of each processing cycle, the required memory address can be obtained through a correlation process by simple round rotation of the available memory addresses, which can be implemented by a simple small address pointer. have. Thus, the jump between memory addresses and the complex state machines required in conventional block correlators are not necessary.

Although embodiments of the present invention have been described in order to facilitate understanding of codes divided into three blocks of three samples each, those skilled in the art will understand that they are not limited to the number of samples per block.

Further use of the last correlation values is known in the art. The last correlation values may be provided to the calculation component 24 by the memory 38, for example, and the final correlation values determine whether the C / A code under consideration is the correct C / A code for the received signal. Calculated to determine the exact phase shift. The obtained information can be used for later processing steps required by the functions provided by the GPS module 21, for example, decoding the received signal, extracting the navigation information, and navigating the navigation information and the measurement results. It can be used to determine the current location of the mobile device 20 based. The GPS module 21 may provide location information, for example, to an application running on the mobile device 20.

Although described above based on the preferred embodiments of the present invention, those skilled in the art will understand that it can be carried out in other specific forms without changing the technical spirit or essential features of the technical field to which the present invention belongs. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. The scope of the present invention is defined by the appended claims rather than the foregoing description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

Claims (18)

A method of processing a data word in multiple processing cycles, The method, Dividing the data word into a plurality of consecutive data blocks during each processing cycle, wherein the consecutive data blocks are shifted by one data block from one processing cycle to the next processing cycle; In each of the processing cycles, processing each of the consecutive data blocks in sequence; In a first processing cycle, storing processing results for the successive data blocks of the first cycle in a memory of memory addresses that constantly vary from one processing result to the next processing result; And  In each subsequent processing cycle, the processing results stored in the memory during the preceding processing cycle and the next processing at a memory address that varies constantly from one processing result in the next processing cycle to the next processing result. Combining the processing results for the successive data blocks of a cycle. The method of claim 1, To store and combine the processing results, And the memory is addressed with an incremented address pointer for each memory access in a round rotating manner. The method of claim 1, To shift the consecutive data blocks by each data block from one processing cycle to the next processing cycle, Consecutive data blocks of the data word, A method of processing data words, characterized in that one data block is generated cyclically and continuously except that it is skipped at the start of each next processing cycle. The method of claim 1, Processing the consecutive data blocks may include: And correlating block-by-block with the samples provided and the known data word. The method of claim 4, wherein The data word is a known data code, And said provided samples are samples of a code modulated signal. A processing module for processing a data word in multiple processing cycles, The processing module, A data word dividing component that divides the data word into a plurality of consecutive data blocks during each processing cycle, wherein the consecutive data blocks are shifted by one data block from one processing cycle to the next processing cycle; A processing component that processes each of the consecutive data blocks in sequence in each of the processing cycles; And In a first processing cycle, storing processing results for the successive data blocks of the first cycle in a memory of memory addresses that vary constantly from one processing result to the next,  In each next processing cycle, the processing results stored in the memory during the previous processing cycle and the continuous data of the next processing cycle, at a memory address that constantly varies from one processing result in the next processing cycle to the next processing result. A data word processing module comprising a combining component that combines the processing results for the blocks. The method of claim 6, Coupling component for storing and combining the processing results, And an incremented address pointer for each memory access in a round rotational manner. The method of claim 6, To shift the consecutive data blocks by each data block from one processing cycle to the next processing cycle, The data word division component is A data word processing module, characterized in that it generates circularly and continuously except that one data block is skipped at the beginning of each next processing cycle. The method of claim 6, The data word division component is Includes a data word generator, a multiplexer and a counter, The data word generator generates blocks of the data word in a cyclic manner; The counter counters the number of blocks generated, provides a predetermined control signal to the multiplexer each time the number of blocks needed for one processing cycle is generated, The multiplexer causes the data word generator to generate successive blocks of the data word unless the counter provides the control signal, and each time the counter provides the control signal, the data word generator causes the data word. And skip one block of the data word processing module. The method of claim 6, The processing component, And processing the successive blocks of data by correlating the data word block by block with the provided samples. The method of claim 10, The data word is a known code, And said provided samples are samples of a code modulated signal. The method of claim 6, And said processing module is implemented in hardware. An electronic device comprising a processing module for processing data words in a number of processing cycles, the method comprising: The processing module, A data word dividing component that divides the data word into a plurality of consecutive data blocks during each processing cycle, wherein the consecutive data blocks are shifted by one data block from one processing cycle to the next processing cycle; A processing component that processes each of the consecutive data blocks in sequence in each of the processing cycles; And In a first processing cycle, storing processing results for the successive data blocks of the first cycle in a memory of memory addresses that vary constantly from one processing result to the next, In each next processing cycle, the processing results stored in the memory during the previous processing cycle and the continuous data of the next processing cycle, at a memory address that constantly varies from one processing result in the next processing cycle to the next processing result. A combining component that combines the processing results for the blocks, Electronic device. The method of claim 13, The device, An electronic device, characterized in that a mobile phone. The method of claim 13, The device, An electronic device, characterized in that the receiver is capable of code division multiple access. The method of claim 13, The device, An electronic device, characterized in that the satellite signal receiver. A system comprising a processing module for processing a data word in a plurality of processing cycles and at least one other module for exchanging data with the processing module at least uni-directionally, The processing module, A data word dividing component that divides the data word into a plurality of consecutive data blocks during each processing cycle, wherein the consecutive data blocks are shifted by one data block from one processing cycle to the next processing cycle; A processing component that processes each of the consecutive data blocks in sequence in each of the processing cycles; And In a first processing cycle, storing processing results for the successive data blocks of the first cycle in a memory of memory addresses that vary constantly from one processing result to the next, In each next processing cycle, the processing results stored in the memory during the previous processing cycle and the continuous data of the next processing cycle, at a memory address that constantly varies from one processing result in the next processing cycle to the next processing result. A combining component that combines the processing results for the blocks, system. Is a stored software program product for processing a data word in multiple processing cycles, the software code implementing the following steps when executed in a processing component:  Dividing the data word into a plurality of consecutive data blocks during each processing cycle, wherein the consecutive data blocks are shifted by one data block from one processing cycle to the next processing cycle; In each of the processing cycles, processing each of the consecutive data blocks in sequence; In a first processing cycle, storing processing results for the successive data blocks of the first cycle in a memory of memory addresses that constantly vary from one processing result to the next processing result; And  In each next processing cycle, the processing results stored in the memory during the previous processing cycle and the continuous data of the next processing cycle, at a memory address that constantly varies from one processing result in the next processing cycle to the next processing result. A software program product comprising combining the processing results for the blocks.

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