KR20070038331A - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

The thin film transistor array panel includes a pixel electrode formed on a substrate, a gate line formed on the substrate, a gate insulating film formed on the gate line, a data line and a drain electrode formed on the gate insulating film, and the data line. And a passivation film formed over a portion of the drain electrode, wherein the gate line includes a first film formed on the same layer as the pixel electrode and a second film formed over the first film. As such, since the gate line and the pixel electrode are formed using one mask, the manufacturing process is simplified and the manufacturing cost is reduced.

Thin film transistor display panel, slit, mask, photoresist, pixel electrode, gate line

Description

Thin film transistor array panel and manufacturing method thereof {THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF}

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

2A and 2B are cross-sectional views of the thin film transistor array panel of FIG. 1 taken along lines IIa-IIa and IIb-IIb, respectively.

 3A and 3B are cross-sectional views of the thin film transistor array panel of FIG. 1 taken along lines IIa-IIa and IIb-IIb, respectively, illustrating a first process of manufacturing a thin film transistor array panel.

4A and 4B are views in the next steps of FIGS. 3A and 3B, respectively.

Figures 5a and 5b show the next steps in Figures 4a and 4b respectively.

Figures 6a and 6b show the next steps in Figures 5a and 5b, respectively.

7, 11, and 13 are layout views at intermediate stages of the method for manufacturing the thin film transistor array panel shown in FIGS. 1 to 2B according to one embodiment of the present invention, respectively, and are arranged in order of process.

8A and 8B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 7 taken along the lines VIIIa-VIIIa and VIIIb-VIIIb, respectively.

9A and 9B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 7 taken along the lines VIIIa-VIIIa and VIIIb-VIIIb, respectively, and are views of the next steps of FIGS. 8A and 8B.

Figures 10a and 10b show the next steps in Figures 9a and 9b respectively.

12A and 12B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 11 taken along the lines XIIa-XIIa and XIIb-XIIb, respectively.

14A and 14B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 13 taken along the XIVa-XIVa line and the XIVb-XIVb line, respectively.

15A and 15B are diagrams in the next step of FIGS. 14A and 14B, respectively.

16A and 16B are diagrams illustrating the next steps of FIGS. 15A and 15B, respectively. FIG. 17 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention.

18A and 18B are cross-sectional views of the thin film transistor array panel of FIG. 17 taken along lines XVIIIa-XVIIIa and XVIIIb-XVIIIb, respectively.

 19A and 19B are cross-sectional views of the thin film transistor array panel of FIG. 17 taken along lines XVIIIa-XVIIIa and XVIIIb-XVIIIb, respectively, illustrating a first process of manufacturing a thin film transistor array panel.

20A and 20B are views at the next stage of FIGS. 19A and 19B, respectively.

21A and 21B are views in the next step of FIGS. 20A and 20B, respectively.

22, 26 and 28 are layout views at intermediate stages of the method for manufacturing the thin film transistor array panel shown in FIGS. 17 to 18B according to one embodiment of the present invention, respectively, and are arranged in the order of the process.

23A and 23B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 22 taken along the lines XXIIIa-XXIIIa and XXIIIb-XXIIIb, respectively.

24A and 24B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 22 taken along the lines XXIIIa-XXIIIa and XXIIIb-XXIIIb, respectively, and are views of the next steps of FIGS. 23A and 23B.

Figures 25a and 25b show the next steps in Figures 24a and 24b respectively.

27A and 27B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 26 taken along the lines XXVIIa-XXVIIa and XXVIIb-XXVIIb, respectively.

29A and 29B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 28 taken along the lines XXIXa-XXIXa and XXIXb-XXIXb, respectively.

30A and 30B are views in the next steps of FIGS. 29A and 29B, respectively.

31A and 31B are views in the next step of FIGS. 30A and 30B, respectively.

The present invention relates to a thin film transistor array panel and a method of manufacturing the same. Active matrix display devices such as liquid crystal displays (LCDs) or organic light emitting displays (organic light emitting displays) are arranged in a substantially matrix form and include field generating electrodes and switching elements ( A plurality of pixels including a switching element is included. Examples of the switching elements include thin film transistors (TFTs) having three-terminal elements of a gate, a source, and a drain, and the thin film transistors of each pixel are applied to a gate. The data signal applied to the source is transmitted to the field generating electrode in response to the signal.

The display device also includes a plurality of signal lines for transmitting signals to the thin film transistors, and the signal lines include gate lines for transmitting gate signals and data lines for transmitting data signals.

The liquid crystal display and the organic light emitting display include a display panel including a thin film transistor, a field generating electrode, and a signal line, which is called a thin film transistor display panel.

The thin film transistor array panel has a layered structure in which a plurality of conductive layers and an insulating layer are stacked. The gate line, the data line and the field generating electrode are made of different conductive layers and separated into insulating layers.

As described above, the thin film transistor array panel having a layered structure is completed through several photolithography processes and accompanying etching processes. The photographic process is not only costly but also takes a long time, so it is desirable to reduce the number if possible.

An object of the present invention is to simplify the manufacturing process of a thin film transistor array panel.

Another object of the present invention is to reduce the defective rate of the thin film transistor array panel.

According to an aspect of the present invention, a thin film transistor array panel includes a pixel electrode formed on a substrate, a gate line formed on the substrate, a gate insulating film formed on the gate line, and formed on the gate insulating film. A semiconductor layer, a data line and a drain electrode formed on the gate insulating layer, and a passivation layer formed on a portion of the data line and the drain electrode, wherein the gate electrode is formed of the same material as the pixel electrode. And a second film formed on the first film.

According to another aspect of the present invention, a thin film transistor array panel includes a pixel electrode formed on a substrate, a gate line formed on the substrate, a gate insulating film formed on the gate line, a semiconductor layer formed on the gate insulating film, and the gate. A first layer formed of the same material on the same layer as the pixel electrode, wherein the gate line includes a data line and a drain electrode formed on the insulating layer, and a passivation layer formed on a portion of the data line and the drain electrode. And a second layer formed on the first layer, and further comprising a conductor made of the same material as the gate line in a portion where the gate insulating layer and the pixel electrode overlap and a portion where the drain electrode and the pixel electrode overlap. .

The pixel electrode may be made of a transparent conductive material.

The second layer of the gate line is formed of a first layer made of molybdenum (alloy), a second layer formed on the first layer and made of aluminum (alloy), and a second layer made of molybdenum (alloy). It may include three layers.

It is preferable that the gate insulating film overlaps a part of an edge of the pixel electrode.

Preferably, the passivation layer partially overlaps an edge of an adjacent pixel electrode.

The protective layer may further include an insulating pattern having a columnar spacer.

The protective film preferably has the same planar shape as the insulating pattern.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor, the method comprising: forming a transparent conductor layer on a substrate, forming a conductor layer on the transparent conductor layer, forming a first photosensitive film on the conductor layer, and Etching the conductor layer using a first photoresist film as a mask and using a first etchant, and etching the transparent conductor layer using a second etchant different from the first etchant as a mask using the first photoresist film as a gate line Forming a second photoresist film by changing the first photoresist film, forming a pixel electrode by using the second photoresist film as a mask, and removing the exposed conductor layer using the first etchant; Forming a gate insulating film on the gate line and the pixel electrode, forming a semiconductor layer on the gate insulating film, Forming a data line and a drain electrode on the semiconductor layer, sequentially laminating a first and a second insulating layer on the data line and the drain electrode, and exposing the second insulating layer to form an insulating pattern having a spacer. And forming a passivation layer by etching the first insulating layer using the insulating pattern as a mask.

According to another aspect of the present invention, a method of manufacturing a thin film transistor includes forming a transparent conductor layer on a substrate, forming a first conductor layer on the transparent conductor layer, and forming a photoresist film on the first conductor layer. Etching the first conductor layer using the photosensitive film as a mask and using a first etchant, and etching the transparent conductor layer using the second etchant different from the first etchant and using the photosensitive film as a mask. Forming a gate pattern comprising: forming a gate insulating film on the gate pattern; forming a semiconductor layer on the gate insulating film; forming a second conductor layer on the semiconductor layer; Etching the exposed gate pattern to form a data line, a drain electrode, and a pixel electrode; Sequentially stacking first and second insulating layers on the emitter line, the drain electrode, and the pixel electrode; exposing the second insulating layer to form an insulating pattern having a spacer; and using the insulating pattern as a mask. Etching the first insulating layer to form a protective film. The first etchant is preferably an integrated etchant.

The second etchant may be a pixel integrated etchant.

The first photoresist layer may be formed using an optical mask having a light blocking region, a transflective region, and a light transmissive region.

The forming of the second photosensitive film may include an ashing process.

The photosensitive film may be formed using a photomask having a light blocking area and a light transmitting area.

According to another aspect of the present invention, a method of manufacturing a thin film transistor array panel includes: forming a transparent conductor layer on a substrate, forming a conductor layer on the transparent conductor layer, forming a first photoresist film on the conductor layer, Forming a gate line by etching the conductor layer and the transparent conductor layer by using the first photoresist film as a mask and using an etchant, changing the first photoresist film to form a second photoresist film, and the second photoresist film Forming a pixel electrode by removing the exposed conductive layer using a photosensitive film as a mask, forming a gate insulating film on the gate line and the pixel electrode, forming a semiconductor layer on the gate insulating film, and the semiconductor layer Forming a data line and a drain electrode thereon; first and second data lines on the data line and drain electrode; Stacking an insulating layer in sequence, exposing the second insulating layer to form an insulating pattern having a spacer, and etching the first insulating layer using the insulating pattern as a mask to form a protective film It includes.

According to another aspect of the present invention, a method of manufacturing a thin film transistor array panel includes forming a transparent conductor layer on a substrate, forming a first conductor layer on the transparent conductor layer, and forming a photosensitive film on the first conductor layer. Forming a gate pattern including a gate line by etching the first conductor layer and the transparent conductor layer by using one photoresist as a mask, and forming a gate insulating film on the gate pattern; Forming a semiconductor layer on the gate insulating layer, forming a second conductor layer on the semiconductor layer, and etching the gate pattern exposed by the second conductor layer to form a data line, a drain electrode, and a pixel electrode First and second insulating layers are sequentially stacked on the data line, the drain electrode, and the pixel electrode. And exposing the second insulating layer to form an insulating pattern having a spacer, and etching the first insulating layer using the insulating pattern as a mask to form a protective film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity, and like reference numerals designate like parts throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Next, a thin film transistor array panel for a liquid crystal display will be described in detail with reference to FIGS. 1 to 2B.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 2A and 2B are cross-sectional views illustrating the thin film transistor array panel of FIG. 1 taken along lines IIa-IIa and IIb-IIb, respectively. to be.

A plurality of pixel electrodes 191 and a transparent conductor 95 are formed on an insulating substrate 110 made of transparent glass or plastic.

Although they are preferably made of amorphous ITO (a-ITO), which is a transparent conductive material having a good profile during the etching process, they may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver, chromium or an alloy thereof. Can be made.

Side surfaces of the pixel electrode 191 and the transparent conductor 95 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

A plurality of gate lines 121 are formed on the substrate 110.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. Each gate line 121 includes a plurality of gate electrodes 124 protruding upward and downward and a wide end portion 129 for connection with another layer or an external driving circuit. A gate driving circuit (not shown) for generating a gate signal may be mounted on a flexible printed circuit film (not shown) attached to the substrate 110 or directly mounted on the substrate 110, It may be integrated into the substrate 110. When the gate driving circuit is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The gate line 121 has a triple layer structure including a lower layer, an intermediate layer, and an upper layer. The lower layer is made of refractory metals such as molybdenum, chromium, tantalum, and titanium, or an alloy thereof, and the intermediate layer is made of aluminum, metal, silver, copper, etc., which have low resistivity, and the upper layer is made of amorphous ITO, or the like. Its contact properties are made of refractory metals or alloys thereof. Examples of such a triple film structure include a molybdenum (alloy) lower film, an aluminum (alloy) interlayer, and a molybdenum (alloy) upper film.

The gate line 121 may have a double layer structure including a refractory metal lower layer (not shown) and a low resistance upper layer (not shown) or a single layer structure made of the aforementioned materials. Examples of the double film structure include a chromium or molybdenum (alloy) bottom film and an aluminum (alloy) top film. However, the gate line 121 may be made of various other metals or conductors.

In FIG. 2A and FIG. 2B, the gate electrode 124 and the end portion 129 of the gate line are denoted by adding the lowercase letter p, the middle layer the letter q, and the upper layer the letter r.

The side surface of the gate line 121 is inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

The transparent conductor 95 exists only under the gate line 121.

The gate insulating layer 140 is made of silicon nitride (SiNx) or silicon oxide (SiOx) to cover the gate line 12 on the gate line 121 except for the end portion 129 of the gate line 121. ) Is formed. In order to increase the aperture ratio of the pixel, the gate insulating layer 140 overlaps some edges of the pixel electrode 191. On the gate insulating layer 140, a plurality of island semiconductors 154 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated as a-Si), polycrystalline silicon, or the like are formed. The semiconductor 154 is positioned over the gate electrode 124.

A plurality of island type ohmic contacts 163 and 165 are formed on the semiconductor 154. The ohmic contacts 163 and 165 may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus are heavily doped, or may be made of silicide. The ohmic contacts 163 and 165 are paired and disposed on the semiconductor 154.

Side surfaces of the semiconductor 154 and the ohmic contacts 163 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is about 30 ° to 80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 163 and 165, the gate insulating layer 140, and a portion of the pixel electrode 191.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate line 121. Each data line 171 includes a plurality of source electrodes 173 extending toward the gate electrode 124 and a wide end portion 179 for connection with another layer or an external driving circuit. . A data driving circuit (not shown) for generating a data signal is mounted on a flexible printed circuit film (not shown) attached to the substrate 110, directly mounted on the substrate 110, or integrated in the substrate 110. Can be. When the data driving circuit is integrated on the substrate 110, the data line 171 may be extended to be directly connected to the data driving circuit.

The drain electrode 175 is separated from the data line 171 and faces the source electrode 173 around the gate electrode 124. Each drain electrode 175 has a rod shape. One portion of the drain electrode 175 overlaps the pixel electrode 191, and the opposite portion is partially surrounded by the source electrode 173 bent in a C shape.

One gate electrode 124, one source electrode 173, and one drain electrode 175 together with the semiconductor 154 form one thin film transistor (TFT), and a channel of the thin film transistor. ) Is formed in the semiconductor 154 between the source electrode 173 and the drain electrode 175.

The data line 171 and the drain electrode 175 are preferably made of a refractory metal such as molybdenum, chromium, tantalum, and titanium, or an alloy thereof, and include a refractory metal film (not shown) and a low resistance conductive film. It may have a multilayer structure including (not shown). Examples of the multilayer structure include a double layer of chromium or molybdenum (alloy) lower layer and an aluminum (alloy) upper layer, and a triple layer of molybdenum (alloy) lower layer and aluminum (alloy) interlayer and molybdenum (alloy) upper layer. However, the data line 171 and the drain electrode 175 may be made of various other metals or conductors.

The side of the data line 171 and the drain electrode 175 may also be inclined at an inclination angle of about 30 ° to about 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 163 and 165 exist only between the semiconductor 154 thereunder and the data line 171 and the drain electrode 175 thereon to lower the contact resistance therebetween.

The pixel electrode 191 is physically and electrically connected to the drain electrode 175 and receives a data voltage from the drain electrode 175. The pixel electrode 191 to which the data voltage is applied has a liquid crystal between the two electrodes by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied. The direction of the liquid crystal molecules in the layer (not shown) is determined. The polarization of light passing through the liquid crystal layer varies according to the direction of the liquid crystal molecules determined as described above. The pixel electrode 191 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off. You can also have other capacitors connected in parallel.

The semiconductor 154 includes portions exposed between the source electrode 173 and the drain electrode 175 and not covered by the data line 171 and the drain electrode 175.

A plurality of linear passivation layers 180 are formed on the data line 171, the drain electrode 175, and the exposed semiconductor 154.

The passivation layer 180 mainly covers the gate line 121 and the data line 171 extending in the vertical direction. Each passivation layer 180 includes an extension that protrudes upward and downward in a portion where the source electrode 173 and the drain electrode 175 are formed, and overlaps some edges of the adjacent pixel electrode 191, but adjacent pixels It may or may not have the same boundary as the electrode 191.

The passivation layer 180 may be made of an inorganic insulator or an organic insulator, and may have a flat surface. Examples of the inorganic insulator include silicon nitride and silicon oxide. The organic insulator may have photosensitivity and the dielectric constant is preferably about 4.0 or less. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portion of the semiconductor 154 while maintaining excellent insulating properties of the organic layer.

A plurality of insulating patterns 322 including a plurality of columnar spacers 321 are formed on the passivation layer 180.

Since the insulating patterns 322 have the same planar shape as the passivation layer 180, the insulation patterns 322 extend along the gate line 121 and the data line 171, similarly to the passivation layer 180.

The plurality of columnar spacers 321 are formed only in a portion through which light does not pass, such as on the thin film transistor portion, and protrude by a predetermined thickness on the insulating pattern 322.

Alternatively, the plurality of columnar spacers 321 may be formed on a portion of the gate line 121 or a portion of the data line 171.

Next, a method of manufacturing the thin film transistor array panel shown in FIGS. 1 to 2B according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 to 15B and FIGS. 1 to 2B.

7, 11, and 13 are layout views at an intermediate stage of the method for manufacturing the thin film transistor array panel shown in FIGS. 1 to 2B according to one embodiment of the present invention, respectively, and are arranged in order of process;

3A and 3B are cross-sectional views of the thin film transistor array panel of FIG. 1 taken along lines IIa-IIa and IIb-IIb, respectively, illustrating a first process of manufacturing the thin film transistor array panel, and FIGS. 4A and 4B. 3A and 3B are respectively shown in the following steps, FIGS. 5A and 5B are respectively shown in the following steps, FIGS. 4A and 4B respectively, and FIGS. 6A and 6B are respectively shown in the following steps, respectively. to be. 8A and 8B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 7 taken along the lines VIIIa-VIIIa and VIIIb-VIIIb, respectively. 9A and 9B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 7 taken along the lines VIIIa-VIIIa and VIIIb-VIIIb, respectively. FIGS. 8A and 8B illustrate the following steps, and FIGS. 10A and 10B. 9A and 9B are diagrams in the next step, respectively. 12A and 12B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 11 taken along the lines XIIa-XIIa and XIIb-XIIb, respectively. 14A and 14B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 13 taken along the XIVa-XIVa line and the XIVb-XIVb line, respectively, and FIGS. 15A and 15B are diagrams at the next steps of FIGS. 16A and 16B are views in the next steps of FIGS. 15A and 15B, respectively.

First, as illustrated in FIGS. 3A and 3B, an amorphous ITO (a-ITO) film is sputtered on an insulating substrate 110 made of transparent glass to form a transparent conductor layer 190. Subsequently, the conductor layer 120 including the lower molybdenum layer 120p, the aluminum layer 120q, and the upper molybdenum layer 120r, such as metal, was laminated by sputtering, and then the photoresist film 40 was deposited thereon. To a thickness of 2 μm. The photomask 50 is aligned on the substrate 110 and then exposed through the photomask 50.

The photomask 50 includes a transparent substrate 51 and an opaque light shielding layer 52 thereon, and is divided into a light transmissive area TA1, a light shielding area BA1, and a transflective area SA. The light blocking layer 52 has an opening located in the transmissive area TA1 and a slit located in the transflective area SA. The openings and slits are determined by whether the width is larger than a predetermined value, where the opening is when the width is larger than the predetermined value and the slit is when the width is smaller than the predetermined value.

When the photosensitive film 40 is irradiated with light through the photomask 50 and then developed, the thickness of the developed photosensitive film 40 varies depending on the location, and given appropriate process conditions, the sum of the layers may be selected due to the difference in thickness of the photosensitive film 40. Can be etched with Therefore, a plurality of gate lines 121 including the gate electrode 124, the pixel electrode 191, and the transparent conductor 95 are formed through a series of etching steps.

A process of forming the plurality of gate lines 121, the pixel electrodes 191, and the transparent conductor 95 will be described in more detail.

As shown in FIGS. 3A and 3B, the transflective area SA faces the pixel electrode 191, the light blocking area BA1 faces the gate line 121, and the other parts of the light transmissive area TA1. ).

When the photosensitive film 40 is irradiated with light through the photomask 50 and then developed, the first portion 42 having a thicker thickness and the first portion 42 having a thicker thickness as shown in FIGS. 4A and 4B. The thin second portion 44 remains. In FIG. 3A and FIG. 3B, the hatched portions mean portions that disappear after development.

As shown in FIGS. 5A and 5B, the exposed conductor layer 120 is etched at once using the remaining photoresist portions 42 and 44 as etch masks. At this time, the etchant used is an etchant containing phosphoric acid, nitric acid, acetic acid and additives in an appropriate ratio, preferably containing 60-75% phosphoric acid, 2-8% nitric acid, 5-15% acetic acid and 0.5-3% additives. Integral etchant can be used.

The integrated etchant has a good profile during etching and does not affect the transparent conductor layer 190 formed below, thereby preventing a pattern defect due to etching of the undesired transparent conductor layer 190.

The exposed transparent conductor layer 190 is etched using the remaining photoresist portions 42 and 44 as an etching mask to form the pixel electrode 191 and the transparent conductor 95. In this case, an undercut may be formed in the lower portion of the etched conductor layer 20 in which a portion of the etched transparent conductor layer 90 is dug inward.

In this case, the etchant used includes an etchant containing a good profile of sulfuric acid and nitric acid having a good profile when the transparent conductor layer 190 is etched, and preferably includes a pixel-integrated etchant including 0.02-10% sulfuric acid 2-15% nitric acid. Can be used.

However, instead of etching the conductor layer 120 and the transparent conductor layer 190 sequentially using two different etchant such as the integrated etchant and the pixel integrated etchant, the conductive layer 120 and the transparent layer are formed using one etchant. The conductor layer 190 may be etched at the same time. This simplifies the manufacturing process and reduces manufacturing costs.

6A and 6B, an ashing process or the like is performed to remove the second portion 44 of the photosensitive film 40, while reducing the thickness of the first portion 42 to reduce the photosensitive film portion. Form 47. As a result, the upper layer 20r of the conductor layer 20 positioned under the second portion 44 of the photosensitive film 40 is revealed.

As shown in Figs. 7 to 8B, the conductor layer 20 is etched at once by using the photosensitive film portion 47 as an etch mask to form a gate line 121 including the gate electrode 124. The gate line 121 including the gate electrode 124 is formed. In this case, the etchant used may include an etchant including phosphoric acid, nitric acid, acetic acid, and additives in an appropriate ratio, and preferably, an integrated etchant may be used. At this time, since the side etching is performed along with the side of the conductor layer 20 exposed to the side, the undercut generated in the lower portion of the conductor layer 20 is eliminated.

9A and 9B, the gate insulating layer 140, the intrinsic amorphous silicon (a-Si) layer 150 which is not doped with impurities, and the amorphous silicon (n + a-Si) layer 160 which is doped with impurities are formed. ) Is successively laminated by plasma chemical vapor deposition (PECVD) or the like, and then the photosensitive film 60 is applied thereon with a thickness of 1 µm to 2 µm. As the material of the gate insulating layer 140, silicon nitride is preferable, and the stacking temperature is preferably low temperature such as about 240 ° C. to 280 ° C. in order to prevent surface damage of the pixel electrode 191 stacked below, or the thickness is 2,000 to 5,000. It is preferable that it is about degree. In this case, when the gate insulating layer 140 is formed, a deposition method in which the lower pixel electrode 191 is not reduced may be used instead of a low temperature deposition method such as about 240 ° C to 280 ° C. By the heat generated when the gate insulating layer 140 is formed, the amorphous ITO used as the material of the transparent conductor layer 190 is changed into poly ITO (poly ITO), thereby improving transmittance of the pixel.

Next, the photosensitive film 60 is irradiated with light through a photomask (not shown) and then developed. The thickness of the developed photoresist film varies depending on the position. In FIGS. 9A and 9B, the photoresist film 60 is formed of first to third portions whose thickness becomes smaller. The first part located in the area A and the second part located in the area B are denoted by reference numerals 62 and 64, respectively, and no reference has been given to the third part located in the area C. This is because the portion has a thickness of zero, which exposes the amorphous silicon layer 160 doped with impurities below. The ratio of the thicknesses of the first portion 62 and the second portion 64 varies depending on the process conditions in the subsequent process, but the thickness of the second portion 64 is 1/2 of the thickness of the first portion 62. It is preferable to set it as the following, for example, it is good that it is about 4,000 Pa or less.

As described above, there may be various methods of varying the thickness of the photoresist film according to the position. In the exposure mask, a translucent area as well as a light transmitting area and a light blocking area may be provided. For example. The semi-transmissive region includes a slit pattern, a lattice pattern, or a thin film having a medium or medium transmittance. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photosensitive film with a conventional mask having only a light transmitting area and a light blocking area, and then reflowing to allow the photosensitive film to flow down to a region in which no light remains.

10A and 10B, the amorphous silicon layers 160 and 150 are sequentially etched using the remaining photoresist film portions 62 and 64 as an etch mask, and then an ashing process is performed to perform the ashing process of the photoresist film 60. While removing the second portion 64, the thickness of the first portion 62 is reduced to form the photoresist portion 67.

11 to 12B, the exposed amorphous silicon layers 160 and 150 and the exposed gate insulating layer 140 are sequentially etched using the photoresist portion 67 as an etch mask, thereby forming a plurality of island-like impurity semiconductors. The layer 63, the plurality of island semiconductors 154, and the gate insulating layer 140 are formed.

13 to 14B, the plurality of data lines 171 including the source electrode 173 and the source layer 173 are deposited by etching a conductive layer 170 such as a metal to a predetermined thickness by sputtering or the like. A plurality of drain electrodes 175 are formed. Next, the island-type ohmic contacts 163 and 165 are formed by removing the exposed impurity semiconductor layer 63 without being covered by the source electrode 173 and the drain electrode 175.

Next, as shown in FIGS. 15A and 15B, the first insulating layer 80 and the second insulating layer 320 made of the photosensitive material are sequentially stacked.

Next, as shown in FIGS. 16A and 16B, the second insulation layer 320 is irradiated with light through a slit mask (not shown) or the like and developed to form an insulation pattern 322 including a plurality of gap materials 321. ).

The thickness of the insulating pattern 322 varies depending on the position, and the height of the insulating pattern 322 formed on a portion of the portion where the light does not pass on the thin film transistor is higher than the height of the insulating pattern 322 formed in the other portion. To form an overhanging protrusion, which serves as the columnar spacer 321. The columnar spacer 32 formed as described above may be formed on a portion of the data line 171 or a portion of the gate line 121.

Next, the exposed first insulating layer 80 is etched using the insulating pattern 322 including the columnar spacer 321 as a mask to complete the passivation layer 180 (see FIGS. 1 and 2B). In this case, since the second insulating layer 320 is etched to extend along the gate line 121 and the data line 171 to form the insulating pattern 322, the passivation layer 180 also has the gate line 121. And extend along the data line 171.

As described above, in the present embodiment, since the pixel electrode 191 is formed together with the gate line 121 using one mask, the manufacturing process is simplified and the manufacturing cost is reduced.

In addition, when the thin film transistor array panel is manufactured, an insulating pattern having a spacer is formed together, and a protective film is formed using the insulating pattern without using a separate mask, thereby reducing manufacturing time and cost of the thin film transistor array panel. .

Furthermore, since the pixel electrode is formed under the protective film, the thickness of the protective film having a predetermined thickness or more can be reduced to protect the lower layer due to the etching process for forming the pixel electrode.

Next, a thin film transistor according to another exemplary embodiment of the present invention will be described in detail with reference to FIGS. 17 to 18B.

17 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention, and FIGS. 18A and 18B are cross-sectional views illustrating the thin film transistor array panel of FIG. 17 taken along lines XVIIIa-XVIIIa and XVIIIb-XVIIIb, respectively.

The layer structure of the thin film transistor according to the present embodiment is almost the same as that of FIGS.

That is, the pixel electrode 191 and the transparent conductor 95 are formed on the substrate 110, and the gate insulating layer 140, the plurality of island semiconductors 154, and the plurality of island resistive contact members 163 and 165 are formed thereon. ) Are formed one after the other. A plurality of data lines 171 and a plurality of drain electrodes 175 including a source electrode 173 are formed on the ohmic contacts 163 and 165, and a plurality of passivation layers 180 are formed thereon. An insulating pattern 322 including a plurality of columnar spacers 321 is formed on the passivation layer 180.

Unlike the thin film transistor array panel of FIGS. 1 and 2B, a part of the conductors 20p, 20q, and 20r remain in the portion of the pixel electrode 191 overlapping the gate insulating layer 140 and the drain electrode 175.

A method of manufacturing such a thin film transistor array panel will be described with reference to FIGS. 17 through 18B and 19A through 31B as well as FIGS. 1 through 16B.

 19A and 19B are cross-sectional views of the thin film transistor array panel of FIG. 17 taken along lines XVIIIa-XVIIIa and XVIIIb-XVIIIb, respectively, and illustrate a first process of manufacturing the thin film transistor array panel, and FIGS. 20A and 20B. Are views in the next steps of FIGS. 19A and 19B, respectively, and FIGS. 21A and 21B are views in the next steps of FIGS. 20A and 20B, respectively.

22, 26 and 28 are layout views at intermediate stages of the method for manufacturing the thin film transistor array panel shown in FIGS. 17 to 18B according to one embodiment of the present invention, respectively, and are arranged in the order of the process. 23A and 23B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 22, taken along the lines XXIIIa-XXIIIa and XXIIIb-XXIIIb, respectively, and FIGS. 24A and 24B illustrate the thin film transistor array panel illustrated in FIG. 22, respectively. Cross-sectional views taken along the lines -XXIIIa and XXIIIb-XXIIIb, which are views in the next steps of FIGS. 23A and 23B, and FIGS. 25A and 25B are views in the next steps of FIGS. 24A and 24B, respectively. 27A and 27B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 26 taken along the lines XXVIIa-XXVIIa and XXVIIb-XXVIIb, respectively. 29A and 29B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 28 taken along the lines XXVIIIIa-XXVIIIIa and XXVIIIIb-XXVIIIIb, respectively, and FIGS. 30A and 30B are respectively taken in the next steps of FIGS. 29A and 29B. 31A and 31B are views in the next steps of FIGS. 30A and 30B, respectively.

In the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of the present invention, the conductors 20p, 20q, and 20r formed on the pixel electrode 191 may be formed using the data line 171 and the drain. It is removed together during the process of forming the electrode 175.

That is, as shown in FIGS. 19A and 19B, unlike in FIGS. 3A and 3B, the portion corresponding to the transflective area SA of the photomask 50 ′, that is, the pixel electrode in FIGS. 3A and 3B is illustrated. The part facing 191 is made into light shielding area BA2.

Then, after irradiating light to the photosensitive film 40 through the photomask 50 ', the exposed conductive layer 120 is etched at once using the remaining photosensitive film 42 as a mask, and then the photosensitive film 42 is again etched. The transparent conductor layer 190 is etched using a mask, and the plurality of gate lines 121 and the etched conductors 20p, 20q, and 20r provided with the gate electrodes 124, as shown in FIGS. 20A to 23A, The pixel electrode 191 under the etched conductors 20p, 20q, and 20r and the transparent conductor 95 under the gate line 121 are formed.

As shown in Figs. 24A to 27B, the gate insulating layer 140, the intrinsic amorphous silicon (a-Si) layer 150 which is not doped with impurities, and the amorphous silicon (n + a-Si) layer doped with impurities ( The plurality of island-like impurity semiconductor layers 63, the plurality of island-like semiconductors 154, and the gate insulating layer 140 are formed by sequentially stacking 160.

Next, as illustrated in FIGS. 28 and 29B, after depositing a conductive layer (not shown) such as a metal, the plurality of data lines 171 and the plurality of data lines including the source electrode 173 may be etched by wet etching or the like. A drain electrode 175 is formed. At this time, using the drain electrode 175 and the gate insulating layer 140 as a mask, the conductors 20p, 20q, and 20r below are also etched. As such, except for the portion overlapping the drain electrode 175 and the gate electrode 140, the portion of the conductors 20p, 20q, and 20r formed on the pixel electrode 191 is removed to remove the pixel electrode 191. Reveal. Next, the island-type ohmic contacts 163 and 165 are formed by removing the exposed impurity semiconductor layer 63 without being covered by the source electrode 173 and the drain electrode 175. Next, as shown in FIGS. 30A to 31B, as shown in FIGS. 15A to 16B, the first and second insulating layers 80 and 320 are sequentially stacked and etched to include a plurality of columnar spacers 321. The insulating pattern 322 and the passivation layer 180 are formed (see FIGS. 17, 18A, and 18B).

In the present embodiment, as shown in FIGS. 1 through 16B, the pixel electrode 191 is formed together with the gate line 121 using one mask, thereby simplifying the manufacturing process and reducing the manufacturing cost. Also. Since the protective film is formed using this spacer without using a separate mask, manufacturing time and cost of the thin film transistor array panel are reduced. In addition, since the pixel electrode is formed under the protective film, the thickness of the protective film can be reduced.

In addition, as described above in the first embodiment, in order to prevent surface damage of the pixel electrode, the gate insulating film or the like formed on the pixel electrode is preferably formed at a low temperature of about 240 ° C to 280 ° C. Since the gate line formed on the electrode acts as a protective member, the surface of the furnace pixel electrode is prevented from being damaged even when a gate insulating film or the like formed on the pixel electrode is formed at a high temperature of about 320 ° C to 360 ° C. Accordingly, surface damage of the pixel electrode does not occur, so that the transmittance of the pixel electrode is reduced and the image quality of the liquid crystal display does not occur.

In the above-described embodiments of the present invention, the gate insulating layer 140 is formed in the horizontal direction along the gate line 121, but may also be formed in the portion where the data line 171 is formed.

As described above, according to the present invention, since the pixel electrode is formed together with the gate line using one mask, the manufacturing process is simplified and the manufacturing cost is reduced.

In addition, since the pixel electrode is formed under the protective film, the thickness of the protective film can be reduced.

When manufacturing a thin film transistor array panel, a protective film is formed without using a mask together with a spacer, and a separate photo etching process for forming the passivation layer is omitted, thereby simplifying the entire process to manufacture a thin film transistor array panel. To reduce.

Furthermore, since the conductive film formed on the pixel electrode is removed when forming the data line and the drain electrode, surface damage of the pixel electrode does not occur even if the gate insulating film or the like formed on the pixel electrode is formed at a high temperature of about 320 ° C to 360 ° C. Do not. Therefore, a decrease in transmittance of the pixel electrode and a deterioration in image quality of the liquid crystal display due to surface damage of the pixel electrode are reduced.

In addition, since the conductive film formed on the pixel electrode is removed when forming the data line and the drain electrode, the etching process is simplified.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (17)

A pixel electrode formed on the substrate, A gate line formed on the substrate, A gate insulating layer formed on the gate line; A semiconductor layer formed on the gate insulating film, A data line and a drain electrode formed on the gate insulating film, and A passivation layer formed on a portion of the data line and the drain electrode. Including, The gate line includes a first film formed of the same material on the same layer as the pixel electrode and a second film formed on the first film. Thin film transistor display panel. A pixel electrode formed on the substrate, A gate line formed on the substrate, A gate insulating layer formed on the gate line; A semiconductor layer formed on the gate insulating film, A data line and a drain electrode formed on the gate insulating film, and A passivation layer formed on a portion of the data line and the drain electrode. Including, The gate line includes a first layer formed of the same material on the same layer as the pixel electrode and a second layer formed on the first layer, And a conductor formed of the same material as the gate line in a portion where the gate insulating layer and the pixel electrode overlap and a portion where the drain electrode and the pixel electrode overlap. Thin film transistor display panel. The method of claim 1 or 2, The pixel electrode is a thin film transistor array panel made of a transparent conductive material. In claim 3, The second film of the gate line is a first layer made of molybdenum (alloy), a second layer formed on the first layer and made of aluminum (alloy), and a third layer formed on the second layer and made of molybdenum (alloy) A thin film transistor array panel comprising a layer. The method of claim 1 or 2, And the gate insulating layer overlaps a portion of an edge of the pixel electrode. The method of claim 1 or 2, The passivation layer is partially overlapped with an edge of an adjacent pixel electrode. The method of claim 1 or 2, The thin film transistor array panel of claim 1, further comprising an insulating pattern having a columnar spacer on the passivation layer. The method of claim 7, wherein The passivation layer has the same planar shape as the insulating pattern. Forming a transparent conductor layer on the substrate, Forming a conductor layer on the transparent conductor layer, Forming a first photoresist film on the conductor layer, Etching the conductor layer using the first photoresist as a mask and using a first etchant; Forming a gate line by etching the transparent conductor layer using the first photoresist as a mask and using a second etchant different from the first etchant; Changing the first photoresist to form a second photoresist; Forming a pixel electrode by removing the conductor layer exposed using the second photoresist layer as a mask and using the first etchant; Forming a gate insulating film on the gate line and the pixel electrode; Forming a semiconductor layer on the gate insulating film, Forming a data line and a drain electrode on the semiconductor layer; Sequentially stacking first and second insulating layers on the data line and the drain electrode; Exposing the second insulating layer to form an insulating pattern having a spacer; and Etching the first insulating layer using the insulating pattern as a mask to form a protective film Method of manufacturing a thin film transistor array panel comprising a. Forming a transparent conductor layer on the substrate, Forming a first conductor layer on the transparent conductor layer, Forming a photoresist film on the first conductor layer, Etching the first conductor layer using the photoresist as a mask and using a first etchant, Forming a gate pattern including a gate line by etching the transparent conductor layer by using the photoresist as a mask and using a second etchant different from the first etchant; Forming a gate insulating film on the gate pattern; Forming a semiconductor layer on the gate insulating film, Forming a second conductor layer on the semiconductor layer, Etching the second conductor layer and the exposed gate pattern to form a data line, a drain electrode, and a pixel electrode; Sequentially stacking first and second insulating layers on the data line and drain electrodes and the pixel electrode; Exposing the second insulating layer to form an insulating pattern having a spacer; and Etching the first insulating layer using the insulating pattern as a mask to form a protective film Method of manufacturing a thin film transistor array panel comprising a. The method of claim 9 or 10, The first etchant is an integrated etchant. The method of claim 9 or 10, The second etchant is a pixel integrated etchant. In claim 9, The first photoresist film is formed using a photomask having a light blocking area, a transflective area, and a light transmitting area. In claim 9, The forming of the second photoresist film includes an ashing process. In claim 10, And the photosensitive film is formed using a photomask having a light shielding region and a light transmitting region. Forming a transparent conductor layer on the substrate, Forming a conductor layer on the transparent conductor layer, Forming a first photoresist film on the conductor layer, Forming a gate line by etching the conductor layer and the transparent conductor layer using the first photoresist layer as a mask and using one etchant; Changing the first photoresist to form a second photoresist; Forming a pixel electrode by using the second photoresist film as a mask and removing the exposed conductor layer; Forming a gate insulating film on the gate line and the pixel electrode; Forming a semiconductor layer on the gate insulating film, Forming a data line and a drain electrode on the semiconductor layer; Sequentially stacking first and second insulating layers on the data line and the drain electrode; Exposing the second insulating layer to form an insulating pattern having a spacer; and Etching the first insulating layer using the insulating pattern as a mask to form a protective film Method of manufacturing a thin film transistor array panel comprising a. Forming a transparent conductor layer on the substrate, Forming a first conductor layer on the transparent conductor layer, Forming a photoresist film on the first conductor layer, Forming a gate pattern including a gate line by etching the first conductor layer and the transparent conductor layer by using the photoresist as a mask and using an etchant; Forming a gate insulating film on the gate pattern; Forming a semiconductor layer on the gate insulating film, Forming a second conductor layer on the semiconductor layer, Etching the second conductor layer and the exposed gate pattern to form a data line, a drain electrode, and a pixel electrode; Sequentially stacking first and second insulating layers on the data line, the drain electrode, and the pixel electrode; Exposing the second insulating layer to form an insulating pattern having a spacer; and Etching the first insulating layer using the insulating pattern as a mask to form a protective film Method of manufacturing a thin film transistor array panel comprising a.

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