KR20070023598A - Semiconductor Memory Systems and Semiconductor Memory Chips - Google Patents

Abstract

The present invention relates to a semiconductor memory system and a semiconductor memory chip in which data, command and address signals are serially transmitted between the memory controller and the semiconductor memory chip in the form of signal frames in accordance with a predetermined protocol. On the receiving signal path in the semiconductor memory chip 1, a frame decoder 3 for decoding a signal frame is disposed following the receiving interface device 2, and includes a cell array 10 between the frame decoder and the memory core 5. An intermediate storage device 4 is arranged, the array comprising a plurality of memory cells and addressing and selector circuits 11-14, instructions provided by a memory controller decoded by the frame decoder 3 and / or Alternatively, an address signal from a write signal frame is applied to this circuit to address the cell array 10 and select write data to be written to the cell array and data to be read therefrom.

Description

Semiconductor memory system and semiconductor memory chip {SEMICONDUCTOR MEMORY SYSTEM AND SEMICONDUCTOR MEMORY CHIP}

1 schematically illustrates a functional block diagram of a variation of one embodiment of a semiconductor memory chip according to the present invention, with reference to which will be described the core purpose and functional features.

2 graphically illustrates a state diagram applicable to a temporary storage device used in the present invention.

Explanation of symbols for the main parts of the drawings

1: semiconductor memory chip 2: receiving interface device

3: frame decoder 4: temporary storage device

5: memory core

10: cell array of temporary storage 4

11: address pointer 12: frame counter

13: Temporary save record selector 14: Temporary save read selector

WD1, WD2, WD3: Record Data Unit

DM: Data Masking Bits and Signal Frames

WR1, WR2, WR3: Record Signal Frame

WR-RET: read request from temporary storage

Z1-Z7: Status

The present invention relates to a semiconductor memory system and a semiconductor memory chip, and is described in each of claims 1 and 8, which are independent claims in the claims. Such semiconductor memory systems and semiconductor memory chips are, for example, conventional DRAM or DDR-DRAM semiconductor memory systems and memory chips.

In conventional DRAM semiconductor memory systems and memory chips, data, command and address signals to and from memory controllers and / or other semiconductor memory chips are not transmitted in the form of signal frames, but in parallel rather than serially. This parallel transfer, for example write data, commands and addresses, can be accomplished by separate data, command and address signal buses from the memory controller to one or more DRAM memory chips.

In future semiconductor memory systems, such as DRAM memory systems and memory chips, data, command and address signals are transmitted at very high rates as serial signal streams in the form of signal frames conforming to a predetermined protocol.

In this evolving semiconductor memory, there is a frame decoder between the memory core and the transmit and receive interface device, which is for decoding signal frames received from the receiving interface device and for later sending data and commands to the memory core. As can also be applied to instruction units belonging to each other, such a semiconductor memory chip is a temporary storage device because the write data units belonging to each other can be included in not only a single signal frame but also a plurality of consecutively transmitted signal frames according to a protocol. The temporary storage device temporarily stores a plurality of data and / or instruction units connected to the frame decoder and the memory device and decoded by the frame decoder, so that the write data unit for the memory core of such an advanced semiconductor memory chip and It provides the flexibility that is absolutely necessary in the transmission of the command unit.

Therefore, an object of the present invention is to temporarily store a large number of write data and / or command units decoded by the frame decoder clock-synchronously with the frame decoder to store data and / or command units that are not critical in time. Memory cores, which are insignificant with respect, also specify a general semiconductor memory system and a semiconductor memory chip that read them.

This object is achieved according to the claims.

According to a first aspect, the present invention provides a semiconductor memory system which achieves the above object by a memory controller and at least one memory chip connected to the memory controller via data, command, and address bus lines. The memory chip includes a memory core and a transmit and receive interface device, which transmits and receives data, command and address signals to the memory controller and / or other similar semiconductor memory chip, respectively, wherein the semiconductor memory system is pre-determined. A data decoder configured to transmit data, command and address signals as a serial signal stream in the form of a signal frame conforming to the protocol, wherein at least one semiconductor memory chip comprises a frame decoder disposed between the receiving interface device and the memory, the decoder having a receiving interface Received by the device Configured to decode a signal frame; and temporary storage for temporarily storing a plurality of write data and / or instruction units decoded by the frame decoder, the apparatus being disposed on a receive path between the frame decoder and the memory core and multiple A cell array comprising addressing and selector circuits to which the address signal decoded by the frame decoder is applied from a memory address and a signal frame supplied by the memory controller, addressing the cell array, and selecting read / write for the cell array. -Also includes.

The addressing and selector circuit has an address pointer and a frame counter.

According to a second aspect, the present invention also provides a semiconductor memory chip which achieves the above object, comprising a memory core and a transmit and receive interface device, which transmits data, command and address signals to the memory controller and / or other similar devices. Each transmitting and receiving to a semiconductor memory chip, the semiconductor memory system being configured to transmit data, command and address signals as a serial signal stream in the form of signal frames conforming to a predetermined protocol, the at least one semiconductor memory The chip comprises a frame decoder disposed between the receiving interface device and the memory, the decoder configured to decode a signal frame received by the receiving interface device, and a plurality of write data and / or command units decoded by the frame decoder. Temporarily save me temporarily Chapter apparatus-The apparatus includes addressing and selector circuitry disposed on a receive path between a frame decoder and a memory core and to which a plurality of memory addresses and address signals decoded by the frame decoder from a signal frame supplied by the memory controller are applied. Taking a cell array, addressing the cell array, and performing read / write selections on the cell array.

In this apparatus, the addressing and selector circuit has an address pointer and a frame counter.

The temporary storage device and its addressing and selector circuitry preferably operate clock-synchronously with the frame decoder in the semiconductor memory system and chip according to the invention.

In addition, each addressable memory cell of the cell array of temporary storage device is intended for continuous or disturbed multiple access when command and / or write data is transmitted in multiple clock cycles in a semiconductor memory system and chip according to the present invention. It is desirable to subdivide the number into individual sections.

In a preferred embodiment, the addressing and selector circuitry of the temporary storage device also has a temporary storage write selector, which stores a temporary storage write selector driven by a write selection control signal formed from an address pointer and an output signal of the frame counter. Has at its input and its output before the memory core has a temporary storage read selector driven by a read select control signal from a read command frame decoded by the frame decoder.

As mentioned above, the temporary storage device and its addressing and selector circuit can be configured to temporarily store both a plurality of write data units and a plurality of command units according to the present invention.

However, in an alternative embodiment, the temporary storage device and its addressing and selector circuit can be configured to temporarily store only write data.

Preferably, when the predetermined protocol of the semiconductor memory system is also set to transmit a temporary approximation and write data masking bits of individual data allocations to individual write data units in the command / write data signal stream, the temporary storage device and its addressing. The selector circuit may in this case temporarily store its associated masking bits in a separate section of each addressable memory cell of the cell array in each case separately from the temporary storage of a plurality of write data units.

Since the temporary storage device and its addressing and selector circuitry proposed herein are divided into multiple accesses that are contiguous or interrupted when the command and / or write data is transmitted in multiple clock cycles per addressable memory cell, logic complexity It has the advantage of reducing and reducing the area of the semiconductor memory chip according to the present invention. In addition, the use of such temporary storage and its addressing and selector circuitry between the frame decoder and the memory core as proposed herein increases flexibility in transferring write data and / or commands from the frame decoder to memory.

In a preferred embodiment of the present specification, the address signal provided to the addressing and selector circuit of the temporary storage device and addressing the cell array to be decoded by the frame decoder comes from a signal frame transmitted by the memory controller, i.e., the memory controller is By finally determining the address for the temporary storage device, the complexity of the logic for generating the address of the temporary storage device is reduced and is less time consuming than any other possible solution for generating an address in the temporary storage device itself.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The above and other objects and advantages of the semiconductor memory system and chip according to the present invention will be described in more detail with reference to the accompanying drawings.

The attached FIG. 1 schematically shows a receive path section of a semiconductor memory chip 1 according to the invention between the simply indicated receive interface device 2 and the memory core 5. Directly followed by a frame decoder 3, indicated as a functional block, to the receiving interface device 2 of the semiconductor memory chip 1 according to the invention, which is the write, read, system and other instructions provided by the receiving interface device 2. And decoding signal frames and masking bits relating to write and read data, and converting the decoded data into a parallel form. The temporary storage device 4 according to this preferred embodiment is configured to temporarily store a plurality of write data and write data masking bits decoded by the frame decoder 3, and the frame decoder 3 and the memory core 5. Located on a receive path between the plurality of addressable memory cells and addressing and selector circuitry provided by a memory controller (not shown) and to which address signals from a signal frame decoded by the frame decoder 3 are applied. Which has an address pointer 11, a write selector 13 and a read selector 14 for addressing and selecting write data and masking bits to be written to and read from the cell array 10. Has The write selector 13 is disposed at the input of the cell array 10 and driven by the output signal of the address pointer 11 and the frame counter 12 to write the write data and masking bits to the cell array 10. The read selector 14 is driven by a read select control signal " address / enable WR-RET " from a read command frame which is disposed at the output of the cell array 10 and decoded by the frame decoder.

In this embodiment, it should be noted that the temporary storage device is configured only for temporarily storing the write data units WD1, WD2, WD3 and the masking bits DM assigned thereto.

Due to the predetermined protocol, it is assumed that the write data units are distributed over a number of write signal frames that do not necessarily follow each other. The frame decoder 3 decodes the incoming signal frames WR1, WR2, WR3, DM into the control signal "receive frame" and supplies them to the frame counter 12 of the temporary storage device 4 to count the frames. The frame decoder 3 also decodes the recording data units and masking bits received in the frame, which are supplied by the frame decoder 3 to the record selector 13. In the exemplary embodiment, the frame decoder 3 decodes the temporary storage write address supplied to the address pointer 11 from the frame WR1 or the DM frame. The write selector 13 is eventually driven by the output signals from the address point 11 and the frame counter 12 to selectively write the write data units WD1, WD2 and WD3 and the write data masking bits. If the address for the temporary storage device 4 has been sent by the memory controller of the signal frame WR1, it does not need to be sent in the signal frames WR2, WR3 and DM.

The recording address will be described more precisely from the arrangement. 1. If an address is fully described before the start of the next address, this address must also be suitably transmitted by the last frame of the previous write cycle of the first frame or another address. 2. If different addresses are superimposed and described, address information must be supplied to each of the frames.

The frame decoder 3 also decodes the instructions from the temporary storage device 4 from the signal frame "WR-RET" and reads write data units and masking bits from the cell array 10 and reads them into the memory core 5. Supply. For this purpose, the temporary storage read selector 14 disposed at the output of the cell array 10 receives the read address decoded from the signal frame WR-RET from the frame decoder 3, thereby receiving the cell array 10 and the enable signal. Read it. The cell array 10 itself is divided into a plurality of sections corresponding to a plurality of write data frames WR1, WR2, WR3 and masking bit frames for each addressable memory cell. The cell array 10 is always accessed in the order of WR1-WR2-WR3-DM. The signal frame may be interrupted by a blank frame or a read request for a different address.

Read and write access to the temporary storage device 4 may be performed by one bidirectional bus system or two unidirectional buses. In the embodiment shown in FIG. 1, two unidirectional buses are implemented in each case from the frame decoder 3 to the temporary storage device 4 and from the temporary storage device 4 to the memory core 5.

Fig. 2 shows a state diagram, which has seven states, Z1-Z7, for the temporary storage device 4 shown in Fig. 1 in a semiconductor memory chip according to the invention. Hereinafter, the operation of the temporary storage device 4 together with the frame decoder 3 and the memory core 5 will be described with reference to FIGS. 1 and 2.

Z1: Initially, the entry and address pointer 11 of the cell array 10 and the frame counter 12 of the temporary storage device 4 are set to zero. Temporary store write selector 13 and temporary store read selector 14 are each secured or blocked.

Z2: Waits for the next operation of the temporary storage device 4, that is, writing the write data and the masking bits to the previous one or reading the write data or the masking bits by the WR-RET.

Z3: Following decoding of the WR1 signal frame, the frame decoder 3 decodes the address of the cell array 10 from the frame bits and sets the address pointer 11 accordingly. The frame counter 12 is set to zero. In the next clock cycle, the write data WD1 may be written to the corresponding address of the cell array 10 via the temporary storage write selector 13. If the DM signal frame is only one option, the DM selection of the corresponding address of the cell array 10 is set to zero.

Z4: While accessing the WR2 signal frame, the frame counter 12 is incremented by 1 only because the address of the cell array 10 is already available from the decoding of the WR1 signal frame. In the next clock period, the write data WD2 is written to the second section of the corresponding address (eg 0) of the cell array 10 via the temporary storage write selector 13.

Z5: While accessing the WR3 signal frame, the frame counter is incremented by only 1 since the address of the cell array 10 is already available from the decoding of the WR1 signal frame. In the next clock period, the write data WD3 is written into the cell array 10 in the third section of the corresponding address (eg 0) via the temporary storage write selector 13.

Z6: During access to the DM signal frame, the frame counter 12 is incremented by only 1 since the address of the cell array 10 is already available from the decoding of the WR1 signal frame. In the next clock period, the data masking bit DM is written to the DM section of the corresponding address (eg 0) via the temporary storage write selector 13. If no DM signal frame occurs, it does not matter since the DM section has been set to zero before any case.

Z7: Read commands from the temporary storage device 4 or its cell array 10 can each arrive using a temporary frame. Simultaneous reading of the cell array 10 is possible even during a write data sequence (obstructed by such a read signal frame) as long as the read request is directed to another address of the cell array 10. When such a read request occurs, the applicable address of the cell array 10 is decoded from the read signal frame and, in the next clock cycle, the write data WD1, WD2, WD3 and possibly the write data masking bits DM are now in It is read from the previously decoded address of the cell array 10 via the enabled temporary storage read selector 14 and sent to the memory core 5. In the example shown in FIG. 1, 128 write data bits and 16 data masking (DM) bits are read from the cell array 10 via the temporary storage read selector 14 and the memory core by this read command WR-RET. Suppose it is sent to (5).

In the above-described solution, the read and write addresses for the cell array 10 of the temporary storage device 4 are also supplied in each case by the memory controller of the read signal frame and the write signal frame WR-RET, so that Fig. 1 The temporary storage device 4 of the semiconductor memory chip according to the present invention shown in FIG. 2 has the following advantages when compared with other kinds of solutions in which the read and write addresses for the cell array are calculated in each case in the temporary storage device. Have

Reduction of the functional block for address calculation for subsequent write data signal frames and reduction of the functional block for recalculation of the address of the cell array 10 for the write data signal frame following the read request WR-RET from the cell array 10; .

-Reduced area of semiconductor memory chips due to the reduction of additional function blocks.

The same period for all address determinations for the cell array

-Time overlap prevention for frame sequence "WR-RET" → "WRD1".

1 and 2, the preferred solution of addressing write data and data masking bits for writing to the cell array 10 and addressing the read data and data masking bits from the data masking bits for additional functional complexity. It avoids the extra hardware expense of the semiconductor memory chip, in particular the address information addressing the cell array 10 already exists in the memory controller, and in any case a free position is used to transfer this address of the WR1 data signal frame. Because it is possible.

1 and 2 and the foregoing, only to temporarily store the write data units WD1-WD3 and in each case their associated masking bits DM of the individual sections of each addressable memory cell of the cell array 10. Although the temporary storage device 4 arranged is described, the basic principle of the present invention is that in addition to the recording data unit and the masking bit, the temporary storage device and the recording data unit and the masking bit which are also temporarily stored also are decoded from the corresponding command signal frame. Instead, it is similarly applicable to a temporary storage device in which only a command unit decoded from a command signal frame is temporarily stored.

The foregoing description describes a semiconductor memory chip according to the present invention, in which case the data, command and address signals in each case with a memory controller and / or other similar semiconductor memory chip via the memory core and in each case the data, command and address bus lines. And a semiconductor memory chip and a memory controller configured to transmit data, command and address signals as serial signal streams in the form of signal frames conforming to a predetermined protocol. The semiconductor memory chip also includes the following apparatus.

A frame decoder which decodes the signal frame received by the receiving interface device and is arranged between the receiving interface device and the memory

An address signal disposed on the receive path between the frame decoder and the memory core and having a cell array comprising a plurality of memory addresses and addressing and selector circuitry, the address signal being decoded by a signal frame supplied by the memory controller from the frame decoder And a temporary storage device for temporarily storing a plurality of write data and / or instruction units decoded by a frame decoder for addressing the cell array and for reading / writing selection of the cell array.

In this case, the addressing and selector circuit has an addressing pointer and a frame counter.

It will be apparent to those skilled in the art that the foregoing features are also applicable to a semiconductor memory system having a memory controller and at least one semiconductor memory chip connected to the memory controller via data, command and address bus lines in accordance with the present invention. The chip has a transmit and receive interface device for transmitting and receiving data, command and address signals in each case to a memory controller and / or other similar semiconductor memory chip via a memory core and in each case data, command and address bus lines, The semiconductor memory chip and the memory controller are configured to transmit data, command and address signals as serial signal streams in the form of signal frames conforming to a predetermined protocol. The semiconductor memory chip also includes the following apparatus.

A frame decoder which decodes the signal frame received by the receiving interface device and is arranged between the receiving interface device and the memory

An address signal disposed on the receive path between the frame decoder and the memory core and having a cell array comprising a plurality of memory addresses and addressing and selector circuitry, the address signal being decoded by a signal frame supplied by the memory controller from the frame decoder And a temporary storage device for temporarily storing a plurality of write data and / or instruction units decoded by a frame decoder for addressing the cell array and for reading / writing selection of the cell array.

According to the present invention, there is provided a semiconductor memory system and a semiconductor memory chip which reduce the logic complexity and reduce the area of the semiconductor memory chip.

Claims (14)

A memory controller, A semiconductor memory system having at least one semiconductor memory chip 1 connected to the memory controller via data, command and address bus lines, The memory chip, A memory core 5 and a transmit and receive interface device 2, wherein the device transmits and receives data, command and address signals to the memory controller and / or other similar semiconductor memory chips, respectively; The semiconductor memory system is configured to transmit the data, command and address signals as a serial signal stream in the form of a signal frame conforming to a predetermined protocol, The at least one semiconductor memory chip 1, A frame decoder 3 disposed between the receiving interface device 2 and the memory 5, the decoder being configured to decode a signal frame received by the receiving interface device; A temporary storage device 4 for temporarily storing a plurality of recording data and / or command units decoded by the frame decoder 3, wherein the device 4 comprises the frame decoder 3 and the memory core 5; And addressing and selector circuits 11-14 disposed on a receiving path therebetween and to which a plurality of memory addresses and an address signal decoded by the frame decoder 3 from a signal frame supplied by the memory controller are applied. And a cell array 10 to address the cell array 10 and to perform read / write selections on the cell array. Semiconductor memory system. The method of claim 1, The addressing and selector circuit has an address pointer 11 and a frame counter 12. Semiconductor memory system. The method according to claim 1 or 2, The temporary storage device 4 and its addressing and selector circuits 11-14 operate clock-synchronously with the frame decoder 3. Semiconductor memory system. The method according to claim 1 or 2, The cell array 10 of the temporary storage device 4 is subdivided into a number of separate sections for multiple accesses that are continuous or interrupted when command and / or write data is supplied to each memory cell addressable in multiple clock cycles. Divided Semiconductor memory system. The method according to claim 1 or 2, The addressing and selector circuit 11-14 is also A temporary storage write selector 13 driven by a write selection control signal formed from the address pointer 11 and an output signal of the frame counter 12, at the input of the cell array 10, At its output before the memory core 5, it has a temporary storage read selector 14 driven by a read select control signal from a read command frame decoded by the frame decoder 3. Semiconductor memory system. The method according to claim 1 or 2, The temporary storage device 4, its cell array 10, and the addressing and selector circuits 11-14 are configured only for temporarily storing write data units. Semiconductor memory system. The method according to claim 1 or 2, The predetermined protocol and the semiconductor memory system are further configured to transmit write data masking bits upon temporal approximation to individual write data units in the command / write data signal stream and upon allocation of individual data, The temporary storage device 4 and its addressing and selector circuits 11-14 are configured to temporarily store write data units and their associated masking bits in each case in separate sections of each addressable memory of the cell array 10. Composed only Semiconductor memory system. A memory core 5, A semiconductor memory chip comprising a transmit and receive interface device 2 which transmits and receives data, command and address signals in each case via the data, command and address lines in each case to a memory controller and / or other similar semiconductor memory chip. As The semiconductor memory chip 1 is set to transmit the data, command and address signals as a serial signal stream in the form of a signal frame in conformity with a predetermined protocol, A frame decoder 3 disposed between the receiving interface device 2 and the memory 5, wherein the frame decoder is configured to decode a signal frame received by the receiving interface device; A temporary storage device 4 for temporarily storing a plurality of recording data and / or command units decoded by the frame decoder 3, wherein the temporary storage device is between the frame decoder 3 and the memory core 5; And addressing and selector circuits 11-14, which are disposed on a receiving path of the PDU and are supplied with a plurality of memory addresses and an address signal from the frame decoder 3 decoded by a signal frame provided by the memory controller. And having a cell array 10 addressing the cell array 10 and selecting data from the cell array. Semiconductor memory chip. The method of claim 8, The addressing and selector circuit has an address pointer 11 and a frame counter 12. Semiconductor memory chip. The method according to claim 8 or 9, The temporary storage device 4 and its addressing and selector circuits 11-14 operate clock-synchronously with the frame decoder 3. Semiconductor memory chip. The method according to claim 8 or 9, The cell array 10 of the temporary storage device 4 is subdivided into a number of individual sections for multiple accesses that are continuous or interrupted when command and / or write data is provided per memory cell addressable in multiple clock cycles. felled Semiconductor memory chip. The method according to claim 8 or 9, The addressing and selector circuit 11-14 is also A temporary storage write selector 13 driven by a write selection control signal formed from the address pointer 11 and an output signal of the frame counter 12, at the input of the cell array 10, At its output before the memory core 5, it has a temporary storage read selector 14 driven by a read select control signal from a read command frame decoded by the frame decoder 3. Semiconductor memory chip. The method according to claim 8 or 9, The temporary storage device 4, its cell array 10, and the addressing and selector circuits 11-14 are configured only for temporarily storing write data units. Semiconductor memory chip. The method according to claim 8 or 9, The predetermined protocol and the semiconductor memory system are further configured to transmit write data masking bits upon temporal approximation to individual write data units in the command / write data signal stream and upon allocation of individual data, The temporary storage device 4 and its addressing and selector circuits 11-14 are configured to temporarily store write data units and their associated masking bits in each case in separate sections of each addressable memory of the cell array 10. Composed only Semiconductor memory chip.

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