KR20070017557A - Printed wiring board and its manufacturing method - Google Patents

Abstract

In the printed wiring board 10, the upper electrode connecting portion 52 penetrates through the condenser portion 40 in the vertical direction without the upper electrode connecting portion first portion 52a contacting the condenser portion 40. The upper electrode connecting portion is connected to the upper electrode 42 from the upper electrode connecting portion second portion 52b via the upper electrode connecting portion third portion 52c formed above. The lower electrode connecting portion 51 does not contact the upper electrode 42 of the condenser portion 40 but penetrates the condenser portion 40 in the vertical direction so as to contact the lower electrode 41. For this reason, in the flow which builds up, it has a structure which sandwiched the high dielectric layer with two metal foils, and after covering the whole surface with the high dielectric capacitor sheet used later as the capacitor part 40, the upper electrode connection part 52 is carried out. And the lower electrode connecting portion 51 can be formed.

Capacitor, High Dielectric Layer, Insulation Layer, Wiring Board

Description

Printed wiring board and its manufacturing method {PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board and a method for manufacturing the same, and more particularly, to a printed wiring board for mounting a semiconductor device having a structure in which a high dielectric layer made of ceramics is sandwiched between an upper electrode and a lower electrode, and a manufacturing method thereof. will be.

Conventionally, the structure of the printed wiring board provided with the buildup part comprised by electrically connecting several wiring patterns laminated | stacked through the insulating layer between via via holes in an insulating layer is proposed. For example, in this type of printed wiring board, when the semiconductor element to be mounted is turned on and off at high speed, switching noise may occur and the potential of the power supply line may be lowered instantaneously. It is proposed to connect and decouple the condenser section between the and ground lines.

For example, Japanese Patent Laid-Open No. 2004-87971 proposes to incorporate a thin film capacitor portion in a printed wiring board (see FIG. 21). In this publication, a laminate 106 in which a release layer 101, an electrode layer 102, a dielectric layer 103, an electrode layer 104, and an insulating layer 105 are laminated in this order on a silicon wafer 100 is prepared. 21 (a) and two field vias 107 and 108 are formed in the insulating layer 105, and then the substrate 110 having the ground electrode 111 and the power supply electrode 112 is separated. The laminate 106 is turned upside down so that the field vias 107, 108 face each electrode 111, 112 of the substrate 110, and are bonded to each other (see Fig. 21 (b)). Thereafter, the condenser portion 113 (the portion consisting of three layers of the electrode layer 102, the dielectric layer 103, and the electrode layer 104) is patterned into a predetermined shape (see Fig. 21 (c)), and the condenser portion 113 ), A polyimide layer 114 is formed, a hole is formed from the upper surface of the polyimide layer 114 to the electrode layer 102, and the hole is filled with a conductive paste to form a field via 115. Similarly, after making a hole from the upper surface of the polyimide layer 114 to the field via 108, the hole is filled with a conductive paste to form the field via 116 (see Fig. 21 (d)). The field vias 115 and 116 are connected by the outer layer pattern 117. Thereby, electric charge is supplied from the power supply electrode 112 to the electrode layer 102 of the capacitor | condenser part 113. FIG.

Disclosure of the Invention

However, in the above-described publication, since the electrode layer 104 of the condenser portion 113 is connected to the ground electrode 111 through the field via 107 extending immediately below, the condenser portion 113 in the flow of the buildup. 21 (a) to 21 (b), the laminate 106 was fabricated separately from the flow of the buildup, and then the substrate 106 was turned upside down to form the electrodes 106 and 112 of the substrate 110. And the field vias 107, 108 need to be faced with each other, which leads to a complicated manufacturing process.

This invention is made | formed in view of such a subject, and one object of this invention is to provide the printed wiring board which can form a capacitor part in the flow of a buildup. Another object of the present invention is to provide a method suitable for producing such a printed wiring board.

The present invention has adopted the following means to achieve at least some of the above described objects.

The printed wiring board of the present invention

A printed wiring board in which a semiconductor element is mounted by incorporating a capacitor portion having a structure in which a high dielectric layer made of ceramics is sandwiched between an upper electrode and a lower electrode.

An upper electrode connecting portion electrically connected to the upper electrode of the condenser portion through a conductor layer formed above the condenser portion without going into contact with the upper electrode or the lower electrode of the condenser portion in an up and down direction;

Lower electrode connecting portion penetrating the condenser part in the vertical direction so as to contact the lower electrode without contacting the upper electrode of the condenser part.

It is equipped with.

In this printed wiring board, the upper electrode connecting portion connected to the upper electrode of the condenser portion is connected to the upper electrode via a conductor layer formed above the condenser portion through the condenser portion in the vertical direction without contacting the condenser portion. The lower electrode connecting portion connected to the lower electrode of the condenser portion is not in contact with the upper electrode of the condenser portion but in contact with the lower electrode. For this reason, in the flow which builds up, it has a structure which sandwiched the high dielectric layer with two metal foils, and even after covering the whole surface with the high dielectric capacitor sheet used later as a capacitor part, an upper electrode connection part or a lower electrode connection part can be formed. Can be. Or in the flow of buildup, after laminating | stacking metal foil, the high dielectric layer made from ceramics, and metal foil so that the whole surface may be covered in this order, you may form an upper electrode connection part or a lower electrode connection part. Thus, according to the printed wiring board of this invention, a capacitor | condenser part can be formed in the flow of a buildup.

In addition, in this specification, although it may express as "up | on" or "lower | bottom", since this is only expressing the relative positional relationship conveniently, you may change upper and lower, or may substitute upper and lower sides for example, for example.

In the printed wiring board of the present invention, the capacitor portion is manufactured separately by sandwiching the high dielectric layer between the upper electrode and the lower electrode, and is formed using a high dielectric capacitor sheet having a size covering the entire plate surface. desirable. In general, since printed wiring boards are often built up at a temperature of 200 ° C. or lower, it is difficult to calcinate the high-k dielectric material at a high temperature (for example, 600 to 950 ° C.) to form ceramics in the flow of building up. It is preferable to fire the high dielectric material separately at a high temperature to make a high dielectric layer made of ceramics.

In the printed wiring board of the present invention, the upper electrode connecting portion is electrically connected to the power terminal or the ground terminal of the semiconductor element, and the lower electrode connecting portion is electrically connected to the ground terminal or the power terminal of the semiconductor element. desirable. In this case, even if the on-off frequency of a semiconductor element is high in several GHz-several tens of GHz (for example, 3 GHz-20 GHz), even if it is easy to produce the instantaneous fall of electric potential, a sufficient decoupling effect will be shown. In this aspect, the upper electrode connecting portion is electrically connected to a power supply conductor or a grounding conductor at a lower end portion of the upper electrode connecting portion that penetrates in the vertical direction, and the lower electrode connecting portion is connected to a ground terminal or a power supply terminal of the semiconductor element. It is preferable that the lower end of the portion which is electrically connected and penetrates the condenser part in the vertical direction is electrically connected to the grounding conductor or the power supply terminal.

In the printed wiring board of the present invention, the high dielectric layer includes barium titanate (BaTiO ₃ ), strontium titanate (SrTiO ₃ ), tantalum oxide (TaO ₃ , Ta ₂ O ₅ ), lead zirconate titanate (PZT), lanthanum zirconate titanate A raw material containing one or more metal oxides selected from the group consisting of lead (PLZT), niobium zirconate zirconate (PNZT), calcium lead zirconate titanate (PCZT), and lead strontium zirconate titanate (PSZT) It is preferable to produce by baking. Since the dielectric constant is high, the capacitance of the capacitor portion is increased, and a sufficient decoupling effect is easily obtained.

In the printed wiring board of the present invention, it is preferable that the upper electrode and the lower electrode are formed as a beta pattern. In this case, the area of the upper electrode and the lower electrode of the condenser portion can be increased, so that the capacitance of the condenser portion is increased. Moreover, although each beta pattern is preferably formed in almost the whole surface of the board surface of a wiring board, it may be formed in part rather than almost the whole surface.

In the printed wiring board of the present invention, it is preferable that the capacitor portion is set to a distance at which the distance between the upper electrode and the lower electrode is 10 占 퐉 or less and is not substantially shorted. In this case, since the distance between the electrodes of a capacitor | condenser part is small enough, the capacitance of this capacitor | condenser part can be enlarged.

The manufacturing method of the printed wiring board of this invention is

(a) adhering a high dielectric capacitor sheet, which is separately manufactured, having a structure in which a high dielectric layer made of ceramics is sandwiched between two metal foils, on a first electrical insulating layer;

(b) forming an upper electrode sheet through hole and a lower electrode sheet through hole penetrating the high dielectric capacitor sheet in an up and down direction;

(c) forming a second electrical insulating layer filling the both sheet through holes and covering the upper surface of the high dielectric capacitor sheet;

(d) a first hole for connecting the upper electrode which is drilled from the second electrical insulating layer to the upper electrode, and is drilled from directly above the sheet through hole for the upper electrode of the second electrical insulating layer to the first electrical insulating layer, The second hole for connecting the upper electrode where all of the upper electrode, the high-k dielectric layer and the lower electrode are not exposed to the inner wall, and the first through-hole of the lower electrode sheet through hole of the second electrical insulating layer; A step of forming a hole for connecting the lower electrode which is drilled up to an electrical insulation layer and the lower electrode is exposed to the inner wall without the upper electrode being exposed to the inner wall;

(e) After filling the first hole for connecting the upper electrode and the second hole for connecting the upper electrode with a conductive material, the both are connected from above the second insulating layer to form an upper electrode connecting portion, And filling the lower electrode connection holes to form the lower electrode connection portion.

In the manufacturing method of this printed wiring board, after attaching a high dielectric capacitor sheet on a 1st electrical insulation layer, the sheet through hole for upper electrodes and the sheet through hole for lower electrodes are formed from this high dielectric capacitor sheet, and each sheet Forming a second electrical insulating layer filling the through hole and covering the upper surface of the high dielectric capacitor sheet, and forming the first and second holes for connecting the upper electrodes and the holes for connecting the lower electrodes from the second electrical insulating layer; The first and second holes for the upper electrode connection are filled with the conductor material, both are connected to the upper electrode connection part, and the lower electrode connection hole is filled with the conductor material to be the lower electrode connection part. Finally, a printed wiring board incorporating a capacitor portion having a structure in which the high dielectric layer is sandwiched between the upper electrode and the lower electrode is obtained. Thus, in the flow of building up, even after covering the whole surface with the high dielectric capacitor sheet, the upper electrode connection part or the lower electrode connection part can be formed.

In the manufacturing method of the printed wiring board of this invention, in the process of said (b), when forming the said sheet | seat through-hole for the said lower electrode, the hole diameter of the part which passes through the said upper electrode of the part which passes through the said lower electrode It is preferable to form so that it may become larger than a hole diameter. This makes it easy to expose the lower electrode without exposing the upper electrode to the inner wall of the lower electrode connecting hole when forming the lower electrode connection hole in the step (d) through the step (c). Can be implemented. In addition, such a lower electrode sheet through-hole removes only a predetermined area for the upper electrode, for example, by etching, and then removes only the area smaller than the predetermined area for etching the high-k dielectric layer and lower electrode present in the predetermined area. It can form by doing this.

In the manufacturing method of the printed wiring board of this invention, in the process of said (d), the said 2nd hole for upper electrode connection is made into the said 1st hole from directly above the said through electrode sheet through hole among the said 2nd electrical insulation layers. A hole for a power supply or a ground conductor in the electrical insulation layer, and the hole for connecting the lower electrode is connected to a ground terminal in the first electrical insulation layer directly above the sheet through hole for the lower electrode; It is preferable to drill the power supply conductor. In addition, after the step (e), the upper electrode connecting portion is electrically connected to a power terminal or a ground terminal of a semiconductor element mounted on the printed wiring board, and the lower electrode connecting portion is a ground terminal or a power supply terminal of the semiconductor element. It is preferable to electrically connect to a terminal. In this way, even if the on-off frequency of a semiconductor element is high in several GHz-several tens of GHz, even if it is easy to produce the instantaneous fall of electric potential, a sufficient decoupling effect will be shown.

In the method of manufacturing a printed wiring board of the present invention, the high dielectric layer includes barium titanate (BaTiO ₃ ), strontium titanate (SrTiO ₃ ), tantalum oxide (TaO ₃ , Ta ₂ O ₅ ), lead zirconate titanate (PZT), titanic acid It contains one or more metal oxides selected from the group consisting of lanthanum lead zirconate (PLZT), niobium zirconate titanate (PNZT), calcium lead zirconate titanate (PCZT), and strontium lead zirconate titanate (PSZT). It is preferable to bake and produce the raw material formed. Since the dielectric constant is high, the capacitance of the capacitor portion is increased, and a sufficient decoupling effect is easily obtained.

In the manufacturing method of the printed wiring board of this invention, it is preferable that the said capacitor | condenser part is set to the distance which the distance between the said upper electrode and the said lower electrode is 10 micrometers or less, and is not substantially short-circuited. In this case, since the distance between the electrodes of a capacitor | condenser part is small enough, the capacitance of this capacitor | condenser part can be enlarged.

1 is a cross-sectional view showing a schematic configuration of a printed wiring board 10;

2 is a cross-sectional view showing the fabrication procedure of the printed wiring board 10 (part 1),

3 is a cross-sectional view showing the fabrication procedure of the printed wiring board 10 (part 2),

4 is a cross-sectional view showing the fabrication procedure of the printed wiring board 10 (part 3),

5 is a cross-sectional view showing the fabrication procedure of the printed wiring board 10 (No. 4),

6 is a sectional view (No. 5) illustrating a manufacturing procedure of the printed wiring board 10,

7 is a cross-sectional view showing the fabrication procedure of the printed wiring board 10 (No. 6),

8 is a sectional view (part 7) showing a fabrication procedure of the printed wiring board 10,

9 is a sectional view (part 8) showing a manufacturing procedure of the printed wiring board 10,

10 is a sectional view (No. 9) illustrating a manufacturing procedure of the printed wiring board 10,

11 is a cross-sectional view showing the production procedure of the printed wiring board 10 (part 10),

12 is a sectional view (No. 11) showing a manufacturing procedure of the printed wiring board 10,

13 is a sectional view (part 12) showing a manufacturing procedure of the printed wiring board 10,

14 is a cross-sectional view showing the manufacturing procedure of the printed wiring board 10 (No. 13),

15 is a cross-sectional view showing the production procedure of the printed wiring board 10 (part 14),

16 is a cross-sectional view showing the fabrication procedure of the printed wiring board 10 (part 15),

17 is a cross-sectional view showing the production procedure of the printed wiring board 10 (No. 16),

18 is a cross-sectional view showing the production procedure of the printed wiring board 10 (17),

19 is a cross-sectional view showing the production procedure of the printed wiring board 10 (part 18),

20 is a graph showing a result of simulating the relationship between the capacitance of the condenser unit and the voltage drop of the IC chip for each driving frequency of the IC chip;

21 is an explanatory diagram of a conventional example.

Best Mode for Carrying Out the Invention

Next, embodiment of this invention is described based on drawing. 1 is a cross-sectional view showing a schematic configuration of a printed wiring board 10 according to an embodiment of the present invention.

The printed wiring board 10 of this embodiment is what is called a buildup multilayer printed wiring board, and the capacitor | condenser part 40 of the structure which sandwiched the high dielectric layer 43 made from ceramics with the lower electrode 41 and the upper electrode 42 was carried out. Grounding terminal 72 of a semiconductor element (IC chip) 70 operating at a frequency of several GHz to several tens of GHz on the ground pad 62 and the power supply pad 64 formed on the mounting surface 60. ) And the power supply terminal 74 are electrically connected through the solder bumps 76 and 78.

The condenser portion 40 is formed on the first electrical insulation layer 31 formed on the upper portion of the build-up portion 20, and the second electrical insulation layer 32 is formed on the upper portion of the condenser portion 40. Here, the build-up part 20 is a multilayered part by forming a conductor layer (for example, thickness exceeding 10 micrometers and less than 20 micrometers), after forming an insulating layer on a core board | substrate, and connecting between layers. Since it is well known in the art, the description thereof is omitted here. However, in this embodiment, the buildup part 20 extends vertically in the insulating layer 23, and has the ground conductor 21 and the insulating layer 23 which have a ground land 21a on the upper surface. It is assumed that the power supply conductor 22 extends in the vertical direction and has the power supply land 22a on the upper surface.

The lower electrode 41 of the condenser portion 40 is a beta pattern of a copper foil (for example, 20 to 50 µm in thickness), and is partially removed by etching or the like, but the upper surface of the first electrical insulating layer 31 It covers almost the entire surface. The lower electrode 41 is electrically connected to the lower electrode connecting portion 51. The lower electrode connecting portion 51 moves the condenser portion 40 upward and downward from the upper surface of the second electrical insulating layer 32 so that the lower electrode connecting portion 51 does not contact the upper electrode 42 of the condenser portion 40 but the lower electrode 41. It penetrates through and reaches the ground land 21a of the ground conductor 21 formed in the upper surface of the buildup part 20. The upper end side of the lower electrode connecting portion 51 is a wiring pattern 51a, and the wiring pattern 51a is formed on the upper surface of the second electrical insulation layer 32, and the ground pad 62 formed on the mounting surface 60. ) Is electrically connected. In this way, the lower electrode 41 is connected to the ground conductor 21 and the ground pad 62 via the lower electrode connecting portion 51.

Here, the lower electrode connecting portion 51 is not necessarily formed in the same number as the pad 62 for grounding. The reason for this is that when the pads 62 for ground are electrically connected to each other in the conductor layer above the upper electrode 42, at least one lower electrode connecting portion 51 connected to the pad 62 for ground exists. This is because all of the ground pads 62 are electrically connected to the ground conductor 21 through the lower electrode connecting portion 51. By doing in this way, since the number of holes in the upper electrode 42 (hole for penetrating the upper electrode 42 without the lower electrode connecting portion 51 in contact with the upper electrode 42) is reduced, the upper electrode 42 ) Area can be increased.

The upper electrode 42 in the condenser portion 40 is a beta pattern made of copper foil, and is partially removed by etching or the like, but is formed so as to have an area substantially equal to the lower electrode 41. The upper electrode 42 is electrically connected to the upper electrode connecting portion 52. This upper electrode connection part 52 is comprised by the upper electrode connection part 1st-3rd parts 52a-52c. The upper electrode connecting portion first portion 52a moves the condenser portion 40 from the upper surface of the second electrical insulating layer 32 so as not to contact the lower electrode 41 of the condenser portion 40 and the upper electrode 42. It is formed so as to penetrate in the up and down direction to reach the power supply land 22a of the power supply conductor 22 formed on the upper surface of the build-up portion 20. In addition, the upper electrode connecting portion second portion 52b is formed to reach the upper electrode 42 of the condenser portion 40 from the upper surface of the second electric insulation layer 32. In addition, the upper electrode connecting portion third portion 52c is formed so as to electrically connect the upper electrode connecting portion first portion 52a and the upper electrode connecting portion second portion 52b on the upper surface of the second electrical insulating layer 32. . Here, the upper electrode connection part third part 52c is formed as a wiring pattern. The upper electrode connecting portion 52 is electrically connected to the power supply pad 64 in which the upper electrode connecting portion third portion 52c is formed on the mounting surface 60, and the lower end of the upper electrode connecting portion first portion 52a is built. It is electrically connected with the power supply conductor 22 formed in the up part 20. In this way, the upper electrode 42 is connected to the power supply conductor 22 and the power supply pad 64 via the upper electrode connection portion 52.

Here, the upper electrode connecting portion first portion 52a does not necessarily have to be formed in the same number as the power pad 64. The reason for this is that if the power supply pads 64 are electrically connected to each other in the conductor layer above the upper electrode 42, at least one upper electrode connection portion first portion 52a connected to the power supply pad 64 exists. This is because all the power supply pads 64 are electrically connected to the power supply conductors 22 through the upper electrode connecting portion first portion 52a. By doing in this way, the hole in the lower electrode 41 and the upper electrode 42 (the upper electrode connection part 1st part 52a does not contact both electrodes 41 and 42, and penetrates both electrodes 41 and 42). Since the number of holes) is reduced, the area of both electrodes 41 and 42 can be increased.

The high-k dielectric layer 43 of the capacitor unit 40 is made of a ceramic obtained by baking a high-k dielectric material at a high temperature (for example, 600 to 950 ° C.), and specifically, BaTiO ₃ , SrTiO ₃ , TaO ₃ , Ta ₂ O _5. , PZT, PLZT, PNZT, PCZT, PSZT, a high-k dielectric material containing one or two or more metal oxides selected from the group consisting of 0.1 to 10 탆 thin film and then calcined to ceramics. The high dielectric layer 43 is in contact with the lower electrode connecting portion 51 but is not in contact with the upper electrode connecting portion 52.

The ground pad 62 is formed to be exposed to the mounting surface 60 and is electrically connected to the via hole 61 extending in the vertical direction in the insulating layer 33 formed on the upper surface of the second electrical insulating layer 32. It is. The ground pad 62 is electrically connected to the ground terminal 72 formed on the rear surface of the semiconductor element 70 through the solder bumps 76. In addition, the via hole 61 is formed so that the lower electrode connection part 51 and the ground pad 62 may be interlayer-connected.

The power supply pad 64 is formed to be exposed to the mounting surface 60, and is electrically connected to the via hole 63 extending in the vertical direction in the insulating layer 33 formed on the upper surface of the second electrical insulating layer 32. have. The power supply pad 64 is electrically connected to the power supply terminal 74 formed on the rear surface of the semiconductor element 70 via the solder bumps 78. In addition, the via hole 63 is formed so that the upper electrode connection part 52 and the power supply pad 64 may be interlayer-connected.

In addition, the soldering resist layer may be formed in the mounting surface 60, and the ground pad 62 and the power supply pad 64 may be exposed to the exterior from this soldering resist layer.

Next, the usage example of the printed wiring board 10 comprised in this way is demonstrated. First, the semiconductor element 70 in which the plurality of solder bumps 76 and 78 are arranged on the rear surface is mounted on the mounting surface 60 of the printed wiring board 10. At this time, the grounding terminal 72 of the semiconductor element 70, the power supply terminal 74, and the signal terminal (not shown) are respectively the grounding pad 62 of the mounting surface 60, the powering pad 64, Equipped with a signal pad (not shown). Then, each terminal is joined to each pad through solder bumps by reflow. Thereafter, the printed wiring board 10 is bonded to another printed wiring board such as a motherboard. At this time, a solder bump is formed in the pad formed in the back surface of the printed wiring board 10 previously, and it joins by reflow in contact with the corresponding pad on another printed wiring board.

Here, the power supply terminal 74 of the semiconductor element 70 is connected to the upper electrode connecting portion 52, the via hole 63, the power supply pad 64, and the solder bumps 78 from the power supply conductor 22 of the build-up portion 20. Power is supplied through. In addition, electric charge is supplied from the upper electrode connecting portion 52 to the upper electrode 42 of the condenser portion 40. On the other hand, the grounding terminal 72 of the semiconductor element 70 includes the solder bump 76, the grounding pad 62, the via hole 61, the lower electrode connecting portion 51, and the grounding conductor of the buildup portion 20 ( 21) is grounded. The lower electrode 41 of the condenser portion 40 is also grounded through the lower electrode connecting portion 51. Therefore, positive charges are stored in the upper electrode 42 of the condenser portion 40, and negative charges are stored in the lower electrode 41. The capacitance C of the capacitor 40 is expressed by C = εS / d (ε: dielectric constant of the high-k dielectric layer 43, S: electrode area, d: distance between electrodes). The dielectric constant ε of the high dielectric layer 43 is large because of ceramics such as barium titanate, and the electrode area S is large enough that both electrodes 41 and 42 have a beta pattern and occupy almost the entire surface of the plate surface of the wiring board. Since the distance d between electrodes is small at 1 µm, the capacitance C becomes a sufficiently large value. In addition, since the capacitor | condenser part 40 is built in just under the semiconductor element 70, the circumferential distance of the wiring of the capacitor | condenser part 40 and the semiconductor element 70 is a chip capacitor (usually semiconductor of the mounting surface 60). It is shortened compared with the circumferential distance of the wiring of the element 70 and the wiring of the semiconductor element 70. FIG.

Next, the manufacture example of the printed wiring board 10 of this embodiment is demonstrated based on FIG. 2-19 is explanatory drawing which shows the manufacturing procedure of a capacitor | condenser part. Here, as shown in FIG. 4, although the core board | substrate with which the buildup part 20 was formed in one side is used, since the manufacturing procedure of the buildup part 20 is well known (for example, June 20, 2000, an industrial newspaper) (See "Building-up multilayer printed wiring board technology" published by Kiyoshi Takagi), the description of the manufacturing procedure is omitted here, and the manufacturing procedure of the capacitor section will be described.

First, as shown in FIG. 2, the high dielectric capacitor sheet 400 in which the high dielectric layer 430 was sandwiched between two copper foils 410 and 420 was prepared. This high dielectric capacitor sheet 400 was produced as follows. That _{is,, BaTiO 3, SrTiO 3,} TaO 3, Ta 2 O 5, PZT, PLZT, PNZT, PCZT, 1 or two or more metals selected from the group consisting of PSZT the copper foil 410 having a thickness of 30 ~ 100㎛ A high dielectric material containing an oxide was printed in a thin film having a thickness of 0.1 to 10 µm (here, 1 µm) using a printing machine such as a roll coater or doctor blade to form an unbaked layer. After printing, the unbaked layer was fired in a non-oxidizing atmosphere such as vacuum or N ₂ gas at a temperature in the range of 600 to 950 ° C. to obtain a high dielectric layer 430. Thereafter, a copper layer is formed on the high-k dielectric layer 430 by using a vacuum deposition apparatus such as a sputter, and further copper is added to the copper layer 420 by adding about 10 μm of copper by electrolytic plating or the like. Formed.

Next, another example of the manufacturing procedure of the high dielectric capacitor sheet 400 will be described below.

(1) In dry nitrogen, diethoxybarium and bitetriisopropoxide titanium weighed to a concentration of 1.0 mol / liter are dissolved in a mixed solvent of dehydrated methanol and 2-methoxyethanol (volume ratio 3: 2). Then, it stirred for 3 days in room temperature nitrogen atmosphere, and prepared the solution of the alkoxide precursor composition of barium and titanium. Subsequently, the precursor composition solution was stirred while maintaining at 0 ° C., and the previously decarbonized water was hydrolyzed by spraying in a stream of nitrogen at a rate of 0.5 microliters / minute.

(2) The sol-gel solution thus prepared was passed through a 0.2 micron filter to filter precipitates and the like.

(3) The filtrate prepared in the above (2) was spin-coated at 1500 rpm for 1 minute on a copper foil 410 having a thickness of 30 to 100 µm (which later becomes the lower electrode 41). The substrate spin-coated with the solution was placed on a hot plate kept at 150 ° C. for 3 minutes to dry. Then, the board | substrate was inserted in the electric furnace maintained at 850 degreeC, and baking was performed for 15 minutes. Here, the viscosity of the sol-gel liquid was adjusted so that the film thickness obtained by one spin coating / drying / firing was 0.03 µm. In addition to copper, nickel, platinum, gold, silver, and the like may be used as the lower electrode 141.

(4) Spincoat / drying / firing was repeated 40 times to obtain a high dielectric layer 430 of 1.2 mu m.

(5) After that, a copper layer is formed on the high dielectric layer 430 using a vacuum deposition apparatus such as a sputter, and copper is further added on the copper layer by about 10 µm by electroplating or the like. 420 (later forming the upper electrode 42) was formed. In this way, a high dielectric constant capacitor sheet 400 was obtained. Dielectric properties were measured under the conditions of 1kHz, temperature 25 ℃, OSC level 1V using INPEDANCE / GAIN PHASE ANALYZER (manufactured by Hewlett-Packard, product name: 4194A), the relative dielectric constant was 1,850. In addition, vacuum vapor deposition may form metal layers, such as platinum and gold, in addition to copper, and may also form metal layers, such as nickel and tin, in addition to copper. In addition, although the high dielectric layer was made of barium titanate, by using another sol-gel solution, the high dielectric layer was made of strontium titanate (SrTiO ₃ ), tantalum oxide (TaO ₃ , Ta ₂ O ₅ ), lead zirconate titanate (PZT), It is also possible to use any one of lanthanum lead zirconate titanate (PLZT), niobium zirconate titanate (PNZT), calcium lead zirconate titanate (PCZT) and lead strontium zirconate titanate (PSZT).

In addition, other methods for producing the high dielectric capacitor sheet 400 include the following methods. That is, barium titanate powder (manufactured by Fuji Titanium Industry Co., Ltd., HPBT series) is 5 parts by weight of polyvinyl alcohol, 50 parts by weight of pure water, and 1 weight of dioctyl phthalate or dibutyl phthalate as a solvent-based plasticizer based on the total weight of barium titanate powder. It disperse | distributes to the binder solution mixed at negative ratio, and this is made to copper foil 410 (later becomes lower electrode 41) of thickness 30-100 micrometers using printing machines, such as a roll coater, a doctor blade, and an alpha coater, It is printed in a thin film having a thickness of about 5 to 7 μm, dried at 60 ° C. for 1 hour, 80 ° C. for 3 hours, 100 ° C. for 1 hour, 120 ° C. for 1 hour and 150 ° C. for 3 hours to obtain an unbaked layer. In addition to BaTiO ₃ , a paste containing one or two or more metal oxides selected from the group consisting of SrTiO ₃ , TaO ₃ , Ta ₂ O ₅ , PZT, PLZT, PNZT, PCZT, and PSZT may be used in a printing machine such as a roll coater or doctor blade. It is good also as a non-baking layer by printing and drying in a thin film shape of thickness 0.1-10 micrometers using (D). After printing, the unbaked layer is baked at a temperature in the range of 600 to 950 ° C. to obtain a high dielectric layer 430. Thereafter, a copper layer is formed on the high-k dielectric layer 430 by using a vacuum deposition apparatus such as a sputter, and further copper is added to the copper layer 420 by adding about 10 μm of copper by electrolytic plating or the like. (Later forming the upper electrode 42) is formed. In addition, vacuum vapor deposition may form metal layers, such as platinum and gold, in addition to copper, and may also form metal layers, such as nickel and tin, in addition to copper. In addition, the sputtering method which targets barium titanate is also possible.

The copper foil 410 on one side of the high dielectric capacitor sheet 400 thus obtained is thinned by etching to a thickness of 20 to 50 µm, and the surface (lower surface) of the copper foil 410 after etching is roughened. (See FIG. 3).

Subsequently, after preparing the core substrate (not shown) in which the buildup part 20 was formed, and laminating | stacking the thermosetting resin sheet 310 of B stage (uncured) so that the whole upper surface of the buildup part 20 may be covered, the said intrinsic The copper foil 410 which performed surface roughening among all the capacitor sheets 400 (51 mm x 51 mm) was adhered on the thermosetting resin sheet 310, and the thermosetting resin sheet 310 was completely thermoset after that ( See FIG. 4). The build-up portion 20 is formed on the upper surface of the ground conductor 21 and the power supply conductor 22 and the build-up portion 20 formed in the insulating layer 23 in the vertical direction, and the ground conductor 21. It was assumed that the land land 21a electrically connected to the ground and the power supply land 22a formed on the upper surface of the build-up portion 20 and electrically connected to the power supply conductor 22 were included.

Subsequently, the copper foil 420 is thinned by etching to a thickness of 20 to 30 μm (see FIG. 5), and after laminating a dry film as a photosensitive resist on the copper foil 420, exposure and development through a pattern mask are performed. This patterned resist 312 was formed (see FIG. 6). This patterning is performed such that the portion corresponding to the ground conductor 21 of the build-up portion 20 and the portion corresponding to the power conductor 22 are removed immediately. As a result, the ground land 21a is removed. The resist opening part 312-1 was formed just above, and the resist opening part 312-2 was formed just above the power supply land 22a. Thereafter, the copper foil 420 in the resist openings 312-1 and 312-2 was removed by etching (see FIG. 7). In this etching, a mixture of sulfuric acid and hydrogen peroxide was used as an etchant so that only the copper foil 420 exposed to the outside was removed, and the high dielectric layer 430 immediately below was not removed. Moreover, although the dry film was used as a photosensitive resist here, you may use a liquid resist.

Subsequently, the resist 312 was removed (see FIG. 8), and the dry film, which is a photosensitive resist, was further laminated, followed by exposure and development through a pattern mask to form a patterned resist 314 (see FIG. 9). This patterning is performed so that the inner circumferential region Ain is not covered with a dry film, but the outer circumferential region Aex is covered with a dry film, among the high dielectric layers 430 exposed to the outside. The resist opening part 314-1 was formed just above 21a, and the resist opening part 314-2 was formed just above the power supply land 22a. Thereafter, the high-k dielectric layers 430 in the resist openings 314-1 and 314-2 were removed by etching (see FIG. 10). This etching used hydrochloric acid as an etchant so that only the high dielectric layer 430 was removed and the copper foil 410 immediately below was not removed. Next, the copper foil 410 in the resist openings 314-1 and 314-2 was removed by etching (see FIG. 11). This etching used copper chloride etchant as an etchant. In addition, although the dry film was used as a photosensitive resist here, you may use a liquid resist. In addition, you may simultaneously etch the high dielectric layer 430 and the copper foil 410 in the resist openings 314-1 and 314-2 in FIG.

Thereafter, the resist 314 was removed (see FIG. 12). As a result, the sheet through-holes 401 and 402 are formed in the high dielectric capacitor sheet 400 immediately above the ground conductor 21 and the power supply conductor 22, respectively. Among these, the portion through which the sheet through hole 401 directly above the ground conductor 21 penetrates the copper foil 410 and the high dielectric layer 430 has a small diameter, and a portion that penetrates the copper foil 420. A large silver diameter is formed, and the portion of the sheet through hole 402 directly above the power supply conductor 22 penetrates the copper foil 410 and the high dielectric layer 430, and has a large diameter. The part which penetrates is made larger in diameter (diameter of the lower electrode connection part 51 <diameter of the upper electrode connection part 1st part 52a).

Subsequently, the thermosetting resin sheet 320 (for example, ABF-45SH manufactured by Ajinomoto Co., Ltd.) of the B stage (uncured) was laminated so as to cover the entire upper surface of the substrate during fabrication (see FIG. 13). ). And the hole was made to the predetermined position of the surface of this thermosetting resin sheet 320 by a carbon dioxide laser, a UV laser, a YAG laser, an excimer laser, etc. (refer FIG. 14). Here, the lower electrode connection hole 501, the upper electrode connection first hole 502, and the upper electrode connection second hole 503 were drilled. Specifically, the copper foil 410 is not exposed to the inner wall of the hole 501, and the copper foil 410 is not exposed to the lower electrode connection hole 501 directly on the ground conductor 21. It was formed so as to reach the land 21a for the ground so as to be exposed to the inner wall. At this time, since the hole diameter of the part which passes the copper foil 420 with respect to the sheet through-hole 401 was previously formed larger than the hole diameter of the part which passes through the copper foil 410, the hole for lower electrode connection It was possible to easily expose the copper foil 410 without exposing the copper foil 420 to the inner wall of the 501. Further, the first hole 502 for connecting the upper electrode is formed directly on the power supply conductor 22 to the power supply land 22a so that both the copper foils 410 and 420 are not exposed to the inner wall of the hole 502. It was. At this time, since the hole diameter of the sheet through hole 402 has been formed in advance, it is easy to avoid exposing both the copper foils 410 and 420 to the inner wall of the first hole 502 for connecting the upper electrode. there was. Moreover, the 2nd hole 503 for upper electrode connection was drilled on the copper foil 420 until it reached the copper foil 420, and was formed. In this way, after the hole was drilled, a desmear treatment was performed to remove smear and the like in each of the holes 501 to 503. In addition, the surface of the thermosetting resin sheet 320 was roughened by the desmear process.

In addition, the number of the lower electrode connection part 51 and the upper electrode connection part first part 52a can be adjusted according to the number of the resist opening parts 312-1 and 312-2 in FIG. For example, if the number of resist openings 312-1 and 312-2 is smaller than the total number of terminals of the IC chip 70, the number of holes drilled in the lower electrode 41 or the upper electrode 42 decreases. The area of each electrode increases, and the capacity of the condenser portion 40 increases. Moreover, the area of the lower electrode 41, the area of the upper electrode 42, the space of the lower electrode connection part 51 and the copper foil 420, and the upper electrode connection part first part 52a and the copper foil 410 and 420 The space of can be adjusted according to the sizes of the resist openings 312-1, 312-2, 314-1, and 314-2. Since the size of the resist openings 312-1, 312-2, 314-1, and 314-2 can be regarded as the size of the hole drilled in the lower electrode 41 or the upper electrode 42, the size of each electrode Furthermore, it can be seen as a factor for adjusting the capacity of the condenser portion 40.

Subsequently, after providing an electroless plating catalyst to the part (including the inner wall of each hole 501-503) exposed to the outside in the thermosetting resin sheet 320, it is immersed in the electroless copper plating aqueous solution, and is 0.6-6 in thickness. An electroless copper plating film 505 of 3.0 mu m was formed (see FIG. 15). Next, the dry film which is a photosensitive resist was laminated on the whole surface of this electroless copper plating film 505, and the patterned resist 506 was formed by exposing and developing through a pattern mask (refer FIG. 16). Then, an electrolytic copper plating film 507 is formed in a portion (including the inner wall of each hole 501 to 503) exposed to the outside of the electroless copper plating film 505 (see Fig. 17), and thereafter. The patterned resist 506 was removed (see FIG. 18), and the portion of the electroless copper plating film 505 exposed on the surface was removed by etching (see FIG. 19). Thereby, while each hole 501-503 was filled with copper, the copper wiring pattern was formed in the part which was exposed in the thermosetting resin sheet 320. As shown in FIG.

In addition, in FIG. 19, thermosetting resin sheets 310 and 320 (for example, ABF-45SH by Ajinomoto Co., Ltd.) correspond to the first electrical insulating layer 31 and the second electrical insulating layer 32, respectively. The copper foil 410, the copper foil 420, and the high dielectric layer 430 of the high dielectric capacitor sheet 400 each have a lower electrode 41, an upper electrode 42, and a high dielectric layer of the capacitor portion 40 ( 43, and copper filled in the lower electrode connection hole 501 and a copper wiring pattern on the second electrical insulating layer 32 connected thereto correspond to the lower electrode connecting portion 51 and the wiring pattern 51a, respectively. The copper filled in the first hole 502 for connecting the upper electrode, the copper filled in the second hole 503 for connecting the upper electrode, and the copper wiring pattern on the second electrical insulating layer 32 connecting them are respectively upper part. It corresponds to electrode connection part 1st-3rd parts 52a-52c.

According to the printed wiring board 10 described in detail above, in the flow which builds up, it has a structure which sandwiched the high dielectric constant layer 430 between two copper foils 410 and 420, and the capacitor part 40 is mentioned later. The lower electrode connecting portion 51 and the upper electrode connecting portion 52 can be formed even after the entire high surface of the plate surface of the wiring board is covered by the high dielectric capacitor sheet 400 to be formed.

In general, printed wiring boards are often built up at a temperature of 200 ° C. or lower, and therefore, it is difficult to sinter the high dielectric material at high temperature (for example, 600 to 950 ° C.) to form ceramics in the flow of building up. Therefore, as in the above-described embodiment, the capacitor portion (using the high dielectric capacitor sheet 400 having a structure in which the high dielectric layer 430, which has been pre-fired separately, is sandwiched between two copper foils 410 and 420), It is preferable to form 40).

In addition, the upper electrode connecting portion 52 is electrically connected to the power supply terminal 74 of the semiconductor element 70, and the lower electrode connecting portion 51 is electrically connected to the ground terminal 72 of the semiconductor element 70. Therefore, even if the on-off frequency of the semiconductor element 70 is high from several GHz to several tens of GHz, even in a situation where a momentary drop of the potential tends to occur, a sufficient decoupling effect is exhibited.

In addition, the high-k dielectric layer 43 of the capacitor | condenser part 40 produced by baking barium titanate etc. with a large dielectric constant, and the upper electrode 42 and the lower electrode 41 of the capacitor part 40 are plate surfaces as a beta pattern. Since the area is large enough to cover almost the entire surface of the electrode, and the spacing between the two electrodes 41 and 42 is 0.1 to 10 µm, the capacitance of the condenser portion 40 is increased, and a sufficient decoupling effect is easily obtained.

Moreover, since the capacitor | condenser part 40 is arrange | positioned just below the semiconductor element 70, compared with the case where a chip capacitor is arrange | positioned around the semiconductor element 70, the winding distance of wiring can be shortened, The occurrence of noise can be suppressed.

In addition, this invention is not limited to embodiment mentioned above at all, It goes without saying that it can implement in various aspects as long as it belongs to the technical scope of this invention.

For example, in the above-described embodiment, the capacitor portion 40 is formed using the high dielectric capacitor sheet 400, but instead of using the high dielectric capacitor sheet 400, the build-up portion 20 On the first electrically insulating layer 31 formed on the upper surface, the metal foil, the high dielectric layer made of ceramics, and the metal foil were laminated so as to cover the entire surface in this order, and then the upper electrode was carried out in the same manner as in the above-described embodiment. The connecting portion 52 or the lower electrode connecting portion 51 may be formed. Also in this case, the capacitor | condenser part 40 can be formed in the flow of a buildup.

In the above-described embodiment, the lower electrode 41 of the capacitor portion 40 is connected to the ground terminal 72 of the semiconductor element 70 or the ground conductor 21 of the build-up portion 20, While the upper electrode 42 was connected to the terminal 74 for power supply and the conductor 22 for power supply, the lower electrode 41 was connected with the terminal 74 for power supply and the conductor 22 for power supply, and the upper electrode 42 was grounded. You may connect with the terminal 72 for earth and the conductor 21 for ground.

In addition, in the above-mentioned embodiment, although the printed wiring board 10 in which the capacitor | condenser part 40 was built was demonstrated, you may make it mount the chip capacitor in the mounting surface 60 other than the built-in capacitor | condenser part 40. FIG. In this way, the capacitor portion 40 alone can be replenished by a chip capacitor mounted on the mounting surface 60 when the capacitance is insufficient. At this time, if the positive terminal of the chip capacitor is connected to the electrode for the power supply of the condenser unit 40 and the negative terminal of the chip capacitor is connected to the ground electrode of the condenser unit, the impedance of the path from the chip capacitor to the IC chip is reduced. Less loss is desirable.

(Examples 1 to 9)

The Example shown in Table 1 was produced according to embodiment mentioned above. Specifically, in the step shown in FIG. 6, the ratio of the number of the pads 62 for ground to the number of the resist openings 312-1 (the lower electrode connecting portion 51) is 1: 0.1, the pad 64 for the power source. The ratio of the number of to and the number of the resist openings 312-2 (the upper electrode connecting portion first portion 52a) was also formed to be 1: 0.1. Further, the sizes of the openings 312-1, 312-2, 314-1, and 314-2 shown in FIGS. 6 and 9 are adjusted so that the area where the lower electrode 41 and the upper electrode 42 face each other is 3.22. It adjusted to * 10 <^-5> m <2> -1.83 * 10 <^-3> m <2>. As a result, the capacity | capacitance of the capacitor part became 0.44 * 10 <^-6> F-25 * 10 <^-6> F. In this case, a plurality of ground terminals 72 of the IC chip 70 are electrically connected to one lower electrode connecting portion 51, and one IC 52 is connected to the first portion 52a of the upper electrode connecting portion 51a. The plurality of power supply terminals 74 are electrically connected.

(Example 10)

In the above-described embodiment, the size of the high dielectric capacitor sheet 400 is 49.5 mm x 43 mm, and the ratio of the number of the pads 62 for ground and the number of the lower electrode connecting portions 51 is 1: 1, for the power source. The ratio of the number of the pads 64 and the number of the upper electrode connection portions first portion 52a is also formed to be 1: 1. In addition, the number of the pads 62 for grounds and the number of pads 64 for power supply were 11000 pieces, respectively. Moreover, the size of each opening part 312-1 and 312-2 was made into the range of 300-400 micrometers (phi). As a result, the capacity | capacitance of the capacitor | condenser part became 0.18 * 10 <^-6> F.

(Example 11)

In Example 10, the ratio of the number of the pads 62 for ground and the number of the lower electrode connection parts 51 is 1: 0.7, and the ratio of the number of the pads 64 for power supply and the number of the first part 52a of the upper electrode connection parts, respectively. It was formed so that 1: 1: 0.7. As a result, the capacity of the capacitor portion became 8.8 × 10 ⁻⁶ F.

(Example 12)

In Example 10, the ratio of the number of the pads 62 for ground to the number of the lower electrode connectors 51 is 1: 0.5, and the ratio of the number of the pads 64 for power and the number of the first electrodes 52a for the upper electrode connectors 52a. 1: It was formed so that it might be 0.5. As a result, the capacity | capacitance of the capacitor part was set to ^{15x10 <-6>} F.

(Example 13)

In Example 10, the ratio of the number of the pads 62 for ground and the number of the lower electrode connection parts 51 is 1: 0.1, and the ratio of the number of the pads 64 for power supply and the number of the 1st parts 52a of the upper electrode connection parts, too. It was formed so that 1: 1: 0.1. As a result, the capacity | capacitance of the capacitor part became 26 * 10 <^-6> F.

(Example 14)

In Example 10, the ratio of the number of the pads 62 for ground and the number of the lower electrode connectors 51 is 1: 0.05, and the ratio of the number of the pads 64 for power and the number of the first portions 52a of the upper electrode connectors. 1: It was formed so that it might be 0.05. As a result, the capacity | capacitance of the capacitor part became 27.5 * 10 <^-6> F.

(Example 15)

In Example 10, the ratio of the number of the pads 62 for ground to the number of the lower electrode connectors 51 is 1: 0.03, the ratio of the number of the pads 64 for power and the number of the first portions 52a for the upper electrode connectors, respectively. 1: It was formed so that it might be 0.03. As a result, the capacity | capacitance of the capacitor part became 28 * 10 <^-6> F.

(Example 16)

In Example 10, the ratio of the number of the pads 62 for ground and the number of the lower electrode connection parts 51 is 1: 0.01, and the ratio of the number of the pads 64 for power supply and the number of the 1st parts 52a of the upper electrode connection parts, too. 1: It was formed so that it might be 0.01. As a result, the capacity | capacitance part became ^{29x10 <-6>} F.

(Example 17)

It produced according to Example 6. Specifically, in the preparation of the high dielectric capacitor sheet 400, the number of repetitions of spin coating / drying / firing was set to one circuit. As a result, the thickness of the high dielectric layer 430 was 0.03 micrometer.

(Example 18)

It produced according to Example 6. Specifically, in the preparation of the high dielectric capacitor sheet 400, the number of repetitions of spin coating / drying / firing was four times. As a result, the thickness of the high dielectric layer 430 was 0.12 micrometer.

(Example 19)

It produced according to Example 6. Specifically, in the preparation of the high dielectric capacitor sheet 400, the number of repetitions of spin coating / drying / firing was 15 circuits. As a result, the thickness of the high dielectric layer 430 was 0.45 µm.

(Example 20)

It produced according to Example 6. Specifically, in the preparation of the high dielectric capacitor sheet 400, the number of repetitions of spin coating / drying / firing was 200 times. As a result, the thickness of the high dielectric layer 430 was 6 µm.

(Example 21)

It produced according to Example 6. Specifically, in the preparation of the high dielectric capacitor sheet 400, the number of repetitions of spin coating / drying / firing was 330 circuits. As a result, the thickness of the high dielectric layer 430 was 9.9 micrometers.

(Example 22)

It produced according to Example 6. Specifically, in the preparation of the high dielectric capacitor sheet 400, the number of repetitions of spin coating / drying / firing was set to 500 circuits. As a result, the thickness of the high dielectric layer 430 was 15 micrometers.

(Example 23)

A chip capacitor was applied to the surface of the printed wiring board of Example 1, and the connection between the chip capacitor, the ground terminal of the IC chip, and the power supply terminal was performed via the capacitor portion 40 incorporated in the printed wiring board.

(Comparative Example)

The high dielectric capacitor sheet of the comparative example was produced based on the procedure of manufacturing another form of the high dielectric capacitor sheet described in the embodiment. However, the electrode was formed on the unbaked layer after drying without firing. As a result, the capacitance directly under the die was less than 0.001 μF.

(Evaluation examination 1)

The following IC chips were mounted on the printed wiring boards of Examples 1 to 16 and 23, and the simultaneous switching was repeated 100 times to repeat the pulse pattern generator / error detector (manufactured by Advantest, trade name: D3186 / 3286). Check for the malfunction using. The case where there was no malfunction was regarded as "good" and the case where there was a malfunction.

① Clock Frequency: 1.3GHz, FSB: 400MHz

② Clock Frequency: 2.4GHz, FSB: 533MHz

③ Clock Frequency: 3.0GHz, FSB: 800MHz

④ Clock Frequency: 3.73GHz, FSB: 1066MHz

From the comparison of the evaluation results of the examples and the comparative examples in which the IC chip of the above ① is mounted, it is understood that a malfunction is less likely to occur by incorporating a capacitor portion made of a dielectric layer made of ceramic. In addition, the evaluation results of mounting the IC chips 2 to 4 showed that malfunctions were less likely to occur as the capacitor capacity was larger, and that 0.8 μF or more resulted in no malfunction even when the IC chip of 3.0 GHz or more was mounted.

Moreover, in the printed wiring board of each Example, the circuit which can measure the voltage of an IC chip was formed in the printed wiring board, and the voltage drop of the IC chip at the time of simultaneous switching was measured. The relationship between the capacitance of the capacitor portion and the voltage drop of the IC chip was simulated for each driving frequency of the IC chip. This result is shown in FIG. The horizontal axis represents the capacitor capacity of the capacitor portion, and the vertical axis represents the voltage drop amount (%) at each driving voltage. From this simulation result, it was suggested that malfunction may occur when the voltage drop exceeds 10%.

(Evaluation examination 2)

Example 4, The printed wiring board of 17-22 was repeated 1000 cycles using -55 degreeC * 5 minutes and 125 degreeC * 5 minutes as 1 cycle. Interconnect the IC from the terminal on the side opposite to the IC chip mounting surface, and connect the connection resistance of the specific circuit connected to the terminal on the side opposite to the IC chip mounting surface (terminal different from the terminal on the opposite side) before the heat cycle test. , 500 cycles and 1000 cycles were measured, and the resistance change rate of the following formula was calculated | required. And when the resistance change rate was less than +/- 10%, when passing "(circle)" and +/- 10% exceeded, it was called defect "x", and the result was put together in Table 1.

Resistance change rate = [(connection resistance after heat cycle-connection resistance before heat cycle) / connection resistance before heat cycle] × 100 (%)

From this test result, it can be seen that the connection reliability tends to be lowered even if the thickness of the high dielectric layer of the capacitor portion is too thin or too thick. The reason for this is not clear, but if the high dielectric layer is too thin (that is, 0.03 µm or less), thermal shrinkage of the printed wiring board may cause cracks in the ceramic high dielectric layer, and the wiring of the printed wiring board may be broken. Doing. On the other hand, if the high dielectric layer of the capacitor portion is too thick (i.e., exceeding 9.9 mu m), the high dielectric layer made of ceramic and the upper electrode and the lower electrode have different coefficients of thermal expansion, so that the high dielectric layer and the upper portion in the horizontal direction of the printed wiring board It is speculated that the difference in the amount of shrinkage and expansion of the electrode and the lower electrode increases, and peeling occurs between the capacitor portion and the printed wiring board and the wiring of the printed wiring board is disconnected.

(Evaluation examination 3)

The printed circuit boards of Examples 10 to 16 were subjected to 500 cycles and 1000 cycles in the same heat cycle test as in Evaluation Test 2. After the heat cycle, an IC chip (clock frequency: 3.73 GHz, FSB: 1066 MHz) was mounted, and the presence or absence of malfunction was confirmed in the same manner as in Evaluation Test 1. The results are shown in Table 1.

From this test result, it turns out that malfunction is easy to generate | occur | produce even if the ratio of the number of electrode connection parts to the number of pads, ie, the number of electrode connection parts / pads, is too small. The reason is not clear, but if this ratio is too small (i.e., less than 0.03), the number of electrode connecting portions (lower electrode connecting portion 51 or upper electrode connecting portion first portion 52a) is too small, so that their electrical connection state In case of deterioration, it is inferred that the effect could not be fully covered by other electrode connection parts, and thus a malfunction may occur well. On the other hand, if this ratio is too large (i.e., exceeds 0.7), the portions of the lower electrode 41 and the upper electrode 42 passing through each electrode connecting portion in a non-contact state increase, and the resin and the high dielectric layer filled therein are increased. Due to the difference in thermal expansion of (43), shrinkage and expansion of the soft high dielectric layer 43 made of ceramic easily occur, and as a result, it is speculated that cracks have occurred in the high dielectric layer 43.

This invention is based on Japanese Patent Application No. 2004-188855 for which it applied on June 25, 2004 as a priority claim, and all the content is integrated.

The printed wiring board of this invention is used in order to mount semiconductor elements, such as an IC chip, and is used, for example in an electric-related industry or a communication-related industry.

Claims (13)

A printed wiring board for mounting a semiconductor element by embedding a capacitor portion having a structure in which a high dielectric layer made of ceramics is sandwiched between an upper electrode and a lower electrode, An upper electrode connecting portion electrically connected to the upper electrode of the condenser portion through a conductor layer formed above the condenser portion without going into contact with the upper electrode or the lower electrode of the condenser portion in an up and down direction; Lower electrode connecting portion penetrating the condenser part in the vertical direction so as to contact the lower electrode without contacting the upper electrode of the condenser part. Printed wiring board having a. The method of claim 1, The capacitor part is manufactured separately in a structure sandwiching the high dielectric layer between the upper electrode and the lower electrode, the printed wiring board is formed using a high dielectric capacitor sheet having a size covering the entire plate surface. The method of claim 1, And the upper electrode connecting portion is connected to a power terminal or a ground terminal of the semiconductor element, and the lower electrode connecting portion is connected to a ground terminal or a power terminal of the semiconductor element. The method of claim 3, wherein The upper electrode connecting portion is connected to a power supply conductor or a grounding conductor at a lower end of the portion penetrating the condenser portion in the vertical direction, and the lower electrode connecting portion is connected to a ground terminal or a power supply terminal of the semiconductor element, The printed wiring board in which the lower end of the part which penetrates in the direction is connected to the ground conductor or the power supply terminal. The method according to any one of claims 1 to 4, The high dielectric layer includes barium titanate (BaTiO ₃ ), strontium titanate (SrTiO ₃ ), tantalum oxide (TaO ₃ , Ta ₂ O ₅ ), lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), zirconate titanate A printed wiring board produced by firing a raw material containing one or two or more metal oxides selected from the group consisting of niobium (PNZT), lead calcium zirconate titanate (PCZT), and lead strontium zirconate titanate (PSZT). . The method according to any one of claims 1 to 5, And the upper electrode and the lower electrode are formed as a beta pattern. The method according to any one of claims 1 to 6, And the condenser portion is set to a distance at which the distance between the upper electrode and the lower electrode is 10 占 퐉 or less and is not substantially shorted. As a manufacturing method of a printed wiring board, (a) adhering a high dielectric capacitor sheet, which is separately manufactured, having a structure in which a high dielectric layer made of ceramics is sandwiched between two metal foils, on a first electrical insulating layer; (b) forming an upper electrode sheet through hole and a lower electrode sheet through hole penetrating the high dielectric capacitor sheet in an up and down direction; (c) forming a second electrical insulating layer filling the both sheet through holes and covering the upper surface of the high dielectric capacitor sheet; (d) a first hole for connecting the upper electrode which is drilled from the second electrical insulating layer to the upper electrode, and is drilled from directly above the sheet through hole for the upper electrode of the second electrical insulating layer to the first electrical insulating layer, The second hole for connecting the upper electrode where all of the upper electrode, the high-k dielectric layer and the lower electrode are not exposed to the inner wall, and the first through-hole of the lower electrode sheet through hole of the second electrical insulating layer; A step of forming a hole for connecting the lower electrode which is drilled up to an electrical insulation layer and the lower electrode is exposed to the inner wall without the upper electrode being exposed to the inner wall; (e) After filling the first hole for connecting the upper electrode and the second hole for connecting the upper electrode with the conductor material, the both are connected from above the second insulating layer to form the upper electrode connecting portion, Filling the lower electrode connection hole to form a lower electrode connection portion Method of manufacturing a printed wiring board comprising a. The method of claim 8, In the step (b), when the sheet through-hole for the lower electrode is formed, the printed wiring board is formed such that the hole diameter of the portion passing through the upper electrode is larger than the hole diameter of the portion passing through the lower electrode. Way. The method according to claim 8 or 9, In the step (d), the second hole for connecting the upper electrode extends from just above the sheet through hole for the upper electrode of the second electrical insulating layer to the power conductor or ground conductor in the first electrical insulating layer. The manufacturing method of the printed wiring board which drills and drills the said lower electrode connection hole from immediately above the said sheet | seat through-hole of the said lower electrode among the said 2nd electrical insulation layers, to the ground terminal or the power supply conductor in the said 1st electrical insulation layer. The method of claim 10, After the step (e), the upper electrode connection portion is connected to a power terminal or a ground terminal of a semiconductor element mounted on the printed wiring board, and the lower electrode connection portion is connected to a ground terminal or a power terminal of the semiconductor element. The manufacturing method of the printed wiring board to say. The method according to any one of claims 8 to 11, The high dielectric layer includes barium titanate (BaTiO ₃ ), strontium titanate (SrTiO ₃ ), tantalum oxide (TaO ₃ , Ta ₂ O ₅ ), lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), zirconate titanate A printed wiring board produced by firing a raw material containing one or two or more metal oxides selected from the group consisting of niobium (PNZT), lead calcium zirconate titanate (PCZT), and lead strontium zirconate titanate (PSZT). Method of preparation. The method according to any one of claims 8 to 12, And the condenser portion is set to a distance at which the distance between the upper electrode and the lower electrode is 10 占 퐉 or less and is not substantially shorted.

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