KR20070011661A - Thin film transistor substrate and its manufacturing method - Google Patents

Abstract

The present invention provides a thin film transistor substrate and a method of manufacturing the same that can prevent a short circuit between signal fan outs.

A method of manufacturing a thin film transistor substrate according to the present invention includes forming a gate fan out on a substrate in a non-display area; Forming an insulating film to cover the gate fan out; Forming a fan out contact hole penetrating the insulating film between the gate fan outs; And forming a data fan out on the insulating layer of the non-display area and removing conductive residues exposed by the fan out contact hole.

Description

Thin Film Transistor Substrate And Method of Fabricating The Same

1A and 1B are diagrams illustrating a short circuit phenomenon of a signal fan-out of a liquid crystal display panel using a conventional poly-silicon.

2 is a plan view illustrating a thin film transistor substrate included in a liquid crystal display panel according to a first exemplary embodiment of the present invention.

FIG. 3 is a cross-sectional view of the thin film transistor substrate of FIG. 2 taken along lines II ′ and II-II ′.

4A and 4B are plan views and cross-sectional views for describing a method of manufacturing the active layer illustrated in FIGS. 2 and 3.

5A and 5B are plan views and cross-sectional views illustrating a method of manufacturing the first conductive pattern group shown in FIGS. 2 and 3.

6A and 6B are plan views and cross-sectional views illustrating a method of manufacturing an interlayer insulating film having a source contact hole, a drain contact hole, and a fan out contact hole shown in FIGS. 2 and 3.

7A and 7B are plan and cross-sectional views for describing a method of manufacturing the second conductive pattern group shown in FIGS. 2 and 3.

8A and 8B are plan views and cross-sectional views for describing a method of manufacturing a passivation film having a pixel contact hole illustrated in FIGS. 2 and 3.

9A and 9B are plan views and cross-sectional views for describing a method of manufacturing the third conductive pattern group illustrated in FIGS. 2 and 3.

10A to 10C are cross-sectional views illustrating a second embodiment of a method of manufacturing a thin film transistor substrate included in a liquid crystal display panel according to a first embodiment of the present invention.

11 is a plan view illustrating a thin film transistor substrate included in a liquid crystal display panel according to a second exemplary embodiment of the present invention.

FIG. 12 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 11 taken along the line III-III ′.

13A to 13C are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIGS. 11 and 12.

14 is a cross-sectional view illustrating a thin film transistor substrate included in a liquid crystal display panel according to a third exemplary embodiment of the present invention.

<Description of Main Parts of Drawing>

101: substrate 102: gate line

104: data line 106: gate electrode

108: source electrode 110: drain electrode

112: gate insulating pattern 114: active layer

116: buffer layer 118: protective film

120,124,144,154 Contact hole 122 Pixel electrode

126: interlayer insulating film 130: thin film transistor

140: gate pad 142: gate fan out

150: Data Pad 152: Data Fan Out

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method for manufacturing the same, and more particularly, to a thin film transistor substrate and a method for manufacturing the same, which can prevent a short circuit between signal fan outs.

In general, a liquid crystal display (LCD) displays an image by allowing each of the liquid crystal cells arranged in a matrix to adjust light transmittance according to a video signal.

The liquid crystal display includes a thin film transistor substrate and a color filter substrate facing each other with a liquid crystal interposed therebetween.

The color filter substrate includes a black matrix for preventing light leakage, a color filter for color implementation, a common electrode forming a vertical electric field with the pixel electrode, and an upper alignment layer coated thereon for liquid crystal alignment.

The thin film transistor substrate includes a gate line and a data line formed to cross each other, a thin film transistor (TFT) formed at an intersection thereof, a pixel electrode connected to the thin film transistor, and a lower alignment layer coated thereon for liquid crystal alignment. It includes.

The signal lines of the gate lines and data lines are connected to the drive driver through signal fan outs and signal pads.

Here, as the number of signal fan-outs increases as the liquid crystal display device becomes higher resolution, the interval between adjacent signal fan-outs decreases. In this case, as shown in FIG. 1A, a short circuit failure between the signal fan outs 2 occurs due to an etching process defect A and a conductive foreign substance defect B as illustrated in FIG. 1B. This short circuit defect is not easy to detect because each signal fan out is commonly connected to the shorting bar during the inspection process, and since the detection is only detected in a diagonal pattern after the progress of the module, there is a problem in that efficiency is reduced in production and cost. In addition, even if the detection can be made through the laser, but there is a problem that the location of the short circuit failure is difficult.

Accordingly, it is an object of the present invention to provide a thin film transistor substrate and a method of manufacturing the same that can prevent a short circuit between signal fan outs.

In order to achieve the above object, a method of manufacturing a thin film transistor substrate according to the present invention comprises the steps of forming a gate fan out on the substrate of the non-display area; Forming an insulating film to cover the gate fan out; Forming a fan out contact hole penetrating the insulating film between the gate fan outs; And forming a data fan out on the insulating layer of the non-display area and removing conductive residues exposed by the fan out contact hole.

The gate fan out and the data fan out may be formed of a metal having the same etching sequence.

Meanwhile, forming the data fan out and removing the conductive residue may include depositing a data metal layer on the insulating film; Forming a photoresist pattern on the data metal layer; And etching the conductive residue using the photoresist pattern as a mask, and etching the data metal layer.

In addition, the method of manufacturing the thin film transistor substrate may include forming an active layer on the substrate; Forming a gate insulating film to cover the active layer; Forming a gate fan out on the gate insulating layer and forming a gate electrode of a gate line and a thin film transistor in a display area; Forming an interlayer insulating film that is the insulating film to cover the gate fan out, the gate line, and the gate electrode; Forming the fan out contact hole through the interlayer insulating film and the gate insulating film and forming a source contact hole and a drain contact hole exposing the active layer; Forming the data fan-out and forming a source electrode of the thin film transistor, a drain electrode of the thin film transistor, and a data line; Forming at least one passivation layer to cover the data fan out, the source electrode, the drain electrode, and the data line; The method may further include forming a pixel electrode on the passivation layer of the display area.

The method of manufacturing the thin film transistor substrate may further include forming a driving circuit part on which the power signal and the control signal are supplied through the gate fan out.

In order to achieve the above object, a method of manufacturing a thin film transistor substrate according to the present invention comprises the steps of forming a gate fan out on the substrate of the non-display area; Forming an insulating film to cover the gate fan out; Forming a fan out contact hole penetrating the insulating film between the gate fan outs; And removing the conductive residue exposed by the fan out contact hole.

The removing of the conductive residue exposed by the fan out contact hole may include removing the conductive residue between the adjacent gate fan outs which short-circuit the gate fan outs by using an insulating film having the fan out contact hole as a mask. Characterized in that the etching step.

In order to achieve the above object, a method of manufacturing a thin film transistor substrate according to the present invention comprises the steps of forming a data fan out on the substrate of the non-display area; Forming at least one layer of passivation film to cover the data fan out; Forming a fan out contact hole penetrating the passivation layer between the data fan outs; And removing the conductive residue exposed by the fan out contact hole.

The removing of the conductive residue exposed by the fan out contact hole may include removing the conductive residue between the adjacent data fan outs which short-circuit the data fan outs by using a protective film having the fan out contact hole as a mask. Characterized in that the etching step.

Or removing the conductive residue exposed by the fan out contact hole may etch the conductive residue positioned between the adjacent data fan outs using the third conductive pattern group as a mask to short the data fan outs. Characterized in that the step.

On the other hand, the manufacturing method of the thin film transistor substrate further comprises the step of forming a driving circuit portion on which the at least one of the power signal, control signal and data supplied through the data fan out on the substrate.

In order to achieve the above object, the thin film transistor substrate according to the present invention is located in the non-display area and the first and second signal fan out of the same etching series of metal; At least one insulating film insulating the first and second signal fan outs; And a fan out contact hole formed to penetrate the insulating layer between the adjacent first signal fan outs.

Wherein the fan out contact hole removes at least one of a conductive residue that shorts the adjacent first signal fan out and a metal residue of the first signal fan out.

The thin film transistor substrate may further include: a gate line formed of the same metal on the same plane as the first signal fan out; A data line formed of the same metal on the same plane as the second signal fan out and intersecting the gate line with the interlayer insulating film interposed therebetween; A pixel electrode formed in the pixel region provided at the intersection of the gate line and the data line; A gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode connected to the pixel electrode, a channel between the source electrode and the drain electrode is formed and overlaps with the gate electrode and the gate insulating layer interposed therebetween A thin film transistor having an active layer is further provided.

The thin film transistor substrate may further include a source contact hole and a drain contact hole that pass through the gate insulating layer and the interlayer insulating layer together with the fan out contact hole to expose the source region and the drain region of the active layer. do.

In order to achieve the above object, the thin film transistor substrate according to the present invention includes a signal fan out formed on the substrate of the non-display area; At least one insulating film formed to cover the signal fan out; And a fan out contact hole formed to penetrate the insulating film of the at least one layer between the adjacent signal fan outs.

The signal fan out may be a gate fan out formed of the same metal on the same plane as the gate line.

In this case, the thin film transistor substrate may further include a source contact hole and a drain contact hole penetrating the insulating layer of the at least one layer together with the fan out contact hole to expose the active layer.

Alternatively, the signal fan out may be a data fan out formed of the same metal on the same plane as the data line.

In this case, the thin film transistor substrate may further include a pixel contact hole that exposes the drain electrode through the at least one passivation layer together with the fan out contact hole.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 to 14.

FIG. 2 is a plan view partially illustrating a polysilicon TFT substrate according to a first embodiment of the present invention, and FIG. 3 is cut along the line I-I 'and II-II' of the TFT substrate shown in FIG. It is sectional drawing.

The polysilicon TFT substrate according to the first embodiment of the present invention shown in FIGS. 2 and 3 includes a TFT 130 connected to a gate line 102 and a data line 104, and a TFT 130 connected to a TFT 130. The pixel electrode 122, the gate pad 140 connected to the gate line 102, and the data pad 150 connected to the data line 104 are provided. The TFT 130 is formed of an N type or a P type, but only a case where the TFT 130 is formed of an N type will be described below.

The TFT 130 charges the pixel electrode 122 with the video signal. To this end, the TFT 130 may include a gate electrode 106 connected to the gate line 102, a source electrode 108 included in the data line 104, and a pixel contact hole 120 passing through the passivation layer 118. An active layer 114 is formed to form a channel between the source electrode 108 and the drain electrode 110 by the drain electrode 110 and the gate electrode 106 connected to the pixel electrode 122.

The active layer 114 is formed to have a channel region 114C, a source region 114S, and a drain region 114D on the lower substrate 101 with the buffer layer 116 interposed therebetween. The channel region 114C is formed to overlap the gate electrode 106 and the gate insulating layer 112 therebetween. The source region 114S and the drain region 114D are connected to the source and drain electrodes 108 and 110, respectively, facing each other with the channel region 114C interposed therebetween.

The gate electrode 106 connected to the gate line 102 is formed to overlap the channel region 114C of the active layer 114 and the gate insulating layer 112 therebetween. The source electrode 108 and the drain electrode 110 are formed to overlap each other with the gate electrode 106 and the interlayer insulating layer 126 therebetween. The source electrode 108 connected to the data line 104 is connected to the source region 114S of the active layer 114 through the source contact hole 124S passing through the interlayer insulating layer 126 and the gate insulating layer 112. Connected. The drain electrode 110 is connected to the drain region 114D of the active layer 114 through the drain contact hole 124D penetrating through the interlayer insulating layer 126 and the gate insulating layer 112.

The data pad 150 is connected to a data driver (not shown) to supply a data signal generated by the data driver to the data line 104 through the data fan out 152. Alternatively, a control signal, a power signal, and data are supplied to a data driver (not shown) formed on the substrate 101 through the data fan out 152.

The gate pad 140 is connected to a gate driver (not shown) to supply a gate signal generated by the gate driver to the gate line 102 through the gate fan out 142. Alternatively, a control signal and a power signal are supplied to a gate driver (not shown) formed on the substrate 101 through the gate fan out 142. Here, the gate driver includes at least one of a shift resist and a level shift. In addition, a power supply unit is mounted on the substrate 101 and at least one of an input terminal of the power supply unit, a gate fan out 142, and a data fan out 152 is connected.

The gate fan out 142 is formed to be spaced apart from the adjacent gate fan out 142 with the fan out contact hole 144 interposed therebetween. The fan out contact hole 144 serves to separate the shorted gate fan out 142. That is, the fan out contact hole 144 positioned in the region where the short circuit between the gate fan outs 142 occurs due to the etching process defect and the foreign matter defect, etc. penetrates the interlayer insulating layer 126 and the gate metal of the gate fan out 142. And to separate the gate fan out 142. In addition, the fan out contact hole 144 positioned in the region where the short circuit between the gate fan outs 142 does not occur is formed to pass through the interlayer insulating layer 126 and the gate insulating layer 112.

This polysilicon TFT substrate is formed by a manufacturing process as shown in Figs. 4A to 9B.

4A and 4B, a buffer layer 116 is formed on the lower substrate 101, and an active layer 114 is formed thereon.

The buffer layer 116 is formed by depositing an inorganic insulating material such as SiO ₂ on the lower substrate 101.

The active layer 114 is formed by depositing amorphous silicon on the buffer film 116 and crystallizing with laser to become poly-silicon, and then patterning the poly-silicon by a photolithography process and an etching process.

5A and 5B, a gate insulating layer 112 is formed on the buffer layer 116 on which the active layer 114 is formed, and the gate electrode 106, the gate line 102, and the gate fan out are formed thereon. A first conductive pattern group including 142 is formed.

The gate insulating layer 112 is formed by depositing an inorganic insulating material such as SiO ₂ on the buffer layer 116 on which the active layer 114 is formed.

In the first conductive pattern group including the gate electrode 106, the gate line 102, and the gate fan out 142, a gate metal layer is formed on the gate insulating layer 112, and then the gate metal layer is photolithographically processed and etched. It is formed by patterning in the process. Here, the first conductive pattern group is formed of a single layer structure made of a metal such as Al, AlNd, Cr, Cu, Mo, Ta, or a multi-layer structure formed of a combination thereof. For example, the first conductive pattern group is formed in a two-layer structure made of AlNd / MoW.

The n + impurity is implanted into the active layer 114 using the gate electrode 106 as a mask, so that the source region 114S and the drain region 114D of the active layer 114 which are not overlapped with the gate electrode 106 are formed. Is formed. The source and drain regions 114S and 114D of the active layer 114 face each other with the channel region 114C overlapping the gate electrode 106 interposed therebetween.

6A and 6B, an interlayer insulating layer 126 is formed on the gate insulating layer 112 on which the first conductive pattern group is formed, and source and drain contacts penetrating the interlayer insulating layer 126 and the gate insulating layer 112. Holes 124S and 124D and fan out contact holes 144 are formed.

The interlayer insulating layer 126 is formed by depositing an inorganic insulating material such as SiO ₂ on the gate insulating layer 112 on which the first conductive pattern group is formed.

Subsequently, the source and drain contact holes 124S exposing the source and drain regions 114S and 114D of the active layer 114 through the interlayer insulating layer 126 and the gate insulating layer 112 by photolithography and etching processes, respectively. 124D) is formed. At the same time, an interlayer insulating layer 126 between the gate fan outs 142 and a fan out contact hole 144 penetrating the gate insulating layer 112 are formed. At this time, when the neighboring gate fan out 142 is shorted, the fan out contact hole 144 is formed to pass through the interlayer insulating layer 126 to expose the short circuit 146 of the gate fan out 142. .

7A and 7B, a second conductive pattern group including a data line 104, a source electrode 108, a drain electrode 110, and a data fan out 152 is formed on the interlayer insulating layer 126. do.

The second conductive pattern group including the data line 104, the drain electrode 110, the source electrode 108, and the data fan out 152 forms a source / drain metal layer on the interlayer insulating layer 126. The source / drain metal layer is formed by patterning the photolithography process and the etching process. The source electrode 104 and the drain electrode 110 are connected to each of the source region 114S and the drain region 114D of the active layer 114 through the source and drain contact holes 124S and 124D, respectively.

At the same time, the short circuit 146 of the gate fan out 142 is removed by an etching process using the interlayer insulating layer 126 having the fan out contact hole 144 as a mask. At this time, the conductive residue, ie, the gate metal layer, positioned at the short circuit portion of the gate fan-out is formed of the same etching-based metal as the source / drain metal layer. That is, when the source / drain metal layer is patterned by dry etching, the gate metal layer is also formed of a material patterned by dry etching. When the source / drain metal layer is patterned by wet etching, the gate metal layer is also formed of a material patterned by wet etching.

Accordingly, the shorted gate fan out 142 is separated by removing the short circuit 146 of the gate fan out 142.

8A and 8B, a first passivation layer 118 and a second passivation layer 128 are formed on the interlayer insulating layer 126 on which the second conductive pattern group is formed, and the first and second passivation layers 118 and 128 are formed. The pixel contact hole 120 penetrating the through hole is formed.

The first passivation layer 118 is formed by depositing an inorganic insulating material on the interlayer insulating layer 126 on which the second conductive pattern group is formed. The second passivation layer 128 is formed by coating an entire surface of the organic insulating material on the first passivation layer 118 for the purpose of improving the aperture ratio.

Subsequently, a pixel contact hole 120 is formed through the first and second passivation layers 118 and 128 to expose the drain electrode 110 of the TFT 130 by a photolithography process and an etching process.

9A and 9B, a third conductive pattern group including the pixel electrode 122 is formed on the passivation layer 118.

The third conductive pattern group including the pixel electrode 122 is formed by depositing a transparent conductive material on the passivation layer 118 and then patterning the transparent conductive material by a photolithography process and an etching process. The pixel electrode 122 is connected to the drain electrode 110 of the TFT 130 through the pixel contact hole 120.

As such, the poly-type TFT substrate and its manufacturing method according to the present invention have a first fan out contact hole formed between adjacent gate fan outs. The conductive residue exposed by this first fan out contact hole is automatically removed during the etching process of the source / drain metal layer. Accordingly, the poly-type TFT substrate and the manufacturing method thereof according to the present invention can automatically separate the shorted gate fan out.

10A to 10C are cross-sectional views illustrating a second embodiment of a method of manufacturing a thin film transistor substrate according to the first embodiment of the present invention. Here, only the manufacturing method of the source contact hole, the drain contact hole and the fan out contact hole, which are different from the first embodiment of the method of manufacturing the thin film transistor substrate according to the first embodiment of the present invention, will be described.

First, as shown in FIG. 10A, an inorganic insulating material such as SiO ₂ is deposited on the gate insulating layer 112 on which the first conductive pattern group is formed to form an interlayer insulating layer 126.

Subsequently, the interlayer insulating film 126 and the gate insulating film 112 are patterned by a photolithography process and an etching process to expose the source and drain regions 114S and 114D of the active layer 114, respectively, as shown in FIG. 10B. And drain contact holes 124S and 124D are formed. At the same time, an interlayer insulating layer 126 between the gate fan outs 142 and a fan out contact hole 144 penetrating the gate insulating layer 112 are formed.

Then, the short circuit 146 of the gate fan out 142 exposed by the fan out contact hole 144 is removed by a separate etching process as shown in FIG. 10C. At this time, when the material of the short circuit portion 146 of the gate fan out 142 is formed of, for example, Al series, the short circuit portion 146 is removed by a wet etching process, and a short circuit of the gate fan out 142 is performed. When the material of the part 146 is formed of Mo-based, for example, the short circuit part 146 is removed by a dry etching process.

As such, the poly-type TFT substrate and the manufacturing method thereof according to the present invention can automatically remove the conductive residue exposed by the fan out contact hole by a separate etching process. Accordingly, the poly-type TFT substrate and the manufacturing method thereof according to the present invention can automatically separate the shorted gate fan out.

FIG. 11 is a plan view illustrating a TFT substrate according to a second exemplary embodiment of the present invention, and FIG. 12 is a cross-sectional view of the TFT substrate illustrated in FIG. 11 taken along line III-III ′.

The TFT substrate according to the second embodiment of the present invention shown in FIGS. 11 and 12 has a second fan out contact hole positioned between the data fan outs 152 as compared to the TFT substrate shown in FIGS. 2 and 3. The same components are provided except that 154 is further provided. Accordingly, detailed description of the same components will be omitted.

Second fan out contact holes 154 are formed between adjacent data fan outs 152. In particular, the second fan out contact hole 154 serves to separate the shorted data fan out 152. That is, the second fan out contact hole 154 positioned in the region where the short circuit between the data fan out 152 is generated due to the etching process defect and the foreign matter defect, etc. may cause the first and second passivation layers 118 and 128 and the data fan out 152. Is formed to penetrate the data metal layer of &lt; RTI ID = 0.0 &gt; In addition, the second fan out contact hole 154 positioned in an area where a short circuit between the data fan outs 152 does not occur is formed to pass through the first and second passivation layers 118 and 128.

13A to 13C are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a second embodiment of the present invention.

First, as shown in FIG. 13A, a source / drain metal layer is formed on the interlayer insulating layer 126, and then the source / drain metal layer is patterned by a photolithography process and an etching process to form a data line 104 and a source electrode 108. ), A second conductive pattern group including a drain electrode 110 and a data fan out 152 is formed. In this case, the data fan outs 152 are often shorted due to a defect of an etching process and a defect due to a foreign material.

As shown in FIG. 13B, the inorganic insulating material and the organic insulating material are sequentially applied to the interlayer insulating film 126 on which the second conductive pattern group is formed, thereby forming the first protective film 118 and the second protective film 128. Subsequently, the pixel contact hole 120 exposing the drain electrode 110 of the TFT 130 and the interlayer insulating layer 126 are exposed through the first and second passivation layers 118 and 128 by a photolithography process and an etching process. In addition, a second fan out contact hole 154 exposing the short circuit 156 of the data fan out 152 is formed.

Then, the short circuit 156 of the data fan out 152 exposed by the second fan out contact hole 154 is removed by an etching process as shown in FIG. 13C. That is, the short circuit 156 of the data fan out 152 is patterned by using an etching gas or an etchant that does not react with the source / drain metal layer after the pixel contact hole is formed. Alternatively, after the third conductive pattern group is formed, the short-circuit portion 156 of the data fan-out is patterned using an etching gas or an etchant that does not react with the second passivation layer 128 using the third conductive pattern group as a mask.

As such, the poly-type TFT substrate and its manufacturing method according to the present invention have a second fan out contact hole formed between adjacent data fan outs. The conductive residue exposed by the second fan out contact hole can be automatically removed by a separate etching process. Accordingly, the poly-type TFT substrate and the manufacturing method thereof according to the present invention can automatically separate the shorted data fan out.

14 is a cross-sectional view illustrating a thin film transistor substrate according to a third exemplary embodiment of the present invention.

The thin film transistor substrate according to the third embodiment of the present invention shown in FIG. 14 has the same configuration except that the thin film transistor substrate shown in FIGS. 2 and 3 further includes a dummy pattern 160 for repair. With elements. Accordingly, detailed description of the same components will be omitted.

The dummy pattern 160 is formed to overlap the gate fan out 142, at least one of the interlayer insulating layer 126, and the first and second passivation layers 118 and 128 therebetween. When a disconnection occurs in the gate fan out 142, the dummy pattern 160 is melted by a laser and electrically connected to the gate fan out 142. The dummy pattern 160 is formed on the same plane as the second conductive pattern group including the data fan-out 152 and coplanar with the same metal as the third conductive pattern group including the pixel electrode 122. Is formed on the phase.

The dummy pattern 160 is formed to overlap not only the gate fan out 142 but also the data fan out 152 with at least one insulating layer therebetween. The dummy pattern 160 is melted by a laser and electrically connected to the data fan out 152 when a disconnection occurs in the data fan out 152.

As described above, the TFT substrate and the manufacturing method thereof according to the present invention have a fan out contact hole formed between adjacent signal fan outs. The conductive residue exposed by this fan out contact hole can be removed by a separate etching process or a source / drain metal layer patterning process. Accordingly, the poly-type TFT substrate and the manufacturing method thereof according to the present invention can automatically separate the shorted signal fan out without a repair process using a laser.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (25)

Forming a gate fan out on the substrate in the non-display area; Forming an insulating film to cover the gate fan out; Forming a fan out contact hole penetrating the insulating film between the gate fan outs; And forming a data fan out on the insulating layer in the non-display area, and removing conductive residues exposed by the fan out contact holes. The method of claim 1, And the gate fan out and the data fan out are formed of a metal having the same etching sequence. The method of claim 2, Forming the data fan out and removing the conductive residue Depositing a data metal layer on the insulating film; Forming a photoresist pattern on the data metal layer; And etching the conductive metal residue using the photoresist pattern as a mask, and etching the data metal layer. The method of claim 1, Forming an active layer on the substrate; Forming a gate insulating film to cover the active layer; Forming a gate fan out on the gate insulating layer and forming a gate electrode of a gate line and a thin film transistor in a display area; Forming an interlayer insulating film that is the insulating film to cover the gate fan out, the gate line, and the gate electrode; Forming the fan out contact hole through the interlayer insulating film and the gate insulating film and forming a source contact hole and a drain contact hole exposing the active layer; Forming the data fan-out and forming a source electrode of the thin film transistor, a drain electrode of the thin film transistor, and a data line; Forming at least one passivation layer to cover the data fan out, the source electrode, the drain electrode, and the data line; And forming a pixel electrode on the passivation layer of the display area. The method of claim 1, And forming a driving circuit part on the substrate to which a power signal and a control signal are supplied through the gate fan out. Forming a gate fan out on the substrate in the non-display area; Forming an insulating film to cover the gate fan out; Forming a fan out contact hole penetrating the insulating film between the gate fan outs; Removing the conductive residue exposed by the fan out contact hole. The method of claim 6, Removing the conductive residue exposed by the fan out contact hole Etching the conductive residue between the adjacent gate fan outs which short-circuit the gate fan outs by using an insulating film having the fan out contact hole as a mask. The method of claim 6, Forming an active layer on the substrate; Forming a gate insulating film to cover the active layer; Forming a gate fan out on the gate insulating layer and forming a gate electrode of a gate line and a thin film transistor in a display area; Forming an interlayer insulating film to cover the gate fan out, the gate line, and the gate electrode; Forming the fan out contact hole through the interlayer insulating film and the gate insulating film and forming a source contact hole and a drain contact hole exposing the active layer; Forming the data fan-out and forming a source electrode of the thin film transistor, a drain electrode of the thin film transistor, and a data line; Forming at least one passivation layer to cover the data fan out, the source electrode, the drain electrode, and the data line; And forming a pixel electrode on the passivation layer of the display area. The method of claim 6, And forming a driving circuit unit on the substrate to which at least one of a power signal, a control signal, and data is supplied through the gate fan out. Forming a data fan out on the substrate in the non-display area; Forming at least one layer of passivation film to cover the data fan out; Forming a fan out contact hole penetrating the passivation layer between the data fan outs; Removing the conductive residue exposed by the fan out contact hole. The method of claim 10, Forming an active layer on the substrate; Forming a gate insulating film to cover the active layer; Forming a first conductive pattern group including a gate fan-out in the non-display area on the gate insulating layer, a gate line in the display area, and a gate electrode of a thin film transistor; Forming an interlayer insulating film to cover the first conductive pattern group; Forming a source contact hole and a drain contact hole through the interlayer insulating layer and the gate insulating layer to expose the active layer; Forming a second conductive pattern group including the data fan out, a source electrode of the thin film transistor, a drain electrode of the thin film transistor, and a data line; Forming a pixel contact hole and a fan out contact hole through the passivation layer of the at least one layer to expose the drain electrode; And forming a third conductive pattern group including a pixel electrode connected to the drain electrode through the pixel contact hole on the passivation layer of the display area. The method of claim 10, Removing the conductive residue exposed by the fan out contact hole And etching the conductive residue between the adjacent data fan outs to short the data fan outs by using a protective film having the fan out contact hole as a mask. The method of claim 10, Removing the conductive residue exposed by the fan out contact hole Etching the conductive residue that is positioned between the adjacent data fan outs using the third conductive pattern group as a mask to short the data fan outs. The method of claim 10, And forming a driving circuit unit on the substrate to which at least one of a power signal, a control signal, and data is supplied through the data fan-out. First and second signal fan-outs positioned in the non-display area and made of metal of the same etching series; At least one insulating film insulating the first and second signal fan outs; And a fan out contact hole formed to penetrate the insulating layer between the adjacent first signal fan outs. The method of claim 15, And the fan out contact hole removes at least one of a conductive residue shorting the adjacent first signal fan out and a metal residue of the first signal fan out. The method of claim 15, A gate line formed of the same metal on the same plane as the first signal fan out; A data line formed of the same metal on the same plane as the second signal fan out and intersecting the gate line with the interlayer insulating film interposed therebetween; A pixel electrode formed in the pixel region provided at the intersection of the gate line and the data line; A gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode connected to the pixel electrode, and a channel between the source electrode and the drain electrode are formed and the gate electrode and the gate insulating film are interposed therebetween. The thin film transistor substrate further comprising a thin film transistor having an active layer overlapping. The method of claim 17, And a source contact hole and a drain contact hole penetrating the gate insulating layer and the interlayer insulating layer together with the fan out contact hole to expose the source region and the drain region of the active layer. A signal fan out formed on the substrate in the non-display area; At least one insulating film formed to cover the signal fan out; And a fan out contact hole formed through the at least one insulating layer between the adjacent signal fan outs. The method of claim 19, And the fan out contact hole removes at least one of a conductive residue that shorts the adjacent signal fan out and a metal residue of the signal fan out. The method of claim 19, A gate line formed on the substrate; A data line crossing the gate line and an interlayer insulating layer therebetween; A pixel electrode formed on the passivation layer of the pixel region provided at the intersection of the gate line and the data line; A gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode connected to the pixel electrode, a channel between the source electrode and the drain electrode is formed and overlaps with the gate electrode and the gate insulating layer interposed therebetween The thin film transistor substrate further comprises a thin film transistor having an active layer. The method of claim 21, And the signal fan out is a gate fan out formed of the same metal on the same plane as the gate line. The method of claim 22, And a source contact hole and a drain contact hole which pass through the at least one passivation layer and expose the active layer together with the fan out contact hole. The method of claim 21, And the signal fan-out is a data fan-out formed of the same metal on the same plane as the data line. The method of claim 24, And a pixel contact hole penetrating the at least one passivation layer and exposing the drain electrode together with the fan out contact hole.

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