KR20070006274A - The manufacturing method of a semiconductor device. - Google Patents

Abstract

In the method of manufacturing a semiconductor device, a mask pattern having a first pitch is first formed on a substrate. The recess is formed by partially etching the substrate using the mask pattern as an etching mask. A gate oxide film is formed continuously on the surface of the substrate and the recess portion. A gate conductive layer is formed on the gate oxide layer to fill the recess. Next, by etching a portion of the gate conductive film, a second sidewall having a second pitch that is 1/2 of the first pitch and having a first sidewall disposed on a substrate and facing the first sidewall is the recessed portion. Forming a gate electrode located on the bottom surface. In the case of the transistor manufactured by the above method, the channel length is longer than the gate line width, and the operation characteristics are good.

Description

A method for manufacturing a semiconductor device.

1 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

100 semiconductor substrate 103 first hard mask film

104: first hard mask pattern 105: photoresist pattern

106: recessed portion 108: gate oxide film

110: preliminary first conductive film 110a: first conductive film

110b: first conductive film pattern 112: second conductive film

112a: second conductive film pattern 114: second hard mask film

114a: second hard mask pattern 116: second photoresist pattern

120: gate electrode 122: spacer

124 Source / Drain

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including a recessed gate electrode.

In recent years, as semiconductor devices have become highly integrated, the line width of the pattern and the distance between the pattern and the pattern have also become very small. In particular, the line width of the gate electrode of a transistor mainly formed on a substrate during manufacture of a semiconductor device is very small.

Due to the reduction in the line width of the gate electrode, it is more difficult to secure the operating characteristics of the transistor. In particular, in the case of the DRAM device, a problem such as the deterioration of the refresh characteristics due to the increase of the leakage current is seriously generated.

In order to overcome the above problems, researches such as changing the structure of the gate electrode from the planar type to the recess type have been continuously conducted. As described above, when the structure of the gate electrode is formed in the recess type, the channel path between the source and the drain becomes long, so that the leakage current may be reduced, thereby improving the refresh characteristic.

In order to form the recessed gate electrode structure, a recess portion having an inner width smaller than the line width of the gate electrode should be formed. However, since the line width of the gate electrode is close to the limit of the current exposure equipment, in order to form a recess having an inner width smaller than the line width of the gate electrode, the thermal resistance of the photoresist is patterned after patterning with the current exposure equipment. A process is advanced by performing a flow process, a chemical addition process, etc. However, when the inner width of the recess portion is reduced through the subsequent processing as described above, it is difficult to expect reproducibility of the inner width of the recess portion, and problems such as the recess portion not being formed normally or the position of the recess portion are shifted continuously. Will occur.

Accordingly, there is a need for a method of manufacturing a semiconductor device having a recessed gate electrode capable of securing leakage current characteristics and refresh characteristics while reducing defects caused by a photo process.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device having a gate electrode capable of securing leakage current characteristics and refresh characteristics by a simpler process.

As a method of manufacturing a semiconductor device according to an embodiment of the present invention for achieving the above object, first, a mask pattern having a first pitch is formed on a substrate. The recess is formed by partially etching the substrate using the mask pattern as an etching mask. A gate oxide film is formed continuously on the surface of the substrate and the recess portion. A gate conductive layer is formed on the gate oxide layer to fill the recess. Next, by etching a portion of the gate conductive film, a second sidewall having a second pitch that is 1/2 of the first pitch and having a first sidewall disposed on a substrate and facing the first sidewall is the recessed portion. A gate electrode is formed on the bottom surface.

According to the process, the first sidewall of the gate electrode is located on the substrate and the second sidewall facing the first sidewall is located on the bottom surface of the recess. Therefore, the inner width of the recess portion is larger than the line width of the gate electrode. In addition, the pitch between the recesses is twice the pitch of the gate electrode. As described above, since the inner width of the recess portion is increased as compared with the related art, the recess portion can be sufficiently formed even by a conventional photographic process. For this reason, the defect which frequently occurred at the time of forming the recess can be reduced.

In addition, by forming the recess portion, the channel path is sufficiently long in the vertical direction, thereby reducing leakage current, thereby improving refresh characteristics.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the dimensions of the substrates, layers (films), regions, patterns or structures are shown in greater detail than actual for clarity of the invention. In the present invention, when referred to as being formed "on", "upper" or "under", "lower" of an object, it may be formed while directly contacting the upper or lower surface of the object. In the state where additional structures are formed on the object, the object may be formed above or below the object.

1 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. In this embodiment, a method of manufacturing a cell transistor of a DRAM device will be described.

Referring to FIG. 1, an active region and a field region are distinguished by forming an isolation layer pattern on a semiconductor substrate.

More specifically, first, a pad oxide film (not shown) and a device isolation hard mask film (not shown) are formed on a semiconductor substrate. The pad oxide layer may be formed using silicon oxide, and the hard mask layer for device isolation may be formed using silicon nitride.

Next, a photolithography process is performed to pattern the device isolation hard mask layer to form a device isolation hard mask pattern (not shown).

The device isolation trench is formed by etching the semiconductor substrate 100 using the device isolation hard mask pattern as an etching mask.

A trench inner wall oxide film (not shown) is formed on the side and bottom of the device isolation trench. A nitride film liner is formed on surfaces of the trench inner wall oxide layer (not shown) and the device isolation hard mask pattern.

Next, an insulating film is deposited to fill the inside of the isolation trench and the insulating film is polished to complete the device isolation pattern. Examples of the insulating film that can be used include HDP oxide film, thermal oxide film, TEOS film or USG film. The insulating film may be formed alone, or may be formed by stacking two or more.

Thereafter, the hard mask pattern for device isolation is removed. Through the above process, the substrate is divided into an active region and a field region.

The first hard mask layer 103 is formed on the substrate in which the active region and the field region are separated. The first hard mask layer 103 is formed using a material having an etching selectivity different from that of the semiconductor substrate 100. The first hard mask layer 103 is formed using a material having a property that the first hard mask layer 103 is hardly etched when the semiconductor substrate is etched. In detail, the first hard mask layer 103 may be formed using silicon oxide or silicon nitride.

A photoresist film (not shown) is coated on the first hard mask film 103. An exposure and development process is performed on the photoresist film to form a photoresist pattern 105 for selectively masking a region where a first hard mask pattern is to be formed. The first hard mask pattern defines a recessed portion of the gate electrode. Specifically, a portion selectively exposed by the first hard mask pattern is a recess portion of the gate electrode.

In this case, the photoresist patterns 105 are disposed to have a first pitch P1. Here, the first pitch P1 is twice the second pitch which is the pitch of the target gate electrode.

As described above, since the photoresist pattern 105 is formed at a pitch twice the pitch of the gate electrode, the process margin during the photolithography process for forming the recess portion can be greatly increased.

Referring to FIG. 2, the first hard mask layers 104 are formed by etching the first hard mask layers (FIGS. 1 and 103) using the photoresist pattern 105 as an etching mask. In this case, the first hard mask pattern 104 is disposed to have the first pitch P1.

Next, the photoresist pattern 105 is removed through an ashing and stripping process.

In the present exemplary embodiment, the first hard mask pattern 104 is formed to have a line shape crossing the active region in the first direction. However, it is noted that the first hard mask pattern 104 may be formed to have an isolated pattern shape that traverses the active region in the first direction.

Referring to FIG. 3, the recess portion 106 is formed by etching the semiconductor substrate 100 using the first hard mask pattern 104 as an etching mask. The recess portion 106 preferably has an internal width of 1.2 to 2.8 times the line width of the target gate electrode.

In the present exemplary embodiment, the recess portion is formed using the first hard mask pattern 104, but as another example, the photoresist pattern is used as an etch mask without forming the first hard mask pattern 104. Note that the recessed portion 106 may be formed.

Referring to FIG. 4, a gate oxide film 108 is formed on the semiconductor substrate 100 on which the recess portion 106 is formed.

The gate oxide layer 108 may be formed through a thermal oxidation process. In this case, the gate oxide film 108 is continuously formed on the upper surface of the substrate and the side and bottom surfaces of the recess 106 in the active region, and the gate oxide film 108 is not formed in the field region.

Alternatively, the gate oxide layer 108 may be formed by depositing a metal oxide having a higher dielectric constant than the silicon oxide. At this time, the deposition process may be applied to the chemical vapor deposition process, atomic layer deposition process and the like. In this case, although not shown, the gate oxide film 108 is continuously formed on the upper surface of the substrate and the side and bottom surfaces of the recess portion 106 in the active region and the field region.

The preliminary first conductive layer 110 is deposited on the substrate on which the gate oxide layer 108 is formed to completely fill the recess 106. The preliminary first conductive layer 110 may be formed by depositing a polysilicon material doped with impurities through a low pressure chemical vapor deposition (LPCVD) process. The impurity doping may be performed by POCl ₃ diffusion, ion implantation, or in-situ doping. When the polysilicon is deposited through a low pressure chemical vapor deposition (LPCVD) process, the step coverage property is good, and thus the preliminary first is formed without generating voids in the recess 106. The conductive film 110 may be buried.

Referring to FIG. 5, the upper surface of the preliminary first conductive layer 110 is polished by performing a chemical mechanical polishing process to form a first conductive layer 110a having a flat upper surface.

A second conductive layer 112 having a lower resistance than the first conductive layer 110a is deposited on the first conductive layer 110a. In detail, the second conductive layer 112 may be formed using a metal or a metal silicide material. In the present embodiment, the second conductive layer 112 is formed using a tungsten silicide material.

Next, a second hard mask film 114 is formed on the second conductive film 112. The second hard mask layer 114 may be formed by depositing silicon nitride.

Referring to FIG. 6, a photoresist film (not shown) is coated on the second hard mask layer 114. Next, the second photoresist pattern 116 for patterning the gate electrode is formed by exposing and developing the photoresist film. The second hard mask pattern 114a is formed by etching the second hard mask layer 114 using the second photoresist pattern 116 as an etching mask. In this case, the pitch of the second hard mask patterns 114a, that is, the second pitch P2 is 1/2 of the first pitch P1.

Thereafter, although not shown, the second photoresist pattern 116 is removed through an ashing and stripping process.

Referring to FIG. 7, the second conductive layers (FIGS. 6 and 112) and the first conductive layers (FIGS. 6 and 110 a) are sequentially etched using the second hard mask pattern 114 a as an etching mask. A first sidewall is disposed on the substrate and a second sidewall facing the first sidewall forms a gate electrode positioned on a bottom surface of the recess.

The gate electrode 120 has a shape in which a first conductive layer pattern 110b and a second conductive layer pattern 112a having a lower resistance than the first conductive layer pattern 110b are stacked. In this case, the pitch between the gate electrodes 120, that is, the second pitch P2 is 1/2 of the first pitch.

When the gate electrode 120 is formed as described above, channels of the completed MOS transistors are formed along sidewalls and bottom surfaces of the recess portion 106. Therefore, it has a long channel length compared to the line width of the gate electrode, which reduces the short channel effect and leakage current.

Referring to FIG. 8, a spacer nitride layer (not shown) is deposited on the gate electrode 120, the second hard mask pattern 114a, and the gate oxide layer 108, and then anisotropically etched to form the gate electrode ( The spacer 122 is formed on sidewalls of the 120 and the second hard mask pattern 114a.

Next, by implanting impurities into the substrate on which the gate electrode 120 and the spacer 122 are formed, the source and the drain 124 are formed under the substrate surface on both sides of the gate electrode 120. The source and drain 124 may be disposed to face each other in a second direction perpendicular to the first direction. One portion of the source / drain is positioned under the upper surface of the substrate, and the other portion is positioned under the bottom of the recess portion. In this embodiment, the drain 124a is located below the upper surface of the substrate, and the source 124b is located below the bottom of the recess.

According to the method of the present embodiment, the recess portion can be formed using a mask pattern having a pitch twice the pitch of the gate electrode. Therefore, the margin of the photolithography process can be increased to reduce defects that may occur when forming recesses.

As described above, according to the present invention, the channel is formed under the substrate surface having the recessed portion, whereby a semiconductor device having a longer channel length than the line width of the gate electrode can be manufactured. As a result, the short channel effect and the leakage current in the MOS transistor of the semiconductor device can be reduced to improve operating characteristics.

In addition, it is possible to increase the margin during the photolithography process, thereby reducing process defects that may occur during the formation of the recess. For this reason, the improvement of the manufacturing yield of a semiconductor device can be anticipated.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (5)

Forming a mask pattern having a first pitch on the substrate; Forming a recess by partially etching the substrate using the mask pattern as an etching mask; Continuously forming a gate oxide film on surfaces of the substrate and the recess portion; Forming a gate conductive layer on the gate oxide layer to fill the recess; And By etching a portion of the gate conductive layer, a second sidewall having a second pitch equal to 1/2 of the first pitch and having a first sidewall disposed on a substrate and facing the first sidewall is formed on the bottom surface of the recess portion. Forming a gate electrode located thereon. The method of claim 1, wherein an inner width of the recess is 1.2 to 2.8 times the line width of the gate electrode. The method of claim 1, wherein the forming of the mask pattern comprises: Forming a mask film on the substrate; Forming a photoresist pattern on the mask layer twice the pitch of the gate electrode; And And etching the mask film by using the photoresist pattern as an etching mask. The method of claim 1, wherein the forming of the gate conductive layer comprises: Forming a preliminary first conductive layer filling the recess portion on the substrate; Polishing the preliminary first conductive film to form a first conductive film having an upper surface flattened thereon; And Forming a second conductive film on the first conductive film, the second conductive film having a lower resistance than the first conductive film. The method of claim 1, further comprising forming a source / drain region on a bottom surface of the substrate and the recessed portions positioned at both sides of the gate electrode.

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