KR20060119749A - Liquid crystal display device having charge sharing function and driving method thereof - Google Patents

Abstract

The present invention provides a liquid crystal display device having a charge sharing function suitable for reducing power consumption to a limit below.

In the above liquid crystal display, a pair of adjacent pixels along the data line on the liquid crystal panel charges pixel data voltages having polarities opposite to those of other adjacent pairs of pixels. By the charge sharing unit, the data lines share charge every time periods in which the pixel data voltage is supplied to adjacent pixels along the data line. The charge sharing unit is controlled by the charge sharing controller to selectively skip the charge sharing operation between periods in which the pixel data voltage is supplied to a pair of adjacent pixels along the data line.

As a result, the power consumed by the liquid crystal display is reduced to below the limit.

Description

Liquid crystal display device with a charge sharing function and driving method

In order to better understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram schematically showing a conventional liquid crystal display device.

2A and 2B are diagrams for explaining a one-dot-2 line inversion driving method.

FIG. 3 is a diagram illustrating a charge sharing unit included in the data driver of FIG. 1.

4 is a waveform diagram illustrating a pixel data voltage and a polarity signal for explaining a charge sharing scheme applied to the liquid crystal display of FIG. 1.

5 is a block diagram schematically illustrating a liquid crystal display device having a charge sharing function according to an exemplary embodiment of the present invention.

FIG. 6 is a detailed circuit diagram showing in detail the charge sharing controller shown in FIG.

FIG. 7 is a waveform diagram showing waveforms of signals output from respective parts shown in FIG. 6.

FIG. 8 is a table for explaining a logical operation result of the AND gate shown in FIG. 6.

<Brief description of the main parts of the drawing>

102: liquid crystal panel 104: gate driver

106: data driver 106A: charge sharing unit

108: timing controller 110: polarity controller

112: charge sharing controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof for allowing data lines to be charged sharing.

Liquid Crystal A conventional liquid crystal display device (hereinafter referred to as "LCD") controls the light transmittance of a liquid crystal so that an image corresponding to video data is displayed. As shown in FIG. 1, the liquid crystal display includes a liquid crystal panel 2 in which a plurality of gate lines GL1 to GLn and data lines DL1 to DLm are arranged to cross each other, and on the liquid crystal panel 2. A gate driver 4 for driving gate lines GL1 to GLn, a data driver 6 for driving data lines DL1 to DLm on the liquid crystal panel 2, and the gate driver 4 And a timing controller 8 for generating a gate control signal and a data control signal for controlling the data driver 6.

The plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm arranged to cross each other distinguish pixel areas. In each of these pixel regions, a pixel including a thin film transistor MT, a liquid crystal cell CLc, and a storage capacitor Cst is formed. The thin film transistor MT includes a gate electrode and a source electrode connected to a corresponding gate line GL and a corresponding data line, respectively. The liquid crystal cell CLc is connected between the drain electrode of the thin film transistor MT and the common electrode Vcom. The storage capacitor Cst is connected between the drain electrode of the thin film transistor MT and the previous gate line GLi-1. Alternatively, the storage capacitor Cst may be connected between the drain electrode of the thin film transistor MT and the common electrode Vcom.

The pixels on the liquid crystal panel 2 are driven by one of three driving methods, a frame inversion system, a line inversion system, and a dot inversion system. . The frame inversion scheme inverts the polarity of the pixel data voltage supplied to the pixel every time the frame is changed. In the line inversion method, the polarity of the pixel data voltage supplied to the pixel is inverted along a line on the liquid crystal panel 2, that is, a gate line. Finally, the dot inversion scheme causes any pixel to be supplied with a pixel data voltage of a polarity opposite to the pixel data voltages to be supplied to the pixels adjacent thereto. Furthermore, the line inversion method and the dot inversion method may be used in a form merged with the frame inversion method in which the polarity of the pixel data voltage to be supplied to the pixel is inverted for each frame.

In the dot inversion method among the three liquid crystal panel driving methods, a pixel data voltage having a polarity opposite to pixel data voltages to be supplied to adjacent pixels in the vertical and horizontal directions is supplied to an arbitrary pixel. Compared to the inversion method and the line inversion method, an image of superior quality is provided. Accordingly, recently, the liquid crystal panel is mainly driven by a dot inversion method.

The dot inversion method is a 1-dot-1 line inversion method in which the pixel data voltage changes every dot in the vertical direction, and the 1-dot-2 line inversion in which the polarity of the pixel data voltage is inverted every two dots along the vertical direction. It is divided in a manner. In the latter one-dot-2 line inversion scheme, as shown in Figs. 2A and 2B, the polarity of the pixel data voltage is inverted every one dot in the horizontal direction, but inverted every two dots in the vertical direction. This 1-dot-2 line inversion method is more flicker than the 1-dot-1 line inversion method when the LCD panel is driven at a frame frequency of 60 Hz (that is, when 60 images are displayed in one second). This reduces the cost.

The 1-dot-2 line inversion type liquid crystal display has a function of allowing data lines to share charges (hereinafter, referred to as a "charge sharing function"). The data driver 6 included in the liquid crystal display of the charge sharing function includes a plurality of buffers 10-1 to 10-m and a plurality of data lines DL1 to DLm. M first switches SW1-1 to SW1-m connected to each other and m-1 second switches SW2-1 to 1 connected between the plurality of data lines DL1 to DLm. SW2- (m-1)). Each of the plurality of buffers 10 supplies an analog pixel data voltage to a corresponding data line DL through a corresponding first switch SW1. The first switches SW1 and the second switches SW2 are turned on by a data output enable signal DOE, which is one of data control signals supplied from the timing controller 8. Turn-On). When the data output enable signal DOE is high (or low), the first switches SW1 are turned on while the second switches SW2 are turned off. Off). In contrast, when the data output enable signal DOE is low (or high), the first switches SW1 are turned off while the second switches SW2 are turned off.

For example, when the scan signal is supplied to the first gate line GL1 and the thin film transistors MT connected to the gate line GL1 are turned on and the data output enable signal DOE is high, Each of the plurality of buffers 10-1 to 10m supplies the pixel data voltage opposite to the adjacent buffers to the corresponding data line DL via the corresponding first switch SW1. Then, each of the thin film transistors MT connected to the first gate line GL1 is charged with the pixel data voltage on the corresponding data line DL to the corresponding liquid crystal cell CLc and the corresponding storage capacitor Cst. do.

In contrast, when the data output enable signal DOE is low, the second switches SW2 are turned on instead of the first switches SW1 so that the plurality of data lines DL1 to DLm are connected to each other. Then, charging and discharging of the voltage are simultaneously performed between the data lines DL charged with the pixel data voltage having the opposite polarity to the adjacent data lines DL. For example, negative pixel data voltages are charged in the odd-numbered data lines DL1, DL3, ..., DLm-1, and positive pixel data in the even-numbered data lines DL2, DL4, ..., DLm. When the voltage is charged, the odd-numbered data lines DL1, DL3, ..., DLm-1 charge the voltage from the adjacent even-numbered data lines DL2, DL4, ..., DLm, while the even-numbered data lines are charged. DL2, DL4, ..., DLm discharge the charged positive pixel data voltage toward adjacent odd-numbered data lines DL1, DL3, ..., DLm-1. As a result, charge sharing occurs so that all of the data lines DL1 to DLm are pre-charged to the intermediate level voltage between the positive pixel data voltage and the negative pixel data voltage. The charge sharing that causes the effect of pre-charging reduces power consumption of the data driver and the liquid crystal display.

Such charge sharing is performed whenever the gate line GL is changed (i.e., every period of the horizontal synchronizing signal) regardless of the polarity signal POL such as the waveforms of EGS-O and EGS-E of FIG. 4 ( Hereinafter referred to as " every line sharing scheme " or the waveforms of the EPE-O and EPE-E in FIG. 4 (i.e., every period of two horizontal synchronization signals) May be referred to as a "polar edge sharing scheme". The EGS-O and EGS-E of Fig. 4 are pixel data voltages and even-numbered data lines DL2, DL4,... Which are supplied to the odd-numbered data lines DL1, DL3,..., DLm-1 in every line sharing scheme. Are waveform diagrams illustrating examples of the pixel data voltage supplied to DLm). EPE-O and EPE-E, in the polar edge sharing scheme, the pixel data voltage and even-numbered data lines DL2, DL4, ..., DLm supplied to the odd-numbered data lines DL1, DL3, ..., DLm-1. Waveforms illustrating examples of pixel data voltages supplied to the waveforms. And POL describe the waveform of the polarity signal.

However, since the line sharing scheme allows charge sharing to be performed unnecessarily even when pixel data voltages of the same polarity and the same voltage level are continuous, power consumption cannot be reduced below the limit. In contrast to this, the polarity edge sharing scheme also cannot reduce the power consumption below the limit because charge sharing is not performed when pixel data voltages having different voltage levels are the same even though the polarities of the voltages are the same.

Accordingly, an object of the present invention is to provide a liquid crystal display device having a charge sharing function and a driving method thereof suitable for reducing power consumption below the limit.

According to an aspect of an exemplary embodiment, a liquid crystal display device includes: a liquid crystal panel in which pixels are arranged to be connected to corresponding gate lines and corresponding data lines; A data driver for driving data lines on the liquid crystal panel such that a pair of adjacent pixels along the data line charge a pixel data voltage having a polarity opposite to that of other adjacent pairs of pixels; And charge sharing means for selectively performing an operation of allowing the data lines to share charges between periods when a pixel data voltage is supplied to a pair of adjacent pixels along the data line.

The charge sharing means skips the charge sharing operation when the pixel data voltage to be supplied to the later pixel among the pair of adjacent pixels along the data line is the same as the pixel data voltage supplied to the pixel supplied to the preceding pixel. .

Said charge sharing means comprises: a plurality of switches connected between said data lines; On the basis of the pixel data to be supplied to the data driver, the switches are turned on every time interval between periods in which the pixel data voltage is supplied to adjacent pixels along the data line, but the pixel data voltage of the same polarity. When a pixel data voltage to be supplied to a later pixel among the pair of adjacent pixels corresponding to is supplied, a charge sharing controller may be configured to selectively turn on.

The charge sharing controller may include: generating a signal that generates an enable signal including an enable pulse that turns on the switches every time interval between periods in which a pixel data voltage is supplied to adjacent pixels along the data line; part; A first line memory for storing one line of pixel data supplied to the data driver; A second line memory for storing one line of data from the first line memory; A comparator for comparing pixel data stored in the first and second memories; A comparison component extraction unit for detecting a comparison component for pixel data to be supplied to a later pixel among a pair of adjacent pixels corresponding to pixel data voltages of the same polarity among the output signals of the comparator; And a pulse removing unit selectively removing the enable pulse to be supplied to the switches from the signal generator in accordance with a comparison component from the comparison component extraction unit.

The charge sharing controller may further include a synchronizer for causing an output signal of the comparator to be supplied to the comparison component extracting unit to be synchronized with a horizontal synchronizing signal. In this case, the synchronization unit preferably includes a flip-flop for latching the output of the comparator toward the comparison component extraction unit in response to the horizontal synchronization signal.

The comparison component extracting unit may include a logic operation element that extracts the comparison component in response to a sampling pulse having a frequency twice the polarity signal indicating the polarity of the pixel data voltage. In this case, the logic calculating element ANDs the output signal of the comparator and the sampling pulse.

The pulse removing unit may include a logic operation element that selectively removes an enable pulse from the signal generation unit in response to the comparison component from the comparison component extraction unit. In this case, it is preferable that the logic calculating element OR-operates the comparison component from the comparison component extraction section and the enable signal from the signal generation section.

In another embodiment, a liquid crystal display includes: a liquid crystal panel in which pixels are connected to a corresponding gate line and a corresponding data line; A data driver for driving data lines on the liquid crystal panel such that a pair of adjacent pixels along the data line charge a pixel data voltage having a polarity opposite to that of other adjacent pairs of pixels; A charge sharing unit for allowing the data lines to share charge every time period during which a pixel data voltage is supplied to adjacent pixels along the data line; And a controller configured to control the charge sharing unit to selectively skip the charge sharing operation between periods in which a pixel data voltage is supplied to a pair of adjacent pixels along the data line.

The third step is to skip the charge sharing operation when the pixel data voltage to be supplied to the later pixel among the pair of adjacent pixels along the data line is the same as the pixel data voltage supplied to the pixel supplied to the preceding pixel. It is preferable to include.

The third step may include: detecting a pixel data voltage to be supplied to a backward pixel, such as a pixel data voltage supplied to a preceding pixel, of a pair of adjacent pixels that respond to pixel data voltages of the same polarity based on the pixel data. Step 3-1; And detecting a pixel data voltage to be supplied to a later pixel, such as the pixel data voltage supplied to the preceding pixel, when the data lines are electrically separated from each other.

Step 3-1 may include: generating an enable signal including an enable pulse every temporal period between periods in which pixel data voltages are supplied to adjacent pixels along the data line; A step 3-1-2 of comparing pixel data of one line for pixels of a line to be driven with pixel data of one line of pixels of a previously driven line; Extracting a comparison component for pixel data to be supplied to a later pixel among a pair of adjacent pixels that respond to pixel data voltages having the same polarity among the comparison results of steps 3-1-2; And step 3-1-4 of selectively removing the enable pulse included in the enable signal according to the comparison component extracted in step 3-1-3.

The step 3-1-3 may include synchronizing the comparison result generated in the step 3-1-2 with the horizontal synchronization signal. In this case, the synchronizing step preferably includes latching the comparison result in response to the horizontal synchronizing signal.

Step 3-1-3 may include sampling the comparison result in response to a sampling pulse having a frequency twice the polarity signal indicating the polarity of the pixel data voltage. In this case, the sampling step preferably includes ANDing the comparison result and the sampling pulse.

Preferably, the step 3-1-4 includes performing an OR operation on the extracted comparison component and the enable signal.

A driving method of a liquid crystal display according to another exemplary embodiment of the present invention relates to a liquid crystal display including a liquid crystal panel in which pixels are arranged to be connected to corresponding gate lines and corresponding data lines. The driving method includes: a first step of supplying pixel data voltages to data lines on the liquid crystal panel such that a pair of adjacent pixels along the data line charge a pixel data voltage having a polarity opposite to that of other adjacent pairs of pixels; A second step of causing the data lines to share charge every period during which a pixel data voltage is supplied to adjacent pixels along the data line; And a third step of selectively skipping a charge sharing operation of the data lines between periods in which a pixel data voltage is supplied to a pair of adjacent pixels along the data line.

According to the above configuration, the liquid crystal display device having the charge sharing function and the driving method thereof according to the present invention, when the pixels on the backward (following) of the two adjacent lines driven with the same polarity is driven, The charge sharing operation is selectively omitted (ie skipped) depending on whether the current pixel data voltage to be supplied is equal to the previous pixel data voltage supplied to the pixels of the previous line. Accordingly, the power consumed by the data driver and the liquid crystal display including the same is reduced to below the limit.

According to the above configuration, the liquid crystal display device having the charge sharing function and the driving method thereof according to the present invention, when the pixels on the backward (following) of the two adjacent lines driven with the same polarity is driven, The charge sharing operation is selectively omitted (ie skipped) depending on whether the current pixel data voltage to be supplied is equal to the previous pixel data voltage supplied to the pixels of the previous line. Accordingly, power consumed by the data driver and the liquid crystal display including the same is reduced to below the limit.

In addition to the objects of the present invention as described above, other objects, other advantages and other features of the present invention will become apparent from the detailed description of the preferred embodiment with reference to the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention. Referring to FIG. 5, the liquid crystal display includes a gate driver 104 driving a plurality of gate lines GL1 to GLn on the liquid crystal panel 102, and a plurality of data lines DL1 to a liquid crystal panel 102. A data driver 106 for driving the DLm, and a timing controller 108 for generating a gate control signal and a data control signal for controlling the gate driver 104 and the data driver 106.

The plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm are formed to cross each other on the liquid crystal panel 102. The pixel regions are divided by the gate lines GL1 to GLn and the data lines DL1 to DLm. In each of the pixel regions, a pixel including the thin film transistor MT, the liquid crystal cell CLc, and the storage capacitor Cst is formed. The thin film transistor MT includes a gate electrode and a source electrode connected to a corresponding gate line GL and a corresponding data line, respectively. The liquid crystal cell CLc is connected between the drain electrode of the thin film transistor MT and the common electrode Vcom. The storage capacitor Cst is connected between the drain electrode of the thin film transistor MT and the previous gate line GLi-1. Alternatively, the storage capacitor Cst may be connected between the drain electrode of the thin film transistor MT and the common electrode Vcom.

The gate driver 104 sequentially and exclusively drives the gate lines GL1 to GLn on the liquid crystal panel 102. To this end, the gate driver 104 sequentially and exclusively applies the gate lines GL1 to GLn on the liquid crystal panel 102 in response to the gate control signal supplied from the timing controller 108 in a period of one horizontal synchronization signal. Supply n scan signals that are enabled. In other words, the gate driver 104 supplies the gate high voltage Vgh to the first to nth gate lines GL1 to GLn sequentially and alternately for each period of one horizontal synchronization signal.

The data driver 106 generates a plurality of data lines DL1 on the liquid crystal panel 102 whenever any one of the gate lines GL1 to GLn is enabled in response to the data control signal generated by the timing controller 108. DLm) to supply the pixel data voltages, respectively. To this end, the data driver 106 inputs pixel data VD for one line and converts pixel data VD for one line into an analog form according to the data control signal. Each of the converted pixel data voltages is supplied to the data line DL on the corresponding liquid crystal panel 102. Then, the thin film transistors MT connected to the enabled gate line GL are turned on so that the pixel data voltages on the corresponding data line DL are applied to the corresponding liquid crystal cell CLc and the storage capacitor Cst. Allow to charge

The timing controller 108 inputs the pixel data VD and the synchronization signals by one frame from an external video signal source (for example, a graphics card or a television signal recovery unit of a computer system), which is not shown. . The sync signals include a vertical sync signal Vsync, a horizontal sync signal Hsync, and a data clock Dclk. The timing controller 108 generates a gate control signal and a data control signal using the data clock Dclk and the horizontal and vertical synchronization signals Hsync and Vsync, and transmits pixel data to the data driver 106 by line. Supply. One line of pixel data VD supplied to the data driver 106 includes red, green, and blue pixel data.

The liquid crystal display of FIG. 5 further includes a polarity controller 110 connected to the data driver 106. The polarity controller 110 controls the polarity of the pixel data voltages output from the data driver 106 to the data lines DL1 to DLm on the liquid crystal panel 102 to be inverted according to the pixels in the horizontal and vertical directions.

For convenience of description, if the pixels on the liquid crystal panel 102 are driven in a 1-dot-2 line inversion manner, the polarity controller 110 generates a polarity signal POL which is inverted every cycle of the 2 horizontal synchronization signals. The polarity signal POL is supplied to the data driver 106. Then, in response to the polarity signal POL, the data driver 106 may have opposite polarities according to pixels in the horizontal direction and may be opposite to every two pixels in the vertical direction (that is, every two gate lines GL). The pixel data voltages having polarity are output.

For example, if the polarity signal POL has a high logic in the first and second horizontal synchronization periods of one frame, the polarity signal POL has a low logic in the third and fourth horizontal synchronization periods. In the first and second horizontal synchronizing periods during which the polarity signal POL maintains high logic (that is, the period in which the first and second gate lines GL1 and GL2 are enabled), the data driver 106 has an odd number. A positive pixel data voltage is output to each of the data lines DL1, DL3, ..., DLm-1, and a negative pixel data voltage is output to each of the even-numbered data lines DL2, DL4, ..., DLm. On the other hand, when the polarity signal POL has a low logic (that is, a period in which the third and fourth gate lines GL3 and GL4 are sequentially enabled), the data driver 106 performs the odd data line DL1. Negative pixel data voltages are respectively outputted to each of DL1, DL3, ..., DLm-1, and positive pixel data voltages are output to each of even-numbered data lines DL2, DL4, ..., DLm. As the logic value of the polarity signal POL is inverted for each period of the two horizontal synchronizing signals in this form, the pixel data voltages to be supplied to the remaining odd and even pixels are every two dots along the vertical direction (that is, Every two gate lines GL) have opposite polarities.

In the liquid crystal display of FIG. 5, the data driver 106 includes a charge sharing portion 106A connected to the data lines DL1 to DLm on the liquid crystal panel 102. The charge sharing unit 106A includes the data lines DL1 to DLm during the period in which the pixel data voltages are not supplied to the data lines DL1 to DLm (for example, the horizontal blanking period of the horizontal synchronization signal Hsync). Are connected to each other so that the data lines DL1 to DLm share a charge. Then, each of the data lines DL1 to DLm has positive (or negative) pixel data voltages on even-numbered data lines DL1, DL3,..., DLm-1, and even-numbered data lines DL2, It is precharged to a voltage of an intermediate level between the negative (or positive) pixel data voltages on DL4, ..., DLm. Accordingly, power consumption of the data driver 106 and the liquid crystal display including the same may be reduced.

To this end, the charge sharing unit 106A includes m first switches SW1 connected between each of the data lines DL1 to DLm and each of the output buffers as shown in FIG. 3, and the data lines. M-1 second switches SW2 connected between DL1 to DLm. The first switches SW1 are turned on when the data output enable signal DOE has high logic (ie, enabled) so that each of the pixel data voltages from the output buffers corresponds to a data line. To be supplied to (DL). In this case, the second switches SW2 are turned off so that the data lines DL1 to DLm are separated from each other. In contrast, when the data output enable signal DOE maintains low logic (ie, when disabled), the second switches SW2 are turned on instead of the first switches SW1 to turn on the data lines DL1 ˜. DLm) is connected to each other so that the data lines DL1 to DLm share a charge.

 Furthermore, the liquid crystal display according to the exemplary embodiment of the present invention further includes a charge sharing controller 112 connected between the timing controller 108 and the charge sharing unit 106A. The charge sharing controller 112 selects a charge sharing operation based on the pixel data VDi-1 of the previous line and the pixel data VDi of the current line supplied from the timing controller 108 to the data driver 106. The charge sharing unit 106A is controlled to be skipped. More specifically, when the pixel data voltages of the same level are supplied to the pixels on the two gate lines GL to be driven by the pixel data voltages of the same polarity, the charge sharing controller 112 may transfer the previous gate line GLi. -1) so that the charge sharing operation of the charge sharing unit 106A to be performed does not occur in the period between the period in which the pixel data voltages are supplied to the pixels on the pixel on the pixel on the subsequent gate line. The charge sharing unit 106A is controlled (to be skipped). On the other hand, the charge sharing controller 112, when the polarity of the pixel data voltages to be supplied to the data lines DL1 to DLm is inverted (that is, the logic state of the polarity signal POL is inverted), the charge sharing unit 112. The charge sharing unit 106A is controlled to perform the charge sharing operation of the 106A.

In order to control the charge sharing unit 106A in this manner, the charge sharing controller 112 includes the pixel data VD from the timing controller 108 and the horizontal synchronization signal Hsync and the polarity signal POL from the polarity controller 110. ) Is used to generate a charge sharing control signal CSCS to be supplied to the charge sharing section 106A. Alternatively, the charge sharing controller 112 may input the data output enable signal DOE instead of the horizontal sync signal Hsync. In this case, the charge sharing controller 112 controls the charge sharing based on the pixel data VD and the data output enable signal DOE from the timing controller 108 and the polarity signal POL from the polarity controller 110. Generate signal CSCS. The charge sharing control signal CSCS has a waveform in which some of the horizontal blanking pulses of a specific logic (eg, low logic) are removed from the horizontal sync signal Hsync, or a specific logic (eg, a data output enable signal). For example, some of the disable pulses (low logic) will have a removed waveform.

As such, when the pixel data voltages of the same level are supplied to the pixels on the two gate lines GL to be driven by the pixel data voltages of the same polarity, the charge sharing operation of the charge sharing unit 106A is skipped. The power consumption of the driver 106 and the liquid crystal display including the same can be reduced below the limit.

FIG. 6 is a detailed circuit diagram of the charge sharing controller 112 shown in FIG. 5 in detail. Referring to FIG. 6, the charge sharing controller 112 stores the first and second line memories 210A and 210B connected to the selection switch 200 and the first and second line memories 210A and 210B. A comparator 220 for comparing the pixel data, and a divider 230 for inputting a polarity signal POL from the polarity controller 110 of FIG. 5.

The selection switch 200 alternately transfers pixel data from the timing controller 108 shown in FIG. 5 to the first and second line memories 210A and 210B by one line. The switching operation of this T selection switch 200 is controlled by the twice-polarized polarity signal MPOL from the distributor 230. For example, when the polarized signal MPOL is a high (or low) logic, the selector switch 200 may output pixel data VDod of the odd-numbered line from the timing controller 108 to the first line memory 210. To feed. On the contrary, if the polarized signal MPOL is low (or high) logic, the selector switch 200 supplies the pixel data VDev of the even-numbered line from the timing controller 108 to the second line memory 210B. do. As a result, odd-numbered pixel data is temporarily stored in the first line memory 210A for one line, while even-numbered pixel data is temporarily stored in one line for the second line memory 210B.

The comparator 220 compares the odd-numbered pixel data VDod of one line stored in the first line memory 210A and the even-numbered pixel data VDev of one line stored in the second line memory 210B. A comparison signal having high or low logic is generated according to the comparison result. The comparison signal has a high (or low) logic when the odd-numbered pixel data VDod for one line and the even-numbered pixel data VDev for one line are the same, while the odd-numbered pixel data for one line is equal. If (VDod) and the even-numbered pixel data VDev for one line are not the same, it has a low (or high) logic. As a result, the comparator 220 compares the previous line pixel data for one line and the current line pixel data for one line and generates a comparison signal according to the comparison result.

In this regard, the selection switch 200 and the first and second line memories 210A and 210B may be replaced by only two line memories connected in series to the timing controller 108. In this case, pixel data of one current line is stored in the front line memory directly connected to the timing controller 108 among the two line memories connected in series, whereas the line memory of the next stage connected to the preceding line memory is stored in the line memory of the preceding line. Pixel data of one previous line may be temporarily stored. In this case, the comparator 220 may compare previous line pixel data of one line and current line pixel data of two lines from two line memories connected in series and generate a comparison signal according to the comparison result. . At this time, the comparison signal has a high (or low) logic when the current line pixel data of one line and the previous line pixel data of one line are the same, while the current line pixel data of one line and the previous line of one line are the same. Different pixel data has low (or high) logic.

The multiplier 230 which inputs the polarity signal POL from the polarity controller 110 generates a polarity signal MPOL which is synchronized with the polarity signal POL and doubled in frequency. This drained polarity signal MPOL has a low (or high) logic in the first half of each of the high logic period and the low logic period of the polarity signal POL, as shown in FIG. It is formed to have. In addition, each of the high logic period and the low logic period of the polarized polarity signal MPOL has a width corresponding to the period of one horizontal synchronization signal.

The charge sharing controller 112 of FIG. 6 further includes a flip-flop 240, an AND gate 250, and an OR gate 260 cascaded to the comparator 220. The flip-flop 240 transmits the comparison signal from the comparator 220 to the AND gate 250 in synchronization with the horizontal synchronization signal Hsync from the timing controller 108. To this end, the flip-flop 240 is a comparator 220 at the falling edge of the horizontal synchronization signal (Hsync) supplied from the timing controller 108 to its clock terminal (CLK) (that is, the start time of the horizontal blanking interval). Latches the comparison signal supplied from the input terminal D to the output terminal Q. Accordingly, the synchronized comparison signal SCS is supplied to the AND gate 250 as shown in FIG. 7. The flip-flop 240 which performs this operation detects the result of comparing the incomplete one line of previous line pixel data and the intact one line of current line pixel data among the comparison signals, and maintains it for the period of one horizontal sync signal. To be. This is because the time when all the corresponding line pixel data for one line is stored in each of the first and second line memories 210A and 210B corresponds to the start time of the horizontal blanking period.

Alternatively, the flip-flop 240 may respond to the data output enable signal DOE from the timing controller 108 instead of the horizontal sync signal Hsync. In this case, the flip-flop 240 is a comparator 220 at the falling edge of the data output enable signal DOE supplied from the timing controller 108 toward its clock terminal CLK (ie, the start point of the horizontal blanking period). Latches the comparison signal supplied to its input terminal D from the side toward the output terminal Q. Accordingly, even when the flip-flop 240 responds to the data output enable signal DOE and the comparison signal, as shown in FIG. 7, the synchronized comparison signal SCS may be generated in the flip-flop 240. have.

The AND gate 250 is one of pixels on two adjacent gate lines to be driven with pixel data voltages of the same polarity among the compared signal SCS synchronized using the polarized polarity signal MPOL from the divider 230. Only the comparison component is detected between the pixel data of the current line to be supplied to the pixels on the later (following) gate line and the pixel data of the previous line to be supplied to the pixels on the preceding (previous) gate line. In addition, the AND gate 250 selectively generates a Skip Control Pulse (SCS) having a specific logic (eg, high logic) in accordance with the result of the detected comparison component. To this end, the AND gate 250 ANDs the comparison signal SCS synchronized with the drained polarity signal MPOL. The skip control pulse SKP output from this AND gate 250 is set to high logic if both the polarized signal MPOL and the synchronized comparison signal SCS are high logic, as shown in the table shown in FIG. On the other hand, if either signal is low logic, it has low logic.

The OR gate 260 selectively removes the horizontal blanking pulse of the base logic included in the horizontal synchronization signal Hsync according to the logic state of the skip control pulse SKP from the AND gate 250 to charge-control the control signal CSCS. Will occur). Specifically, the period during which the skip control pulse SKP maintains a certain logic (i.e., high logic) (i.e., behind (or subsequent) of pixels on two adjacent gate lines GL driven with the same polarity. If the pixel data of the current line to be supplied to the pixels on the gate line is the same as the pixel data of the previous line supplied to the pixels on the preceding (or previous) gate line), the OR gate 260 is included in the horizontal sync signal. This causes the horizontal blanking pulse of the low logic to be removed. On the other hand, pixel data voltages are supplied to, or behind (or subsequent to) the pixels on the preceding gate line of the two adjacent gate lines GL driven with the same polarity (ie, the period during which the skip control pulse SKP maintains low logic. The pixel data (ie, pixel data of the current line) for the pixel data voltages to be supplied to the pixels on the gate line is the pixel data (ie, pixel data for the pixel data voltages supplied to the pixels on the preceding gate line). Different from the pixel data of the previous line), the OR gate 260 causes the horizontal synchronization signal Hsync to be output as it is without the horizontal blanking pulse of the low logic. To this end, the OR gate 260 ORs the skip control pulse SKP from the AND gate 250 and the horizontal synchronization signal Hsync from the timing controller 108. Accordingly, as shown in FIG. 7, the charge sharing control signal CSCS generated at the OR gate 260 has a waveform in which horizontal blanking pulses of low logic are selectively removed from the horizontal synchronization signal Hsync. .

Alternatively, the OR gate 260 may input the data output enable signal DOE from the timing controller 108 instead of the horizontal sync signal Hsync. In this case, the OR gate 260 ORs the skip control pulse SKP from the AND gate 250 and the data output enable signal DOE from the timing controller 108 and supplies the OR to the charge sharing unit 106A. Generate a charge sharing control signal (CSCS) to be. In other words, a period in which the skip control pulse SKP maintains a specific logic (i.e., high logic) (i.e., a later (following) gate line (of the pixels on two adjacent gate lines GL driven with the same polarity) When the pixel data VD to be supplied to the pixels on the GL is the same as the pixel data VD of the previous line to be supplied to the pixels on the previous gate line), the OR gate 260 is the data output enable signal DOE. Remove the disable logic pulses in row logic. On the other hand, the pixel data voltages are supplied to the pixels on the preceding gate line among the two adjacent gate lines GL driven with the same polarity or the pixels on the backward gate line during the period during which the skip control pulse SKP maintains the low logic. In the case where the pixel data VD of the current line to be supplied to is different from the pixel data of the previous line for the pixels on the previous gate line), the OR gate 260 does not remove the low logic disable pulse. The data output enable signal DOE is output as it is. Accordingly, the charge sharing control signal CSCS generated at the OR gate 260 responsive to the skip control pulse SKP and the data output enable signal DOE is displayed at a low logic level in the data output enable signal DOE. The enable pulse has a waveform that is selectively removed.

The charge sharing control signal CSCS generated at the OR gate 260 included in the charge sharing controller 112 is supplied to the charge sharing unit 106A included in the data driver 106. The charge sharing unit 106A, which responds to the charge sharing control signal CSCS, corresponds to a data line DL1 to DLm corresponding to one line of pixel data voltages according to the logic state of the charge sharing control signal CSCS. Via this, it is supplied to a corresponding pixel on one gate line GL or a charge sharing operation for precharging the data lines DL1 to DLm is performed.

First, when the charge sharing control signal CSCS maintains a high logic, the first switches SW1 included in the charge sharing unit 106A are turned on instead of the second switches SW2 so that the buffers 10 may be turned on. ) Are electrically connected to the corresponding data lines DL1 to DLm, respectively. Accordingly, each of the pixel data voltages output from the buffers 10 includes the liquid crystal cell CLc of the corresponding pixel on one of the gate lines GL enabled via the corresponding data lines DL1 to DLm, and The storage capacitor Cst is charged.

On the contrary, in the period of the low logic horizontal blanking pulse (or disable pulse) included in the charge sharing control signal, the second switches SW2 included in the charge sharing unit 106A are replaced with the first switches SW1. It is turned on to electrically connect the data lines DL1 to DLm. Accordingly, pixel data voltages charged with opposite polarities are charged and discharged on the odd-numbered data lines DL1, DL3,..., DLm-1 and the even-numbered data lines DL2, DL4, .., DLm. . As a result, all data lines DL1 to DLm have positive (or negative) pixel data voltages and even-numbered data lines on the odd-numbered data lines DL1, DL3, ..., DLm-1. The voltage at the intermediate voltage level (i.e., average voltage level) between the negative (or positive) pixel data voltages on DL2, DL4, ..., DLm is pre-charged. The precharge of the data lines DL1 to DLm due to charge sharing causes the voltage variation in the data lines DL1 to DLm according to the pixel data voltage to be small. As a result, power consumption of the data driver 106 and the liquid crystal display device is reduced.

The charge sharing unit 106A responsive to the charge sharing control signal CSCS includes periods in which pixel data voltages occupy between periods of supplying the data lines DL1 to DLm (ie, horizontal scanning periods). That is, the charge sharing operation to be performed every horizontal blanking periods) is intermittently filtered (i.e., intermittently skipped). In other words, the charge sharing unit 106A charges in the horizontal synchronizing period without a horizontal logic blanking pulse (or disable pulse) of low logic that divides the horizontal synchronizing period among the horizontal synchronizing periods in the charge sharing control signal CSCS. Do not perform a sharing operation. In other words, the charge sharing section 106A intermittently performs a charge sharing operation to be performed every horizontal synchronization period every two horizontal synchronization periods. Specifically, the current pixel data voltages to be supplied to the pixels on the later (or subsequent) gate line of the pixels on two adjacent gate lines driven by the pixel data voltages of the same polarity are the data lines ( In the horizontal synchronizing period supplied to DL1 to DLm, the charge is obtained when the pixel data voltages of the current line have the same voltage level as the pixel data voltages of the previous line supplied to the pixels on the preceding (or previous) gate line. The sharing operation will not be performed. Accordingly, all of the charges supplied to the data lines DL1 to DLm in the previous horizontal synchronizing period are used in the current horizontal synchronizing period, so that the voltage fluctuations on the data lines DL1 to DLm during the two horizontal synchronizing periods. There will be no. As a result, the power consumed by the data driver 106 and the liquid crystal display is further reduced than when the charge sharing operation is performed every horizontal synchronization period. In other words, since the charge sharing operation is intermittently skipped, the data driver 106 and the liquid crystal display according to the exemplary embodiment of the present invention can reduce power consumption to a limit or less.

As described above, the liquid crystal display of the charge sharing function and the driving method thereof according to the embodiment of the present invention are applied to the pixels when the pixels on the backward (following) line of two adjacent lines driven with the same polarity are driven. The charge sharing operation is selectively omitted (ie skipped) depending on whether or not the pixel data voltage to be supplied is equal to the previous pixel data voltage supplied to the previous pixel. Accordingly, the power consumed by the data driver and the liquid crystal display including the same is reduced to below the limit.

As described above, the present invention has been described with reference to the embodiments illustrated in the drawings, but it is only an example, and it will be appreciated by those skilled in the art to which the present invention pertains. In addition, it will be apparent to those skilled in the art that various modifications, changes, and equivalent embodiments may be made without departing from the spirit and scope of the present invention. Therefore, the spirit and scope of the present invention to be protected will be defined by the appended claims.

Claims (20)

A liquid crystal panel in which pixels are arranged to be connected to corresponding gate lines and corresponding data lines; A data driver for driving data lines on the liquid crystal panel such that a pair of adjacent pixels along the data line charge a pixel data voltage having a polarity opposite to that of other adjacent pairs of pixels; And And a charge sharing means for selectively performing an operation of allowing the data lines to share charges between periods in which a pixel data voltage is supplied to a pair of adjacent pixels along the data line. . 2. The charge sharing device according to claim 1, wherein the charge sharing means includes the charge when the pixel data voltage to be supplied to a later pixel among the pair of adjacent pixels along the data line is equal to the pixel data voltage supplied to a pixel supplied to the preceding pixel. A liquid crystal display device, wherein the sharing operation is skipped. The method of claim 1 wherein the charge sharing means is: A plurality of switches connected between the data lines; And On the basis of the pixel data to be supplied to the data driver, the switches are turned on every time interval between periods in which the pixel data voltage is supplied to adjacent pixels along the data line, but the pixel data voltage of the same polarity. And a charge sharing controller for selectively turning on when the pixel data voltage to be supplied to the lagging pixel among the adjacent pair of pixels corresponding to the second pixel is supplied. 4. The charge sharing controller of claim 3, wherein the charge sharing controller is: A signal generator configured to generate an enable signal including an enable pulse to turn on the switches every time interval between pixel periods in which pixel data voltages are supplied to adjacent pixels along the data line; A first line memory for storing one line of pixel data supplied to the data driver; A second line memory for storing one line of data from the first line memory; A comparator for comparing pixel data stored in the first and second memories; A comparison component extraction unit for detecting a comparison component for pixel data to be supplied to a later pixel among a pair of adjacent pixels corresponding to pixel data voltages of the same polarity among the output signals of the comparator; And And a pulse removing unit for selectively removing the enable pulse to be supplied to the switches from the signal generator in accordance with a comparison component from the comparison component extraction unit. 5. The liquid crystal display device according to claim 4, wherein the charge sharing controller further comprises a synchronizer for causing an output signal of the comparator to be supplied to the comparison component extracting unit to be synchronized with a horizontal synchronizing signal. 6. The liquid crystal display device according to claim 5, wherein the synchronizer includes a flip-flop for latching an output of the comparator toward the comparison component extractor in response to the horizontal synchronizing signal. 5. The logic unit as set forth in claim 4, wherein the comparison component extracting unit includes a logic calculating element for extracting the comparison component in response to a sampling pulse having a frequency twice the polarity signal indicating the polarity of the pixel data voltage. Liquid crystal display. 8. The liquid crystal display device according to claim 7, wherein the logic calculating element performs an AND operation on the output signal of the comparator and the sampling pulse. 5. The liquid crystal display device according to claim 4, wherein the pulse removing unit includes a logic operation element that selectively removes an enable pulse from the signal generating unit in response to the comparison component from the comparison component extracting unit. 10. The liquid crystal display device according to claim 9, wherein the logic operation element ORs a comparison component from the comparison component extraction section and an enable signal from the signal generation section. A method of driving a liquid crystal display device comprising a liquid crystal panel arranged such that pixels are connected to a corresponding gate line and a corresponding data line: Supplying pixel data voltages to data lines on the liquid crystal panel such that a pair of adjacent pixels along the data line charge a pixel data voltage having a polarity opposite to that of other adjacent pairs of pixels; A second step of causing the data lines to share charge every period during which a pixel data voltage is supplied to adjacent pixels along the data line; And And a third step of selectively skipping a charge sharing operation of the data lines between periods in which a pixel data voltage is supplied to a pair of adjacent pixels along the data line. Driving method. 12. The method of claim 11, wherein the third step is performed when the pixel data voltage to be supplied to a later pixel among the pair of adjacent pixels along the data line is equal to the pixel data voltage supplied to a pixel supplied to the preceding pixel. And skipping the sharing operation. The method of claim 11, wherein the third step is: Detecting a pixel data voltage to be supplied to a backward pixel, such as a pixel data voltage supplied to a preceding pixel, from among a pair of adjacent pixels corresponding to pixel data voltages of the same polarity based on the pixel data; And And when the pixel data voltage to be supplied to the backward pixel, such as the pixel data voltage supplied to the preceding pixel, is detected, maintaining the data lines in the electrically separated state. Method of driving the device. The method of claim 13, wherein step 3-1 comprises: Generating an enable signal including an enable pulse in each temporal section between periods in which a pixel data voltage is supplied to adjacent pixels along the data line; A step 3-1-2 of comparing pixel data of one line for pixels of a line to be driven with pixel data of one line of pixels of a previously driven line; Extracting a comparison component for pixel data to be supplied to a later pixel among a pair of adjacent pixels that respond to pixel data voltages having the same polarity among the comparison results of steps 3-1-2; And And driving step 3-1-4 of selectively removing the enable pulse included in the enable signal according to the comparison component extracted in step 3-1-3. Way. 15. The method of claim 14, wherein the step 3-1-3 includes synchronizing the comparison result generated in the step 3-1-2 with the horizontal synchronization signal. 16. The method of claim 15, wherein the synchronizing step comprises latching the comparison result in response to the horizontal synchronizing signal. 15. The method of claim 14, wherein the step 3-1-3 includes sampling the comparison result in response to a sampling pulse having a frequency twice the polarity signal indicating the polarity of the pixel data voltage. A drive method of a liquid crystal display device. 18. The method of claim 17, wherein the sampling comprises performing an AND operation on the comparison result and the sampling pulse. 15. The method of claim 14, wherein the step 3-1-4 comprises OR-operating the extracted comparison component and the enable signal. A liquid crystal panel in which pixels are arranged to be connected to corresponding gate lines and corresponding data lines; A data driver for driving data lines on the liquid crystal panel such that a pair of adjacent pixels along the data line charge a pixel data voltage having a polarity opposite to that of other adjacent pairs of pixels; A charge sharing unit for allowing the data lines to share charge every time period during which a pixel data voltage is supplied to adjacent pixels along the data line; And And a controller for controlling the charge sharing unit to selectively skip the charge sharing operation between periods in which a pixel data voltage is supplied to a pair of adjacent pixels along the data line.

Images