KR20060091491A - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

Depositing a first conductor layer and a second conductor layer on a substrate; photo-etching the first and second conductor layers to form a gate line including a gate electrode; and the first and second conductors in first and second regions. Forming a body, forming a gate insulating film on the gate line and the first and second conductors, forming a semiconductor layer on the gate insulating film, and forming an ohmic contact on the semiconductor layer, the Forming a source electrode and a drain electrode separated from each other by the same layer on the ohmic contact member, and a data line connected to the source electrode and intersecting the gate line, the first and second conductive portions formed in the at least first region; Forming a protective film having an opening area exposing the sieve, and etching the second metal film exposed through the opening area It is a manufacturing method of a transistor display panel.

Thin Film Transistor Display Board, 4 Masks, Bottom ITO

Description

Thin film transistor array panel and manufacturing method thereof

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II ',

3, 5, 7, and 9 are layout views of thin film transistor array panels at an intermediate stage of the method of manufacturing the thin film transistor array panels shown in FIGS. Drawing,

FIG. 4 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 3 taken along the line IV-IV ′.

FIG. 6 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 5 taken along the line VI-VI ′.

FIG. 8 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 7 taken along the line VIII-VIII ′.

FIG. 10 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 9 taken along the line 'VIII'.

<Description of the symbols for the main parts of the drawings>

110: substrate 121: gate line

129: gate pad 124: gate electrode

144: gate insulating film 154: semiconductor

164: ohmic contact 171: data line

173: source electrode 175: drain electrode

179: data pad 180: protective film

181: first contact hole 182: second contact hole

187: opening region 190: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array panel and a manufacturing method thereof, and more particularly, to a thin film transistor array panel for a liquid crystal display device and a manufacturing method thereof.

A thin film transistor (TFT) is used as a circuit board for independently driving each pixel in a liquid crystal display or an organic light emitting display (OLED).

The thin film transistor array panel includes a gate line transmitting a gate signal and a data line transferring a data signal, and includes a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and the like.

The thin film transistor includes a semiconductor layer forming a channel and a gate electrode connected to the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode with respect to the semiconductor layer.

The thin film transistor is a switching device that controls a data signal transmitted to a pixel electrode through a data line according to a gate signal transmitted through a gate line.

 However, in order to manufacture the thin film transistor array panel, several photolithography processes are required.

Each photolithography process includes a number of complex detailed processes, so the number of photolithography processes determines the time and cost of the thin film transistor array panel manufacturing process.

An object of the present invention is to simplify the manufacturing process of a thin film transistor array panel.

In order to solve the above problems, the present invention provides the following thin film transistor array panel and its manufacturing method.

More specifically, the step of depositing a first metal film and a second metal film on the substrate, the photo-etched the first and second metal film, the gate line including a gate electrode, and the first and second regions in the first, Forming a second conductor, forming a gate insulating film on the gate line and the first and second conductors, forming a semiconductor layer on the gate insulating film, and forming an ohmic contact on the semiconductor layer Forming a source electrode and a drain electrode separated from each other by the same layer on the ohmic contact member, and a data line connected to the source electrode and intersecting the gate line; Forming a protective film having an opening region exposing the second conductor, and etching the second metal film exposed through the opening region. Eojinda.

In the method of manufacturing the thin film transistor array panel, it is preferable that the first metal film is made of ITO or IZO, and the second metal film is made of a single layer or a double layer.

In addition, the second metal film is formed of Cr at the bottom, and an Al-based metal at the top, and the source electrode, the drain electrode, and the data line are made of a single layer of any one of Cr, Mo, Cr at the bottom, and Al at the top. It is preferable that it consists of a double layer of a series metal.

The first region is a predetermined region defined by the gate line and the data line, the second region is an end portion of the data line, and the drain electrode is formed of the first and second conductors formed in the first region. And the data line is in contact with the second conductor formed in the second region.

Further, in the forming of the passivation layer, a contact hole is formed to expose the first and second metal layers formed in the second region, and the second metal layer exposed through the opening region is exposed through the contact hole. The second metal layer is etched, and the gate insulating layer, the semiconductor layer, and the ohmic contact member have the same planar shape, and the gate insulating layer, the semiconductor layer, and the ohmic contact member have an island shape on the gate electrode. It is desirable to.

And forming the source electrode, the drain electrode, and the data line, by etching the ohmic contact exposed between the source electrode and the drain electrode.

On the other hand, a thin film transistor array panel according to an aspect of the present invention, a substrate, a gate line formed on the substrate, including a gate electrode, a first metal film and a second conductive formed in the first region and the second region A sieve, a gate insulating film formed on the gate line, a semiconductor layer formed on the gate insulating film, a source electrode and a drain electrode separated from each other by the same layer on the semiconductor layer, and connected to the source electrode, In a thin film transistor array panel including a passivation layer formed on an intersecting data line, the source electrode, the drain electrode, and the data line, and having an opening region exposing a first conductor formed in the at least first region. A predetermined area defined by the gate line and the data line, and the second area Is preferably the end of the data line.

Then, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity, and like reference numerals designate like parts throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along the line II-II ′.

A plurality of gate lines 121, a plurality of pixel electrodes 190, and a plurality of second conductors 179 are formed on the insulating substrate 110.

The gate line 121 mainly extends in the horizontal direction and transmits a gate signal. Each of the gate lines 121 is bent at a predetermined position, and has a wide area at the end portion having a large area for connection with a plurality of gate electrodes 124 located near the bent portion and another layer or an external driving circuit. 129).

The pixel electrode 190 is positioned in an area between the gate lines 121 and has a substantially rectangular shape.

The conductor 179 is positioned above the set of gate lines 121.

The gate line 121, the pixel electrode 190, and the conductor 179 at least partially include two layers having different physical properties, that is, a first conductor layer and a second conductor layer thereon. The first conductor layer is made of a transparent conductor such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The second conductor layer includes an upper layer and a lower layer, and the upper layer is formed of a low resistivity metal such as aluminum-based metal such as aluminum (Al) or aluminum alloy so as to reduce the delay or voltage drop of the gate signal. The lower layer is made of another material having good contact properties with the first conductor layer, such as molybdenum (Mo), molybdenum alloy (eg, molybdenum-tungsten (MoW) alloy), chromium (Cr), and the like. Preferred examples of the combination of the lower layer and the upper layer include two layers etched under different etching conditions such as a Cr layer and an Al layer (or an Al alloy layer), an Mo layer, and an Al layer (or an Al alloy layer).

In FIG. 2, the lower and upper layers of the first conductor layer and the second conductor layer of the gate electrode 124 are denoted by reference numerals 124p, 124q, and 124r, respectively, of the first conductor layer and the second conductor layer of the pixel electrode 190. The lower layer and the upper layer are denoted by reference numerals 190p, 190q, and 190r, respectively, and the lower and upper layers of the first conductor layer and the second conductor layer of the conductor 179 are indicated by reference numerals 179p, 179q, and 179r, respectively. have.

The pixel electrode 190 includes a single layer portion consisting of only the first conductor layer 190p and a multilayer portion including both the first and second conductor layers 190p, 190q, and 190r, and the single layer portion occupies most of the area. do. The second conductor 179 also includes a single layer portion composed of only the first conductor layer 179p and a multilayer portion including both the first and second conductor layers 179p, 179q, and 179r. Although not shown, the end portion of the gate line 129 also includes a single layer portion and a multilayer portion.

The second conductor layer may be made of a single layer, in which case it is preferably made of any one of Al, Cr, Mo.

Side surfaces of the gate electrode 124, the pixel electrode 190, and the conductor 179 are inclined, respectively, and the inclination angle is about 30-80 ° with respect to the surface of the substrate 110.

On the gate line 121, the pixel electrode 190, and the conductor 179, a plurality of island insulating gate insulating members 144 including silicon nitride (SiNx) are formed.

A plurality of semiconductors 154 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating member 144. A plurality of ohmic contacts 161 and 163 made of a material such as n + hydrogenated amorphous silicon in which silicide or n-type impurities are heavily doped is formed on the semiconductor 154.

The gate insulating member 144 has an island shape on the semiconductor 154 and has substantially the same planar shape on the gate electrode 124. The ohmic contacts 161 and 163 are positioned over the semiconductor 154 and have substantially the same planar shape as the gate insulating member 144 and the semiconductor 154 except for some.

Side surfaces of the gate insulating member 144, the semiconductor 154, and the ohmic contacts 161 and 163 are also inclined with respect to the surface of the substrate 110, and the inclination angle is 30-80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 including a source electrode 173 are formed on the ohmic contacts 161 and 163.

The data line 171 mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. One pixel electrode 190 is positioned in each region surrounded by the gate line 121 and the data line 171.

In each data line 171, a plurality of pairs of branches extending from both sides of the drain electrode 175 and portions therebetween form a source electrode 173. The pair of source electrodes 173 and the drain electrode 175 are separated from each other, and the ohmic contacts 161 and 163 at the bottom thereof are also separated from each other, but the semiconductor 154 is connected without being disconnected there.

The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the semiconductor 154, and the channel 200 of the thin film transistor includes a source electrode ( 173 and a portion of semiconductor 154 between drain electrode 175.

The drain electrode 175 contacts the second conductor layer of the multilayer part of the pixel electrode 190, and the data line 171 contacts the second conductor layer of the multilayer part of the conductor 179.

The data line 171 and the drain electrode 175 include lower metal films 171p and 175p made of refractory metal and upper metal films 171q and 175q made of low resistance metal. Preferred examples of the combination of the lower metal films 171p and 175p and the upper metal films 171q and 175q include two layers or a Mo lower film etched under different etching conditions such as a Cr lower film and an Al (alloy) upper film, and the like. Two layers of Al (alloy) upper film, etc. are mentioned. In FIG. 2, the lower metal film and the upper metal film of the source electrode 173 are denoted by reference numerals 173p and 173q, respectively.

Meanwhile, the data line 171 and the drain electrode 175 may be formed of a single layer or a triple layer. Examples of the data line 171 and the drain electrode 175 may include a single layer such as Cr, Al, Al-alloy, Mo, Mo-alloy, and Mo / Al /. Triple films, such as Mo, Mo / Al-alloy / Mo, Mo-alloy / Al / Mo-alloy, are mentioned.

Like the gate line 121, the data line 171, the source electrode 173, and the drain electrode 175 are also inclined at an angle of about 30 to 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 161 and 163 exist only between the semiconductor 154 below and the data line 171 and the drain electrode 175 thereon, and serve to lower the contact resistance therebetween.

On the upper portion of the data line 171 and the drain electrode 175 and the exposed semiconductor portion, that is, the channel portion 200, an organic material having excellent planarization characteristics and photosensitivity, plasma enhanced chemical vapor deposition And a passivation layer 180 made of a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or silicon nitride, which is an inorganic material, formed by PECVD.

In the passivation layer 180, a plurality of opening regions 187 exposing a single layer portion of the pixel electrode 190, a single layer portion of a gate pad 129 of the gate line 121, and a single layer portion of the conductor 179, respectively. A plurality of exposed contact holes 181, 182 are provided.

As described above, in the embodiment in which the passivation layer 180 has contact portions 182 and 181 exposing the end portions 179 and 129 of the data line 171 or the gate line 121, an external driving circuit may be formed using an anisotropic conductive layer. The data line 171 or the gate line 121 has a contact portion for connecting to the data line 171 or the gate line 121, and as shown in FIG. 1, the data line 171 or the gate line 121 is illustrated. End portions 179 and 129 may have a wider width than the data line 171 or the gate line 121 as necessary.

In addition, the boundary line between the end portion 129 of the gate line 121 and the conductor 179 is located outside the boundary lines of the contact holes 181 and 182.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the second conductor layers 190q and 190r on the multilayer part to receive a data voltage from the drain electrode 175. The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules between the two electrodes by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which the common voltage is applied. Let's do it.

In addition, the pixel electrode 190 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off. There is another capacitor connected in parallel with the capacitor, which is called a storage capacitor (not shown).

The storage capacitor is made by overlapping the pixel electrode 190 with another gate line 121 adjacent thereto (referred to as a prior gate line) or a storage electrode formed separately. The storage electrode (not shown) is made of the same layer as the gate line 121 and is separated from the gate line 121 to receive a voltage such as a common voltage. In order to increase the capacitance of the storage capacitor, that is, the capacitance, the area of the overlapped portion is increased or the conductor connected to the pixel electrode 190 and overlapped with the front gate line or the storage electrode under the protective film 180 is disposed between the two. You can get close.

The first conductor layers 129 and 179p exposed through the first and second contact holes 181 and 182 of the gate line 121 and the end portions 129 and 179 of the data line 171 are the same as the driving integrated circuit. Glued with external device.

According to another exemplary embodiment of the present invention, a transparent conductive polymer may be used as the material of the pixel electrode 190, and in the case of a reflective liquid crystal display, an opaque reflective metal may be used.

Next, a method of manufacturing the thin film transistor array panel for the liquid crystal display device illustrated in FIGS. 1 and 2 according to an embodiment of the present invention will be described in detail with reference to FIGS. 3 to 10, and FIGS. 1 and 2.

3, 5, 7, and 9 are layout views of thin film transistor array panels at an intermediate stage of the method of manufacturing the thin film transistor array panels shown in FIGS. 4 is a cross-sectional view of the thin film transistor array panel of FIG. 3 taken along line IV-IV ', and FIG. 6 is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along line VI-VI'. 8 is a cross-sectional view of the thin film transistor array panel of FIG. 7 taken along the line VIII-VIII ′, and FIG. 10 is a cross-sectional view of the thin film transistor array panel of FIG. 9 taken along the line VIII-VIII.

First, as illustrated in FIGS. 3 and 4, three conductive layers are sequentially deposited on the insulating substrate 110 made of transparent glass or the like by sputtering, and then the three conductive layers are formed by a photolithography process using a photosensitive film pattern. The body layers are sequentially patterned to form a plurality of gate lines 121 including a plurality of gate electrodes 124, a plurality of pixel electrodes 190, and a plurality of conductors 179.

It is preferable that the first conductor layers 121p, 190p, and 179p have a thickness of 400 GPa to 500 GPa as IZO, ITO, a-ITO, or the like.

When the material of the first conductor layers 121p, 190p, and 179p is IZO, a product called indium x-metal oxide (IDIXO) manufactured by Idemitsu, Japan may be used as a target, and may include In ₂ O ₃ and ZnO. The content of zinc in the total amount of indium and zinc is preferably in the range of about 15-20 atomic%. In addition, the sputtering temperature of IZO, ITO, a-ITO is preferably 250 ° C or less in order to minimize contact resistance. IZO can be etched with a weak acid such as oxalic acid.

The second conductor layer is deposited to have a thickness of 1,000 kPa to 3,000 kPa. For example, the lower layers 121q, 190q, and 179q may be formed of a metal having excellent contact properties with IZO, ITO, or a-ITO, for example, molybdenum and molybdenum. It is preferable that the alloy or chromium or the like have a thickness of about 500 kPa, and the upper films 121r, 190r, and 179r have an aluminum-based metal of about 1,000 kPa to 3,000 kPa, preferably about 2,500 kPa.

The patterning of the upper films 121r, 190r, and 179r, which are aluminum-based metals, is CH ₃ COOH (8-15%) / HNO ₃ (5-8%) / It is possible to proceed with wet etching using H ₃ PO ₄ (50 to 60%) / H ₂ O (rest), and when the lower layer (121q, 190q, 179q) is molybdenum or molybdenum alloy, the side slope is changed under the same etching conditions. Can be etched while giving.

The first conductor layers 121p, 190p, and 179p may proceed by dry etching or wet etching, and may be etched together with the lower layers 121q, 190q, and 179q, which are second conductor layers, or an upper layer of the second conductor layer. It may be etched together with the (121r, 190r, 179r) and the lower layer (121q, 190q, 179q).

Next, as shown in FIGS. 5 and 6, a three-layer film of a gate insulating film, intrinsic amorphous silicon, and an impurity amorphous silicon layer is chemical vapor deposition (CVD), or the like. It is deposited continuously.

As the material of the gate insulating film, silicon nitride is preferable, and the lamination temperature is preferably about 250 to 500 DEG C, and the thickness is about 2,000 to 5,000 GPa.

In addition, it is preferable that the thickness of an intrinsic amorphous silicon layer and an impurity amorphous silicon layer is 500 kV-1,500 kPa, and 300 kPa-600 kPa, respectively.

Subsequently, the gate insulating layer, the intrinsic amorphous silicon layer, and the impurity amorphous silicon layer are etched and patterned in an island shape on the gate electrode 124.

The lower metal films 171p, 173p, and 175p, which are conductive layers such as metal, and the upper metal films 171q, 173q, and 175q, are deposited to a predetermined thickness by a sputtering method, and then patterned and separated from each other in the same layer. The source electrode 173 and the drain electrode 175 and the data line 171 connected to the source electrode 173 and intersecting the gate line 121 are formed.

Thereafter, the ohmic contact 164 of the channel part 200 positioned between the source electrode 173 and the drain electrode 175 is etched.

In this way, the source electrode 173, the drain electrode 175, and the ohmic contact member patterns 161 and 163 below are separated to complete the channel portion 200.

Subsequently, an oxygen plasma treatment is preferably performed to stabilize the surface of the exposed portion of the intrinsic semiconductor layer 154.

The lower metal films 171p, 173p, and 175p are made of Cr, Mo, Mo-alloy, or the like. Preferably, the thickness is about 500 kPa, and the upper metal films 171q, 173q, and 175q are made of aluminum or an aluminum alloy, and preferably have a thickness of about 2500 kPa.

In this embodiment, Al-Nd alloy containing aluminum or 2 atomic% Nd is suitable as a target material of the upper metal films 171q, 173q, and 175q made of Al-Nd, and sputtering temperature is preferably about 150 ° C. .

Next, as shown in FIGS. 9 and 10, an inorganic insulating film such as silicon nitride or an organic insulating film having a low dielectric constant is deposited or coated to form a protective film 180, and a photosensitive film (not shown) is applied thereon. Next, the passivation layer 180 is patterned by a photolithography process using a mask (not shown) to form an area defined by the gate line 121 and the data line 171 and an end portion of the gate line 121 (gate pad). A plurality of opening regions 187 and first and second contact holes 181 and 182 exposing 129 and an end portion (data pad) 179 of the data line are formed.

In this case, the opening region 187 and the second contact hole 182 are the first conductor layer defined by the gate line 121 and the data line 171, and the second conductor layer of the end portion (data pad) 179 of the data line. (190r, 179r).

In addition, an upper layer (not shown) of the second conductor layer of the end portion 129 of the gate line 121 is also exposed.

Next, the upper layers 190r and 179r and the lower layers 190q and 179q of the second conductor layer exposed through the opening region 187 and the second contact hole 182 are sequentially etched to form the first conductor layer 190p, 179p).

Similarly, the upper layer and the lower layer (not shown) of the second conductor layer exposed through the first contact hole 181 are also etched to expose the lower first conductor layer (not shown).

In this case, the boundary line between the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 is outside the boundary lines of the first and second contact holes 181 and 182, referring to FIG. 9. Located in

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, the thin film transistor array panel and the method of manufacturing the same according to the present invention eliminate the separate photolithography process for forming the pixel electrode by forming the gate line including the pixel electrode and the gate electrode through one mask and thus, the entire process. Can be simplified.

Therefore, manufacturing time and cost of the thin film transistor array panel can be reduced.

Claims (11)

Depositing a first and a second conductor layer on the substrate, Photo-etching the first and second conductor layers to form a gate line and a pixel electrode; Forming a gate insulating film on at least a portion of the gate line, Forming a semiconductor layer on the gate insulating film, Forming an ohmic contact on the semiconductor layer, Forming a drain electrode in contact with the pixel electrode and a data line crossing the gate line on the ohmic contact; Forming a protective film having an opening region at least partially exposing a second conductor layer of the pixel electrode; Removing the portion of the second conductor layer exposed through the opening region, Method of manufacturing a thin film transistor array panel comprising a. In claim 1, And the first conductor layer comprises ITO or IZO. In claim 1, And the second conductor layer is a double layer. In claim 3, The second conductor layer may include a Cr lower layer and an Al upper layer. The method of claim 1 or 4, The drain electrode and the data line may be formed of a single layer including any one of Cr and Mo, or a double layer including a Cr lower layer and an Al upper layer. In claim 1, And forming a conductor connected to the data line in the gate line and the pixel electrode forming step. In claim 6, Forming a contact hole at least partially exposing the conductor in the forming of the passivation layer, And etching the second conductor layer exposed through the contact hole in the etching of the second conductor layer exposed through the opening region. In claim 1, And the gate insulating film, the semiconductor layer, and the ohmic contact member have the same planar shape. In claim 1 or 8, The gate line includes a gate electrode, the data line includes a source electrode, The gate insulating layer, the semiconductor layer, and the ohmic contact may be formed in an island shape on the gate electrode. Thin film transistor array panel. In claim 9, In the forming of the drain electrode and the data line And etching the ohmic contact exposed between the source electrode and the drain electrode. Board, A gate line formed on the substrate and including a gate electrode, A pixel electrode formed on the substrate and separated from the gate line; A conductor formed on the substrate and separated from the gate line and the pixel electrode; A gate insulating film formed on the gate line, A semiconductor layer formed on the gate insulating film, A source electrode and a drain electrode formed on the semiconductor layer and separated from each other, and a data line connected to the source electrode and crossing the gate line, A passivation layer formed on the source electrode, the drain electrode, and the data line and having an opening region exposing at least a portion of the pixel electrode. Including; The pixel electrode has at least a portion of a multilayer structure, and the pixel electrode portion exposed by the opening region has a single layer structure.

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