KR20060069173A - Method of manufacturing thin film transistor array panel - Google Patents

Abstract

A method of manufacturing a thin film transistor array panel according to the present invention includes forming a semiconductor including an intrinsic region and an impurity region on a substrate, forming a gate insulating film on the semiconductor, and forming a gate line overlapping the intrinsic region on the gate insulating film. Forming an interlayer insulating film covering the gate line and the gate insulating film; forming a data line formed on the interlayer insulating film and connected to the impurity region; and forming an output electrode on the interlayer insulating film so as to be separated from the data line and connected to the impurity region. Forming a light emitting layer; stacking first and second passivation layers covering the output electrode and the data line; exposing and developing a predetermined area of the second passivation layer to expose the first passivation layer; and etching the exposed first passivation layer. Step, curing the second protective film, is connected to the output electrode on the second protective film And forming a pixel electrode rock.

Thin film transistor, protective film, contact hole, curing

Description

Manufacturing method of thin film transistor array panel {MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY PANEL}

1 is a layout view of a polysilicon thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along the line II-II'-II ".

3 is an enlarged partial view of region A of FIG. 2.

4A is a layout view at an intermediate stage of the method of manufacturing the thin film transistor array panel shown in FIGS. 1 and 2 according to an embodiment of the present invention.

4B is a cross-sectional view of the thin film transistor array panel of FIG. 4A taken along line IVb-IVb′-IVb ″.

5A is a layout view of a thin film transistor array panel in the next step of FIG. 4A.

FIG. 5B is a cross-sectional view of the thin film transistor array panel of FIG. 5A taken along a line Vb-Vb′-Vb ″.

FIG. 6 is a cross-sectional view of the thin film transistor array panel of FIG. 5B taken along the line Vb-Vb′-Vb ″ of FIG. 5A.

FIG. 7A is a layout view of a thin film transistor array panel in the next step of FIG. 6.                 

FIG. 7B is a cross-sectional view of the thin film transistor array panel of FIG. 7A taken along the line VIIb-VIIb′-VIIb ″.

8A is a layout view of a thin film transistor array panel in the next step of FIG. 7A.

FIG. 8B is a cross-sectional view of the thin film transistor array panel of FIG. 8A taken along the line VIIIb-VIIIb′-VIIIb ″.

FIG. 9 is an enlarged partial view of B of FIG. 8B.

* Description of symbols on the main parts of the drawings *

110: insulating substrate 121: gate line

124: gate electrode 140: gate insulating film

151: semiconductor 171: data line

173: input electrode 175: output electrode

190: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistor array panels, and more particularly to thin film transistor array panels comprising polycrystalline silicon.

In general, a thin film transistor (TFT) is used as a switching element for driving each pixel independently in a flat panel display such as a liquid crystal display or an organic light emitting display. The thin film transistor array panel including the thin film transistor includes a scan signal line (or gate line) that transmits a scan signal to the thin film transistor, a data line that transmits a data signal, and the like, in addition to the thin film transistor and the pixel electrode connected thereto.

The thin film transistor includes a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode connected to the pixel electrode, and a semiconductor positioned on the gate electrode between the source electrode and the drain electrode. The data signal from the data line is transferred to the pixel electrode in accordance with the scanning signal of.

The pixel electrode and the drain electrode are electrically connected to each other through a contact hole formed in the protective film. The protective film may be formed of a single layer or a plurality of layers, and may be formed by including an inorganic film therebetween in order to improve the adhesion between the organic film and the lower film.

In the case of forming the double layer of the inorganic film and the organic film as described above, undercut occurs under the organic film due to the characteristic difference between the inorganic film and the organic film. In order to remove the undercut, the inorganic film and the organic film are patterned by separate photolithography processes, or the occurrence of the undercut is reduced by using high density anisotropic etching rather than low plasma density isotropic etching.

However, when the inorganic film and the organic film are etched separately, the process becomes complicated and the anisotropic etching has a problem in that the production cost increases because the apparatus is expensive compared to the isotropic etching. SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a thin film transistor array panel in which a process is simplified and a production cost is not increased.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor array panel, the method including forming a semiconductor including an intrinsic region and an impurity region on a substrate, forming a gate insulating layer on the semiconductor, and overlapping the intrinsic region on the gate insulating layer. Forming a gate line; forming an interlayer insulating film covering the gate line and the gate insulating film; forming a data line formed on the interlayer insulating film and connected to an impurity region; and separating the data line on the interlayer insulating film. Forming an output electrode connected to the impurity region, laminating first and second passivation layers covering the output electrode and the data line, exposing and developing a predetermined region of the second passivation layer to expose the first passivation layer, and exposing Etching the first passivation layer, curing the second passivation layer, and second beam Film and forming a pixel electrode so that on the connection with the output electrode.

The method may further include the step of the ashing process after the curing step.

In the step of removing the first passivation layer, the etching is performed at 60 ± 6 mm / 250 ± 25 mT / 500 ± 50 W / SF ₆ with 100 ± 10 and O ₂ with 100 at electrode / substrate spacing / chamber pressure / power / injection gas / etching time. It is preferable to proceed at a condition of ± 10 sccm and He of 450 ± 45 sccm / 50 ± 5 seconds.

In addition, the ashing process has an electrode and substrate spacing, chamber pressure, power, injection gas, and etching time of 40 ± 4 mm / 1700 ± 170 mT / 1700 ± 170 W / O ₂ of 750 ± 75 sccm and He of 350 ± 35 sccm / 60 ± 6 seconds. It is preferable to proceed under conditions.

In addition, the curing step preferably proceeds for about 1 hour at about 230 ℃.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

A thin film transistor array panel according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

First, a polysilicon thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view of a polysilicon thin film transistor array panel according to an exemplary embodiment of the present invention, FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along the line II-II′-II ″, and FIG. A partial enlarged view showing the area A of 2 at an enlarged scale.

A blocking film 111 made of silicon oxide (SiO ₂ ), silicon nitride (SiNx), or the like is formed on the transparent insulating substrate 110. The blocking film 111 may have a multilayer structure.

On the blocking film 111, a plurality of island-like semiconductors 151 made of polycrystalline silicon are formed. The island-like semiconductor 151 is formed to be horizontally long, and both ends thereof may be formed to have an extended width for contacting the upper conductive layer.

Each semiconductor 151 includes an impurity region containing conductive impurities and an intrinsic region containing little conductive impurities, and a heavily doped region having a high impurity concentration in the impurity region. There is a lightly doped region with low concentrations of impurities.

The intrinsic region includes two channel regions 154a and 154b that are spaced apart from each other. The high concentration impurity region includes a plurality of source / drain regions 153, 155, and 157 separated from each other with respect to the channel regions 154a and 154b.

The low concentration impurity regions 152a and 152b located between the source / drain regions 153, 155 and 157 and the channel regions 154a and 154b are called lightly doped drain regions (LDD regions) and have a width. Narrower than other areas                     

Examples of the conductive impurity include P-type impurities such as boron (B) and gallium (Ga) and N-type impurities such as phosphorus (P) and arsenic (As). The lightly doped regions 152a and 152b prevent leakage current or punch through from the thin film transistor, and the lightly doped regions 152a and 152b are free of impurities. ) Can be replaced with an area.

A gate insulating layer 140 of hundreds of thicknesses of silicon nitride or silicon oxide is formed on the semiconductor 151 and the blocking layer 111.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 extending in the horizontal direction are formed on the gate insulating layer 140.

The gate line 121 transmits a gate signal, and a portion of the semiconductor 151 protrudes upward and includes a plurality of protrusions overlapping the channel regions 154a and 154b of the semiconductor 151. As such, a portion of the gate line 121 overlapping the channel regions 154a and 154b is used as the gate electrodes 124a and 124b of the thin film transistor. The gate electrodes 124a and 124b may also overlap the lightly doped regions 152a and 152b.

One end portion of the gate line 121 may have a large area in order to connect to another layer or an external driving circuit, and when a gate driving circuit (not shown) generating a gate signal is integrated on the substrate 110. The gate line 121 may be directly connected to the gate driving circuit.

The storage electrode line 131 is positioned between the two gate lines 121 and is adjacent to the lower side of the two gate lines 121. The storage electrode line 131 includes the storage electrode 133 extending in the vertical direction to the vicinity of the upper gate line 121, and applies a predetermined voltage such as a common voltage applied to a common electrode (not shown). Receive.

The gate line 121 and the storage electrode line 131 may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based metal such as copper (Cu) or copper alloy, Molybdenum-based metals such as molybdenum (Mo) and molybdenum alloy, chromium (Cr), tantalum (Ta), titanium (Ti) and the like. However, the gate line 121 may have a multilayer structure including two conductive layers (not shown) having different physical properties.

One of these conductive films is a low resistivity metal such as an aluminum-based metal, a silver-based metal, or a copper-based metal so as to reduce signal delay or voltage drop of the gate line 121 and the storage electrode line 131. It may be made of a metal. The other conductive layer may be formed of a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metal, chromium, tantalum, titanium, or the like. A good example of such a combination is a chromium bottom film and an aluminum top film, and an aluminum bottom film and a molybdenum top film.

Side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110 so that the upper thin film can be smoothly connected.

An interlayer insulating film 160 is formed on the gate line 121, the storage electrode line 131, and the gate insulating layer 140. The interlayer insulating layer 160 is an organic material having excellent planarization characteristics and photosensitivity, a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or the like formed by plasma chemical vapor deposition, or It may be formed of an inorganic material such as silicon nitride. A plurality of contact holes 163 and 165 exposing the outermost source / drain regions 153 and 155 are formed in the interlayer insulating layer 160 and the gate insulating layer 140, respectively.

A plurality of date lines 171 and a plurality of output electrodes 175 are formed on the interlayer insulating layer 160 to intersect the gate line 121.

Each data line 171 includes an input electrode 173 connected to the source / drain region 153 through the contact hole 163. One end of the data line 171 may have a large area in order to connect to another layer or an external driving circuit. Line 171 may be directly connected to the data driving circuit. The storage electrode 133 is positioned between two adjacent data lines 171.

The output electrode 175 is separated from the input electrode 173 and connected to the source / drain region 155 through the contact hole 165.

The data line 171 and the output electrode 175 are preferably made of a refractory metal such as molybdenum, chromium, tantalum, titanium, or an alloy thereof. However, they may also have a multilayer structure including a conductive film having a low resistance and a conductive film having good contact characteristics, such as the gate line 121. Examples of the multilayer film structure include a triple film of molybdenum film, aluminum film, and molybdenum film in addition to the above-described double film of chromium lower film and aluminum upper film or aluminum lower film and molybdenum upper film.                     

Side surfaces of the data line 171 and the output electrode 175 may also be inclined with respect to the substrate 110 surface.

Passivation layers 180a and 180b are formed on the data line 171, the output electrode 175, and the interlayer insulating layer 160. The passivation layers 180a and 180b may include the first passivation layer 180a and the second passivation layer 180b, the first passivation layer 180a may be formed of an inorganic material such as silicon nitride, and the second passivation layer 18b may be easily planarized. It consists of one organic substance and the like. The passivation layers 180a and 180b include a plurality of contact holes 185 exposing the output electrode 175 and a plurality of contact holes 182 exposing one end of the data line 171.

On the passivation layer 180b, a pixel electrode 190 and a contact auxiliary member 82 made of a transparent conductive material such as IZO (indium zinc oxide) or ITO (indium tin oxide), or an opaque reflective conductive material such as aluminum or silver ) Is formed.

The pixel electrode 190 is connected to the output electrode 175 connected to the source / drain region 155 through the contact hole 185 to receive a data voltage from the source / drain region 155 and the output electrode 175.

The contact assistant 82 serves to protect the adhesiveness between the end portion of the data line 171 and the external device. The pixel electrode 190 to which the data voltage is applied generates an electric field together with the common electrode to which the common voltage is applied, thereby determining the direction of the liquid crystal molecules of the liquid crystal layer (not shown) between the two electrodes or the light emitting layer between the two electrodes. Current) to emit light.

In the case of the liquid crystal display, the pixel electrode 190 and the common electrode form a capacitor (hereinafter, referred to as a 'liquid crystal capacitor') to maintain an applied voltage even after the thin film transistor is turned off. To do this, another capacitor connected in parallel with the liquid crystal capacitor is provided, which is called a storage capacitor. The storage capacitor is made by overlapping the storage electrode line 131 including the pixel electrode 190 and the storage electrode 133. The storage electrode 133 may not be formed depending on the amount of storage power required.

The pixel electrode 190 overlaps with the data line 171 to improve the aperture ratio.

Next, a method of manufacturing the thin film transistor array panel shown in FIGS. 1 to 3 will be described in detail with reference to FIGS. 1 to 3 along with FIGS. 4A to 9.

FIG. 4A is a layout view at an intermediate stage of the method of manufacturing the thin film transistor array panel shown in FIGS. 1 and 2 according to the embodiment of the present invention, and FIG. 4B is the IVb-IVb′-IVb ″ view of the thin film transistor array panel of FIG. 4A; 5A is a layout view of a thin film transistor array panel in the next step of FIG. 4A, and FIG. 5B is a cross-sectional view cut along the line Vb-Vb′-Vb ″ of FIG. 5A. 6 is a cross-sectional view of the thin film transistor array panel of FIG. 5B taken along the line Vb-Vb-Vb ″, and FIG. 7A is a cross-sectional view of the thin film transistor array panel of the next stage of FIG. 5B. FIG. 7B is a cross-sectional view of the thin film transistor array panel of FIG. 7A taken along the line VIIb-VIIb′-VIIb ″, and FIG. 8A is a layout view of the thin film transistor array panel in the next step of FIG. 7A. 8B is a cross-sectional view of the thin film transistor array panel of FIG. 8A taken along a line VIIIb-VIIIb'-VIIIb ″, and FIG. 9 is an enlarged partial view of B of FIG. 8B.

First, as shown in FIGS. 4A and 4B, the blocking layer 111 is formed on the transparent insulating substrate 110, and then, as amorphous silicon by chemical vapor deposition (CVD), sputtering, or the like. The semiconductor film 150 thus formed is formed.

Next, the semiconductor film 150 is crystallized by laser annealing, furnace annealing, or sequential lateral solidification (SLS).

The semiconductor film 150 is patterned to form a plurality of island-like semiconductors 151, and a gate insulating layer 140 is formed thereon by a chemical vapor deposition method.

As shown in FIGS. 5A and 5B, a metal film is stacked on the gate insulating layer 140 by sputtering and the photoresist pattern PR is formed. The metal film is etched using the photoresist pattern PR to form a plurality of gate lines 121 including the gate electrode 124 and a plurality of storage electrode lines 131 including the storage electrode 137.

In this case, the etching time is sufficiently long so that the boundary line between the gate line 121 and the storage electrode line 131 is positioned inside the photoresist pattern PR.

Subsequently, N-type or P-type impurity ions are implanted at high concentration into the island-type semiconductor 151 using the photoresist pattern PR as an ion implantation mask to form source / drain regions 153, 155, and 157, which are high concentration impurity regions.

Next, as shown in FIG. 6, after removing the photoresist pattern PR, the island-type semiconductor 151 is doped with low concentration of N-type or P-type impurity ions using the gate line 121 and the storage electrode line 131 with an ion implantation mask. Thus, a plurality of low concentration impurity regions 152a and 152b are formed. In this way, the region under the gate electrode 124 positioned between the source region 153 and the drain region 155 becomes the channel region 154.

The low concentration impurity regions 152a and 152b may be formed by using metal films having different etching ratios in addition to the photoresist pattern described above, or by forming spacers on sidewalls of the gate line 121 and the storage electrode line 131. have.

7A and 7B, a plurality of contact holes 163 and 165 exposing the source region and the drain region 153 and 155 by stacking the photo interlayer insulating layer 160 on the entire surface of the substrate 110 and etching the photo, respectively. To form.

Next, a plurality of data lines 171 and a plurality of drain electrodes having a source electrode 173 connected to the source region 153 and the drain region 155 through contact holes 163 and 165 on the interlayer insulating layer 160, respectively. 175 is formed.

As shown in FIGS. 8A and 8B, an inorganic material such as silicon nitride (SiNx) is stacked on the entire surface of the substrate 110 to form a first passivation layer 180a, and a second passivation layer is formed by stacking an organic material having photosensitivity. To form 180b.

Next, a portion of the second passivation layer 180b is removed by exposing the first passivation layer 180a. Thereafter, the first passivation layer 180a exposing the second passivation layer 180b as a mask is removed to form contact holes 185 and 182 exposing end portions of the output electrode 175 and the data line 171, respectively. Etch conditions include electrode and substrate spacing / chamber pressure / power / injection gas / etching time 60 ± 6mm / 250 ± 25mT / 500 ± 50W / SF ₆ 100 ± 10, O ₂ 100 ± 10sccm, He 450 ± 45sccm / 50 ± 5 seconds. Here, the etching surfaces of the first passivation layer 180a and the second passivation layer 180b have a stepped profile, and the upper portion of the first passivation layer 180a is partially exposed. In this case, the width of the exposed first passivation layer 180a is referred to as D1.

Finally, as shown in FIGS. 1 to 3, a curing process is performed to cure the second passivation layer 180b. At this time, since the second passivation layer 180b flows down to cover a part of the first passivation layer 180a, the distance of D2 shown in FIG. 9 is reduced as in D1 shown in FIG. The curing process proceeds for about 1 hour at a temperature of about 230 ° C.

In this case, when the second passivation layer 180b completely covers the first passivation layer 180a, an ashing process may be further performed. Conditions for ashing process include electrode and substrate spacing / chamber pressure / power / injection gas / etching time substrate spacing / chamber pressure / power / injection gas / etching time 40 ± 4mm / 1700 ± 170mT / 1700 ± 170W / O ₂ 750 ± 75 sccm, He should be 350 ± 35 sccm / 60 ± 6 seconds. . Thereafter, a plurality of pixel electrodes 190 connected to the output electrode 175 are formed on the passivation layer 180 through a contact hole 185 using a transparent conductive material such as IZO or ITO.

 As described above, when the first and second passivation layers are etched and cured, the formation of the undercut and the stepped profile may be minimized, thereby improving contact characteristics between the upper conductive layer and the lower conductive layer.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (5)

Forming a semiconductor including an intrinsic region and an impurity region on the substrate, Forming a gate insulating film on the semiconductor, Forming a gate line overlapping the intrinsic region on the gate insulating layer; Forming an interlayer insulating film covering the gate line and the gate insulating film; Forming a data line on the interlayer insulating layer and connected to the impurity region; Forming an output electrode on the interlayer insulating layer, the output electrode being separated from the data line and connected to the impurity region; Stacking first and second passivation layers covering the output electrode and the data line; Exposing and developing a predetermined area of the second passivation layer to expose the first passivation layer, Etching the exposed first passivation layer; Curing the second passivation layer, And forming a pixel electrode on the second passivation layer so as to be connected to the output electrode. In claim 1, And performing the ashing process after the curing step. In claim 1, In the step of removing the first passivation layer, the etching may be performed at an interval of 60 ± 6 mm / 250 ± 25 mT / 500 ± 50 W / SF ₆ with 100 ± 10 and O ₂ with an electrode and a substrate gap / chamber pressure / power / injection gas / etch time. A manufacturing method of a thin film transistor array panel in which 100 ± 10sccm, He proceeds at 450 ± 45sccm / 50 ± 5 seconds. In claim 2, The ashing process is performed at an electrode and substrate spacing / chamber pressure / power / injection gas / etch time of 40 ± 4 mm / 1700 ± 170 mT / 1700 ± 170 W / O ₂ at 750 ± 75 sccm and He at 350 ± 35 sccm / 60 ± 6 seconds. The manufacturing method of a thin film transistor display panel which advances. In claim 1, The curing step of manufacturing a thin film transistor array panel proceeds for about 1 hour at about 230 ℃.

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