KR20060057308A - Thin film transistor substrate, method of manufacturing same, and liquid crystal display panel comprising same - Google Patents

Abstract

A thin film transistor substrate comprising a gate wiring, a data wiring formed having an intersection area with the gate wiring, and an active layer interposed between the gate wiring and the data wiring, wherein the active layer crosses the intersection. And an extension part formed over at least one side of both sides of the data line in the longitudinal direction in the region. As a result, it is possible to increase the success rate of CVD repair for the step-opening caused by the step difference between the gate wiring and the data wiring.

Description

A thin film transistor substrate, a method of manufacturing the same, and a liquid crystal display panel including the same, and a liquid crystal display panel including the same.

1 is a layout view of a thin film transistor substrate according to the prior art,

2 is a cross-sectional view taken along the line II-II of FIG.

3 is a cross-sectional view of a liquid crystal display panel according to the present invention;

4 is a layout view of a thin film transistor substrate according to the present invention;

5 is a cross-sectional view taken along the line VV of FIG. 4,

6 to 9 are cross-sectional views sequentially illustrating steps of manufacturing a thin film transistor substrate according to the present invention.

* Explanation of symbols for the main parts of the drawings

1: second substrate 5: liquid crystal layer

10 second insulating substrate 20 gate wiring

22: gate pad 24: gate electrode

26: gate line 29, 39: extension

30 gate insulating film 40 active layer

42 semiconductor layer 45 resistive contact layer                 

50: data wiring 51: data wiring

52,56: source electrode 53: data pad

54 drain electrode 60 protective film

70: metal layer 68,72,74: contact hole

100: pixel electrode 200: first substrate

210: first insulating substrate 220: black matrix

230: color filter 240: overcoat layer

250: common electrode

The present invention relates to a thin film transistor substrate, a method of manufacturing the same, and a liquid crystal display panel including the same, and more particularly, to a thin film transistor having a reduced level difference in an intersecting region of mutually insulated metal lines, and a method of manufacturing the same. The present invention relates to a liquid crystal display panel including the same.

A liquid crystal display panel displays a desired image by adjusting light transmittance of liquid crystal cells arranged in a matrix form according to image signal information. The liquid crystal display panel is interposed so as to face the thin film transistor substrate, the color filter substrate including a color filter, a black matrix, an overcoat layer, and a common electrode to be opposite to the thin film transistor substrate, and injected between the thin film transistor substrate and the color filter substrate. It includes a liquid crystal.

In general, a thin film transistor (TFT) substrate is used as a circuit board for independently driving each pixel in a liquid crystal display (LCD), an organic luminescence (EL) display, and the like. The thin film transistor substrate includes an active layer including scan signal wires or gate wires for transmitting a scan signal, image signal lines or data wires for transmitting an image signal, and a semiconductor layer and an ohmic contact layer interposed between the gate wires and the data wires. Is formed.

The thin film transistor substrate includes a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, a gate insulating film covering and insulating the gate line, and a protective film covering and insulating the thin film transistor and the data line.

The thin film transistor includes a gate electrode that is a part of the gate wiring, an active layer including an island-like semiconductor layer and an ohmic contact layer formed on the gate electrode, a source electrode and a drain active that are part of the data wiring, a gate insulating film, a protective film, and the like. The thin film transistor is a switching device that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.

The process of manufacturing a thin film transistor substrate includes a gate process in which a gate metal is laminated and patterned on an insulating substrate to form a gate wiring, an active process in which a semiconductor layer and an ohmic contact layer are laminated and patterned, and a pixel process in which a pixel electrode is stacked and patterned. And a data process of stacking and patterning data metal to form a source and a drain, a process of forming a channel and a passivation layer, and an inspection process.

In the gate process of manufacturing the thin film transistor substrate, when the environmental particles (fine particles, dust, etc.) are present on the deposited gate metal layer, the photosensitive material is not applied or thinly applied to the region where the environmental particles are present. Alternatively, the photosensitive material may be applied locally thin even without environmental particles. In the process of etching the gate metal layer to pattern the gate wiring because the photosensitive material is not applied to the region in which the environmental particles exist, the gate wiring is also etched and broken like the region a shown in FIG. 2. However, disconnection of the gate wiring can be repaired by a chemical vapor deposition (CVD) method.

However, when the defect is generated in the intersection area where the gate wiring and the data wiring cross, there is a problem in that the success rate of CVD repair decreases due to the step formed by each layer. As shown in the regions g and h of FIGS. 1 and 2, the source electrode branched from the data line is formed to be in contact with the outer surface of the active layer, resulting in a step formed by the active layer and the data line. Therefore, as shown in areas (b) and (c) of FIG. 2, the step layer of the metal layer deposited for repairing the disconnected gate wiring is weak due to the step, resulting in a step open that is broken by the infiltration of the etchant. There is a problem. Alternatively, cracks may occur due to film stress caused by a step, and the metal layer may be stepped open, resulting in low CVD repair success rate.

Accordingly, an object of the present invention is to provide a thin film transistor substrate having a high success rate of CVD repair for a step-open caused by a step between a gate wiring and a data wiring, and a manufacturing method thereof.

The object is a thin film transistor substrate comprising a gate wiring, a data wiring formed to have an intersection area with the gate wiring, and an active layer interposed between the gate wiring and the data wiring, wherein the active layer is formed as described above. It is achieved by a thin film transistor substrate comprising an extension formed over at least one side of both sides in the longitudinal direction of the data line in the cross region.

        Here, it is preferable that the said active layer is formed in the area | region of the said gate wiring.

        The gate line may include a gate line, and a gate electrode having a width of a line increased at the intersection area of the gate line and the data line, wherein the active layer is positioned on the gate electrode, and the extension part is disposed on the gate line. It is preferably located on the line.

        The data line may include a data line and a source electrode branched from the data line and formed in a J or U shape, and the extension part extends in an outward direction of the source electrode.

In addition, the above object is a method of manufacturing a thin film transistor substrate, comprising the steps of: forming a gate wiring on an insulating substrate; Forming an active layer on the gate wiring; And forming a data line on the active layer, the data line having a cross region with the gate line, wherein the active layer has a length direction of the data line in the cross region. It is achieved by a method for manufacturing a thin film transistor substrate, characterized in that it has an extension formed over at least one side of both sides.

        Here, the active layer is preferably manufactured to be formed in the gate wiring region.

In addition, the above object, the first substrate; A second substrate disposed opposite the first substrate and including a gate wiring, a data wiring formed to have an intersection area with the gate wiring, and an active layer interposed between the gate wiring and the data wiring; A liquid crystal display panel including liquid crystal injected between the first substrate and the second substrate, wherein the active layer includes an extension part formed over at least one side of both sides of a length direction of the data line in the cross region. It is achieved by the liquid crystal display panel characterized by the above-mentioned.

Here, it is preferable that the said active layer is formed in the area | region of the said gate wiring.

The gate line may include a gate line, and a gate electrode having a width of a line increased at the intersection area of the gate line and the data line, wherein the active layer is positioned on the gate electrode, and the extension part is disposed on the gate line. It is preferably located on the line.

The data line may include a data line and a source electrode branched from the data line and formed in a J or U shape, and the extension part extends in an outward direction of the source electrode.

Hereinafter, a thin film transistor substrate according to the present invention, a method of manufacturing the same, and a liquid crystal display panel including the same will be described with reference to the accompanying drawings. The same parts as in the prior art will be described with the same reference numerals.

The liquid crystal display panel includes a color filter substrate (hereinafter referred to as a first substrate), a thin film transistor substrate (hereinafter referred to as a second substrate) attached to face the color filter substrate, and a first substrate and a second substrate. It includes a liquid crystal injected into.

As shown in FIG. 3, the first substrate 200 is formed in a stripe or lattice shape to have an opening region on the first insulating substrate 210 made of an insulating material such as glass, quartz, ceramic, or plastic. The black matrix 220, the red, green, and blue color filters 230 formed in the opening regions of the black matrix 220, respectively, and the overcoat layer sequentially stacked on the black matrix 220 and the color filter 230 ( 240 and the common electrode 250.

As shown in FIGS. 5 and 6, the second substrate is formed by depositing a gate metal on a second insulating substrate 10 made of an insulating material such as glass, quartz, ceramic, or plastic, and then patterning the gate metal. The wiring 20 is formed. The gate wiring 20 may be formed as a single layer or may be formed as a double layer or more. The reason for forming the gate wirings in multiple layers is to compensate for the disadvantages of each metal or alloy and to obtain desired physical properties. Taking the double layer as an example, the first gate wiring layer includes aluminum or an aluminum alloy, and the second gate wiring layer includes chromium. In other words, aluminum or aluminum alloy with small specific resistance is used to prevent signal resistance due to wiring resistance as the lower layer, and to protect the disadvantages of aluminum or aluminum alloy where corrosion resistance by chemicals is weak and easily oxidized due to oxidization. At least one selected from chromium, molybdenum, molybdenum-tungsten, and molybdenum-tungsten nitride having high corrosion resistance to chemicals is used.

The gate line 20 has a gate pad 22 formed at one end of the branched gate electrode 24 and the gate line 26 by increasing the width of the gate line 26 and a portion of the gate line 26 extending in the horizontal direction. It consists of).

Here, when the environmental particles (fine particles, dust, etc.) are present on the deposited gate metal layer, the photosensitive material is not applied or thinly applied to the region where the environmental particles are present. Alternatively, the photosensitive material may be applied locally thin even without environmental particles. In the process of etching the gate metal layer to pattern the gate wiring 20 because the photosensitive material is not applied to the region in which the environmental particles exist, the gate wiring 20 is also etched and broken like the region a shown in FIG. 5. . However, when the defect is detected in the inspection step of the second substrate, it can be repaired by a chemical vapor deposition (CVD) method.

Here, the CVD method involves reacting a gaseous compound on a heated base surface and depositing a product on the base surface. After fabrication of the second substrate, disconnection as shown in the region a of FIG. 5 may be detected by the environmental particles described above in the inspection step. In order to repair the disconnected gate wiring, as shown in FIG. 9, a metal layer 70 such as tungsten is laminated by the CVD method. The metal layer 70 stacked on the upper part while melting the passivation layers 60, 62, 64 and the gate insulating layers 30, 32, 34 by irradiating a laser to the e region and the f region with the disconnected portion of the gate wiring in the center thereof. It is melted into the hole formed by the laser. Thus, the disconnected gate wiring is connected by the metal layer 70 to repair the defect. However, there is a problem in that the success rate of CVD repair is low because the metal layer 70 is broken due to a step formed by several layers stacked below.

The above problem is solved by changing the pattern of the active layer 40 which will be described later.

A gate insulating layer 30 made of silicon nitride (SiNx) is formed on the gate wiring 20 to cover the gate wiring 20.

A semiconductor layer 42 made of a hydrogenated amorphous silicon semiconductor is formed on the gate insulating layer 30, and on the semiconductor layer 42, an amorphous silicon having a high concentration of n-type impurities such as phosphorus (P) is doped. An ohmic contact layer 45 is formed. The semiconductor layer 42 and the ohmic contact layer 45 are referred to as an active layer 40. The gate insulating layer 30, the semiconductor layer 42, and the ohmic contact layer 45 are successively deposited, and the active layer 40 including the semiconductor layer 42 and the ohmic contact layer 45 is patterned to form a gate electrode ( 24) island-shaped. The ohmic contact layer 45 serves to lower the contact resistance between the lower semiconductor layer 42 and the upper data line 50.

In the intersecting region of the gate wiring 20 and the data wiring 50, in particular, on the gate electrode 24, a layer composed of the semiconductor layer 42, the ohmic contact layers 44, 48 and the source electrodes 52, 56 is too large. A high level | step difference is formed and the above-mentioned problem arises. Therefore, in the present invention, extension portions 29 and 39 are formed in which the active layer including the semiconductor layer and the ohmic contact layer extends both outer surfaces in the longitudinal direction of the data line. It is preferable that the extensions 29 and 39 are in the gate wiring area, in particular, the active layer is located on the gate electrode and the extensions 29 and 39 are located on the gate line. The extensions 29 and 39 form a stepped shape between the active layer 40 and the source electrodes 52 and 58. Therefore, even when the metal layers 70 for repairing the disconnection of the gate wiring 20 are stacked, the level difference is low, thereby preventing the disconnection of the metal layer 70 due to the weakness of the film stress or the layer covering. In particular, since the inclination is formed smoothly due to the properties of the material of the active layer 40, the effect of compensating the step is further increased.

The data metal is laminated on the island-like active layer 40 and formed of the data wiring 50. The data line 50 may also be formed of one material or may be formed of a multilayer such as a double layer as in the above-described gate line 20. The data line 50 may be formed of the same metal as the above-described gate line 20 as well as another metal material.                     

The data line 50 is formed in the vertical direction, and is connected to the data line 51 and the ends of the data line 51, and receives the image signal from the outside and transmits the image signal to the data line 51. And the source electrodes 52 and 56 of the thin film transistor, which are branches of the data line 50, and the drain electrode 54 of the thin film transistor, which is separated from the data line 51. The source electrodes 52 and 56 on the gate electrode 24 are branched in a J or U shape on the data line, and the drain electrode 54 separated from the data line 52 is inside the source electrodes 52 and 56. Is formed.

As shown in the cross-sectional view of FIG. 5, the source electrodes 52, 56 in the longitudinal direction of the data line and the extensions 29, 39 of the active layer 40 form a step shape. That is, the extensions 29 and 39 of the active layer 40 are formed longer than the outer surfaces of the source electrodes 52 and 56 by a predetermined length to compensate for the step difference. Meanwhile, the ohmic contact layer 45 in the region forming the channel portion is formed in the same shape as the source electrodes 52 and 56 and the drain electrode 54.

On the other hand, the semiconductor layer 42 is formed in a stepped shape forming a layer with the data line 50 in the same manner as the ohmic contact layers 44, 46, and 48 except for the channel portion of the thin film transistor. Specifically, in the channel portion of the thin film transistor, the data wires 42 are separated from the source electrodes 52 and 56 and the drain electrode 54, and the ohmic contacts 44, 46 and 48 are also the source electrodes 52 and 56. ) And the drain electrode 54 are formed separately from each other. However, the semiconductor layers 42 are connected to each other without being cut off to form channels of the thin film transistors.

A protective film made of an a-Si: C: O film or an a-Si: O: F film (low dielectric constant CVD film) or an organic insulating film deposited by silicon nitride or plasma enhanced chemical vapor deposition (PECVD) on the data line 50. 60 is formed. The protective film 60 has a drain electrode 54 and contact holes 74 and 68 exposing a part of the data pad 53, and also has a contact hole 72 exposing a part of the gate pad 22.

The pixel electrode 100 is formed on the passivation layer 60 to receive an image signal from the thin film transistor and generate an electric field together with the common electrode of the upper plate. The pixel electrode 100 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and is physically and electrically connected to the drain electrode 54 through a contact hole 74 to receive an image signal. Receive. The pixel electrode 100 overlaps with the neighboring gate line 26 and the data line 51 to increase the aperture ratio but may not overlap.

On the other hand, on the gate pad 22 and the data pad 53, a contact auxiliary member (not shown) connected to the external circuit device, the gate wiring 20, and the data wiring 50 through contact holes 72 and 68, respectively, is provided. Is formed. The contact assist member (not shown) is not essential to supplement the adhesion between the end portion and the external circuit device and to protect the gate pad 22 and the data pad 53, and their application is optional. to be.

Hereinafter, a brief description will be given of a method for manufacturing a second substrate having the structure of FIGS. 4 and 5 according to the present invention.

6 to 9 are cross-sectional views sequentially showing steps for manufacturing a second substrate according to the present invention.

As shown in FIG. 6, a gate metal is deposited on the first insulating substrate 10 and then subjected to a photolithography process, and includes a gate line 26, a gate pad 22, and a gate electrode 24. The wiring 20 is formed. For example, a double-filled gate wiring is formed by depositing a low resistance aluminum or aluminum alloy on an insulating substrate to form a first gate wiring layer, and in chromium, molybdenum, molybdenum-tungsten, and molybdenum-tungsten nitride having excellent physical and chemical properties. At least one selected is deposited to deposit a second gate wiring layer, and then the gate wiring is formed through a photolithography process as described above.

As described above, there is a problem in that the gate wiring 20 is disconnected as shown in region a of FIG. 5 due to environmental particles or the like. However, when the defect is detected at the inspection step, it can be compensated by the CVD repair method described above.

Next, as shown in FIG. 7, a gate insulating film, a semiconductor layer, and an ohmic contact layer made of silicon nitride (SiNx) are successively deposited to a thickness of using chemical vapor deposition. Here, the gate insulating film 30 is 1,500 kPa to 5.000 kPa, the semiconductor layer 42 is 500 kPa to 2000 kPa, the ohmic contact layer 45 is continuously deposited to a thickness of 300 to 600 kPa, and the semiconductor layer 42 is resistive. The contact layer 45 is etched to form an island-like semiconductor layer 42 and an ohmic contact layer 45 on the gate electrode 24 and the gate insulating layer 30.

Here, in the present invention, extension portions 29 and 39 are formed in which the active layer including the semiconductor layer and the ohmic contact layer extends both outer surfaces in the longitudinal direction of the data line. Preferably, the extensions 29 and 39 are in the gate wiring area, particularly the active layer is on the gate electrode and the extensions 29 and 39 are on the gate line. The extensions 29 and 39 form a stepped shape between the active layer 40 and the source electrodes 52 and 58. Therefore, even when the metal layers 70 for repairing the disconnection of the gate wiring 20 are stacked, the level difference is low, thereby preventing the disconnection of the metal layer 70 due to the weakness of the film stress or the layer covering. In particular, since the inclination is formed smoothly due to the properties of the material of the active layer 40, the effect of compensating the step is further increased.

Subsequently, as shown in FIG. 8, the data metal layer is stacked, patterned by a photolithography process using a mask, connected to the data line 51 and the data line 51 crossing the gate line 26, and the gate electrode. (24) Separated from J or U-shaped source electrodes 52, 56 and source electrodes 52, 56 extending to the upper part, and located inside the source electrodes 52, 56 around the gate electrode 24. The data line 50 including the drain electrode 54 is formed. The source electrodes 52 and 56 and the drain electrode 54 are stacked to have a thickness of 2500 kPa to 3000 kPa. The source electrodes 52 and 56 form a step shape together with the active layer 40 to compensate for the step difference.

Subsequently, the ohmic contact layer 45 leaves the above-described extension 29 through a mask process, and the other portions are formed by etching in shapes similar to the source electrodes 52 and 56 and the drain electrode 54. The semiconductor layer 42 is exposed between the source electrode and the drain electrode to form a channel portion. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 42, it is preferable to perform an oxygen plasma.

Next, as shown in FIG. 9, the silicon nitride film, the a-Si: C: O film or the a-Si: O: F film is grown by chemical vapor deposition (CVD) or an organic insulating film is applied to protect the protective film 60. ).

Next, as shown in FIGS. 4 and 5, the passivation layer 60 is patterned together with the gate insulating layer 30 by a photolithography process to form the gate pad 22, the drain electrode 54, and the data pad 53. Forming contact holes 72, 74, 68 are formed.

Next, an ITO or IZO film is deposited and photo-etched to pass through the gate pad 22 and the data pad through the pixel electrode 100 and the contact holes 72 and 68 connected to the drain electrode 54 through the contact hole 74. 53, contact auxiliary members (not shown) respectively connected to each other are formed. The gas used in the pre-heating process before laminating ITO or IZO is preferably nitrogen.

Thereafter, the second substrate is inspected for defects. If there is no defect, a liquid crystal is injected between the prepared first substrate and the second substrate, and then the liquid crystal display panel is completed.

When a defect such as disconnection of the gate wiring occurs in the inspection step, as shown in FIG. 9 with the disconnected portion of the gate wiring stacked, a metal layer such as tungsten is laminated, and then irradiated with laser on the e region and the f region. As the protective layers 60 and 62 and the gate insulating layers 30 and 32 are melted, the metal layers 70 stacked thereon are melted into holes formed by the laser. Thus, the disconnected gate wiring is connected by the metal layer 70 to repair the defect. In addition, the step is lowered due to the extension of the active layer, thereby preventing the disconnection of the metal layer 70, thereby increasing the CVD repair success rate.

 As described above, according to the present invention, in the second substrate having the metal interconnects intersecting with each other, the structure of the intersecting region is improved to increase the success rate of CVD repair for the step-open caused by the step difference between the gate interconnection and the data interconnection. Can

Claims (10)

A thin film transistor substrate comprising a gate wiring, a data wiring formed having an intersection area with the gate wiring, and an active layer interposed between the gate wiring and the data wiring, And the active layer includes an extension part formed over at least one side of both side surfaces of the data line in the cross region.         The method of claim 1,         And the active layer is formed in a region of the gate wiring.         The method of claim 1,         The gate line includes a gate line and a gate electrode having a line width increased at the intersection area of the gate line and the data line,         The active layer is positioned on the gate electrode and the extension portion is located on the gate line.         The method of claim 1,         The data line includes a data line and a source electrode branched from the data line and formed in a J or U shape.         And the extension part extends in an outward direction of the source electrode.        In the method of manufacturing a thin film transistor substrate, Forming a gate wiring on the insulating substrate; Forming an active layer on the gate wiring; And A method of manufacturing a thin film transistor substrate, the method comprising: forming a data line on the active layer, the data line having an intersection area with the gate line; And the active layer has an extension portion formed over at least one side of both sides of the data line in the longitudinal direction in the cross region. The method of claim 5,         And the active layer is formed in the gate wiring region. A first substrate; A second substrate disposed opposite the first substrate and including a gate wiring, a data wiring formed to have an intersection area with the gate wiring, and an active layer interposed between the gate wiring and the data wiring; A liquid crystal display panel comprising a liquid crystal injected between the first substrate and the second substrate, And the active layer includes an extension part formed over at least one side of both side surfaces of the data line in the cross region. The method of claim 7, wherein The active layer is formed in an area of the gate wiring. The method of claim 7, wherein The gate line includes a gate line and a gate electrode having a line width increasing at the intersection area of the gate line and the data line, And the active layer is on the gate electrode and the extension is on the gate line. The method of claim 7, wherein         The data line includes a data line and a source electrode branched from the data line and formed in a J or U shape.         And the extension portion extends in an outward direction of the source electrode.

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