KR20060028001A - Manufacturing method of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, in a flash memory device using a control gate of a polysilicon / metal stacked structure, a metal layer is formed after a gate reoxidation process by a damascene process, and thus a metal layer is formed in a gate reoxidation process. Deterioration of the tunnel oxide film and inter-gate oxide film due to diffusion does not occur, so that almost any metal that can be processed can be used to increase process margins, and high temperature gate reoxidation and source / drain region heat treatment processes are performed before forming metal gates. Therefore, the reaction between the metal and the polysilicon layer interface is minimized, so that the RC delay is reduced to enable high-speed operation of the device, thereby improving process yield and device operation characteristics.

Flash memory devices, metal layers, damascene, gates, reification

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

1A to 1E are manufacturing process diagrams of a semiconductor device according to the prior art.

2 is a layout diagram of the state of FIG. 1B;

3 is a current density graph according to a gate voltage according to a gate reoxidation method.

4 is an interfacial trap density graph according to a gate reoxidation method.

Figures 5a to 5g is a manufacturing process of the semiconductor device according to the present invention.

6 is a layout diagram of the state of FIG. 5A;

         <Explanation of symbols for the main parts of the drawings>

10, 40: semiconductor substrate 12, 42: device isolation film

14, 44 tunnel oxide film 16, 46 first polysilicon layer

18, 48: inter-gate insulating film 20, 50: second polysilicon layer

22: diffusion barrier 24, 70: W layer

26, 56: hard mask layer 28, 58: photosensitive film pattern

30, 60: property film 32, 62: spacer

34, 64 source / drain regions 36, 66: interlayer insulating film

52 sacrificial oxide film 54 third polysilicon layer

68: diffusion barrier

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, in a flash memory device using a control gate of a polysilicon / metal stacked structure, a metal layer is formed after a gate reoxidation process by a damascene process, and free metal can be used. The present invention relates to a method for fabricating a semiconductor device capable of minimizing the reaction between the polysilicon layer interface and reducing the RC delay to enable high-speed operation of the device, thereby improving process yield and device operation characteristics.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.

The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate, but is primarily proportional to the light source wavelength (??) and the process variable (k) of the reduction exposure apparatus used. It is inversely proportional to the lens aperture (NA, numerical aperture) of the exposure apparatus.

Here, the wavelength of the light source is reduced to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. In order to form a fine pattern of 0.5 μm or less, a deep ultra violet (DUV) or a KrF laser having a wavelength of 248 nm or 193 nm is used to form a fine pattern of 0.5 μm or less, respectively. An exposure apparatus using an ArF laser as a light source should be used.

In addition to the reduction exposure apparatus, the process method includes a method of using a phase shift mask as a photo mask, or forming a separate thin film on the wafer to improve image contrast. A contrast enhancement layer (CEL) method or a tri layer resister (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers. In addition, a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.

In addition, in order to reduce the size of the semiconductor device as the semiconductor device is highly integrated, a process such as a gate electrode, a source / drain region, and a contact thereof with a metal oxide semi-conductor field effect transistor (hereinafter referred to as a MOS FET) Although the overall design rule is reduced, there is a problem in that the width of the gate electrode and the electrical resistance are proportional to each other, so that if the width is reduced by N times, the electrical resistance is increased by N times to reduce the operation speed of the semiconductor device. Therefore, in order to reduce the resistance of the gate electrode, polyside, which is a laminated structure of the polysilicon layer and the silicide, may be used as the low resistance gate by using the property of the polysilicon layer / oxide layer interface that exhibits the most stable MOSFET characteristics.

Conventionally, the h-integrated nonvolatile flash memory device having a gate line width of 0.1 μm or less uses a W / WNx / polycrystalline silicon layer structure having relatively low resistance due to an increase in resistance when a control gate having a W-polyside stack structure is used. .

1A to 1E are manufacturing process diagrams of a semiconductor device according to the prior art, which will be described with reference to FIG. 2. FIG. 2 is a layout diagram in the state of FIG. 1B, wherein FIGS. 1A and 1B are process progress diagrams in a cross-sectional state along the line I-I in FIG. 2, and FIGS. 1C and 1D are line II- in FIG. 2. The process progression of the cross-sectional state by II.

Referring to FIG. 1A, a stripe-type device isolation layer 12 is formed on a semiconductor substrate 10 of a silicon wafer using a shallow trench process, and a tunnel oxide layer 14 is formed on the semiconductor substrate 10. The first polysilicon layer 16 serving as a floating gate is formed on the tunnel oxide layer 14.

Referring to FIG. 1B, an inter-gate insulating film 18 having an oxide film-nitride-oxide film structure is coated on the entire surface of the structure, and the second polysilicon layer 20 serving as a control gate is formed on the inter-gate insulating film 18. And the diffusion barrier 22 and the gate W layer 24 made of WN or W-Si-N are sequentially formed.

Referring to FIG. 1C, a hard mask layer 26 is coated on the W layer 24, and a photosensitive film pattern 28 for floating gate patterning is formed on the hard mask layer 26.

Referring to FIG. 1D, the photoresist layer pattern 28 is sequentially etched from the hard mask layer 26 to the first polysilicon layer 16 using a mask to form an island-shaped first polycrystalline silicon layer 16 pattern. A gate is formed, and a pattern of the second polysilicon layer 20 and the W layer 24 superimposed thereon is formed.

Thereafter, the semiconductor substrate 10 having the structure is subjected to a gate reoxidation process in an O 2 atmosphere, or a gate selective reoxidation process is performed in an H 2 O and H 2 mixed atmosphere to form the polysilicon layers 16 and 20. The reoxidation film 30 is formed on the side wall. In this case, the reoxidation process is a process for compensating for plasma damage after the gate etching, in which the gate Buzzvik oxidation occurs at the gate edge portion.

Referring to FIG. 1E, spacers 32 are formed on sidewalls from the first polysilicon layer 16 pattern to the W layer 24 pattern, and source / drain regions are formed on the semiconductor substrate 10 on both sides of the patterns. After the 34 is formed, an interlayer insulating film 36 is applied to the entire surface of the structure, and the interlayer insulating film 36 is formed by chemical-mechanical polishing (hereinafter referred to as CMP) or etch back. ) Is removed to expose the top of the W layer (24).

As described above, in the method of manufacturing a semiconductor device according to the prior art, after patterning the laminated gate of the W / WNx / polycrystalline silicon layer / inter-gate insulating film / polycrystalline silicon layer, gate re-oxidation to compensate for damage by plasma Proceed with the process.

At this time, the W layer is exposed to the outside, and in order to prevent abnormal oxidation of W, instead of the conventional dry O2 gate reoxidation process, a selective gate reoxidation process is performed in an H 2 O / H 2 mixed gas atmosphere.

However, as the gate reoxidation process is shown in FIG. 3, the selective gate reoxidation process worsens the characteristics of the stress induced leakage current of the gate oxide film than the gate reoxidation process, and as shown in FIG. 4, the interface trap density is selective. The gate reoxidation process has an increased problem than the gate reoxidation process.

In addition, Si-N and Si-O bonds are formed at the interface between the W layer and the polysilicon layer during the selective gate reoxidation process performed at a high temperature in the prior art, and the Si-N bonds do not affect properties because they act as diffusion barriers. However, the Si-O bond is formed as O2 or H2O is formed to reach the interface through the W layer during the selective reoxidation process, causing the RC delay of the high-speed operating device.

The present invention is to solve the above problems, the object of the present invention is to form a W layer by the damascene method by a simple process change to prevent the deterioration of the characteristics of the device by the gate reoxidation process process yield and It is to provide a method of manufacturing a semiconductor device that can improve the reliability.

Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,

Forming a stripe-shaped device isolation film on the semiconductor substrate;

Forming a tunnel oxide film on the semiconductor substrate;

Forming a first polysilicon layer pattern on the tunnel oxide film;

Sequentially forming an inter-gate insulating film, a second polysilicon layer, a sacrificial oxide film, and a third polysilicon layer on the entire surface of the structure;

Patterning the third polysilicon layer to the first polysilicon layer using a mask for gate patterning to form a first polycrystalline silicon layer pattern as an island-shaped floating gate, and second and third polysilicon layer patterns Process to do,

Forming a reoxidation film on the surfaces of the first to third polysilicon layer patterns by performing a gate reoxidation process on the semiconductor substrate having the structure;

Forming a spacer on sidewalls of the patterns;

Filling the gaps between the patterns with an interlayer insulating film;

Exposing the second polycrystalline silicon layer by removing the third polysilicon layer pattern and the sacrificial oxide film;

And filling the grooves from which the third polysilicon layer is removed with a metal layer.

In another aspect of the present invention, the inter-gate insulating film may be formed of an oxide film, a nitride film, or an oxide film-nitride film-oxide stacked structure, or a metal oxide, metal nitride oxide, or metal nitride including Hf, Zr, Al, Ce, or Ta. Is formed.

In still another aspect of the present invention, the gate reoxidation process is heat-treated at 700-1100 ° C. in an O 2 or H 2 O atmosphere, or plasma treated at 100-700 ° C. in an atmosphere containing O 2, and the gate at the gate reoxidation process. Buzzvik oxidation occurs.

In addition, the spacer is formed of an oxide film, a nitride film or a laminated film structure, wherein the metal layer is formed of W, Mo, Ta, Co, Ti, Cu or Pt, and comprises a step of forming a diffusion barrier film before the metal layer forming process It is characterized by.

In addition, the diffusion barrier is formed in a thickness of 10-100Å, the diffusion barrier is a metal nitride film material WNx, MoNx, TiNx, HfNx, TaNx, W-Si-N, Ti-Si-N, Ti-Al-N or It is formed of Ta-Si-N (x = 0.05-2.0), and the diffusion barrier layer is W, Mo, Ti, Hf, Ta, WSix, MoSix, TiSix, HfSix or TaSix (10-50Å thick at the bottom of the metal nitride film) x = 0.05-2.0) is further inserted to form a double diffusion barrier.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

5A to 5G are manufacturing process diagrams of a semiconductor device according to the present invention, which is an example of a nonvolatile flash device, and will be described with reference to FIG. 6. FIG. 6 is a layout diagram in a state of FIG. 5A, where FIG. 5 is a process progress diagram in a cross-sectional state along the line III-III in FIG. 6, and FIGS. 5B to 5G are in line IV-IV in FIG. 6. The process progress of the cross-sectional state along.

Referring to FIG. 5A, a shallow trench process may be performed on a semiconductor substrate 40 such as a silicon wafer to form a stripe device isolation layer 42, and a well and channel ion implantation process may be performed. A tunnel oxide film 44 of a flash device is formed on the flash device, and a polysilicon layer coating and photolithography process is performed on the first polycrystalline silicon layer 46 pattern serving as a floating gate on the tunnel oxide film 44. It is formed in a stripe shape parallel to the separator 42.

Then, a second material serving as a control gate on the inter-gate insulating film 48 is applied to the entire surface of the structure by applying a predetermined material, for example, an oxide film, a nitride film, or an oxide-nitride film-oxide film stacked structure. After coating and planarizing the polysilicon layer 50, the sacrificial oxide layer 52 and the third polysilicon layer 54 are sequentially formed on the second polysilicon layer 50. The inter-gate insulating layer 48 may be a high-k dielectric film such as metal oxide, metal nitride oxide, or metal nitride including Hf, Zr, Al, Ce, or Ta.

Referring to FIG. 5B, a hard mask layer 56 is coated on the third polysilicon layer 54, and a photosensitive film pattern 58 for floating gate patterning is formed on the hard mask layer 56.

Referring to FIG. 5C, the first polysilicon layer 46 pattern, which is an island-shaped floating gate, is sequentially etched from the hard mask layer 56 to the first polysilicon layer 56 using the photoresist pattern 58 as a mask. And the second and third polysilicon layers 50 and 54 patterns are formed, and the remaining photoresist pattern 58 and the hard mask layer 56 are removed.

Referring to FIG. 5D, the semiconductor substrate 40 having the structure is heat-treated at 700-1100 ° C. in an O 2 or H 2 O atmosphere, or plasma-treated at 100-700 ° C. in an oxygen-containing atmosphere. Thereby forming a reoxidation film 60 on the exposed surfaces of the patterns. In this case, the reoxidation process is a process for compensating for plasma damage after the gate etching, in which the gate Buzzvik oxidation occurs at the gate edge portion.

Referring to FIG. 5E, a gate spacer material, for example, an oxide film, a nitride film, or a laminated film structure, is deposited on the entire surface of the structure, and the upper surface of the third polysilicon layer 54 pattern is exposed. The spacer 62 is formed on the outer side of the sidewall reoxidation layer 60 of the patterns.

Then, source / drain regions 64 are formed by ion implantation of impurities into the semiconductor substrate 40 on both sides of the third polysilicon layer 56, and an interlayer insulating film 66 is formed on the entire surface of the structure. The upper part of the third polysilicon layer 54 is exposed by planarizing the upper part by a method such as etch back or CMP.

Referring to FIG. 5F, the second polycrystalline silicon layer 50 is exposed by removing the exposed third polysilicon layer 54 pattern and the sacrificial oxide layer 52 to proceed with the damascene process. On the entire surface, a diffusion barrier film 68 made of a metal nitride film and a W layer 70 serving as a control gate are sequentially formed. Wherein the diffusion barrier 68 may use WNx, MoNx, TiNx, HfNx, TaNx, W-Si-N, Ti-Si-N, Ti-Al-N or Ta-Si-N, x is 0.05- Form a thickness of about 10-100 mm with a value of 2.00. In addition, in order to prevent the formation of an insulating film such as Si-N at the interface between the second polysilicon layer 50 and the diffusion barrier 68, a thickness of 10-50 Å W is provided under the diffusion barrier 68 of the metal nitride layer. , Mo, Ti, Hf, Ta or WSix, MoSix, TiSix, HfSix, TaSix (x = 0.05-2.0) film may be further formed to form a double diffusion barrier. In addition, when the thermal process temperature is 600 ° C. or lower in a subsequent process performed after the formation of the W layer 70, diffusion between the W and the polysilicon layer hardly occurs, and thus the diffusion barrier layer 68 may not be formed.

Referring to FIG. 5G, a portion of the third polysilicon layer 54 removed by sequentially removing the W layer 70 and the diffusion barrier 68 on the interlayer insulating layer 66 by CMP or etch back. Only the W layer 70 pattern remains. In the flash memory device according to the present invention, since the tunnel oxide film and the gate oxide film do not deteriorate in the gate reoxidation process, the W layer 70 may be processed such as W, Mo, Ta, Co, Ti, Cu, or Pt. Almost all metals can be used.

As described above, in the method of manufacturing a semiconductor device according to the present invention, since a metal layer is formed after a gate reoxidation process by a damascene process in a flash memory device using a control gate of a polysilicon / metal stacked structure, Since the tunnel oxide film and the gate oxide film do not deteriorate due to diffusion through the metal layer, almost any metal that can be processed can be used to increase the process margin, and the high temperature gate reoxidation and the source / drain region heat treatment process form the metal gate. Since it is performed before, the reaction between the metal and the polysilicon layer interface is minimized, so that the RC delay is reduced, so that the device can be operated at high speed, thereby improving process yield and device operation characteristics.

Claims (12)

Forming a stripe-shaped device isolation film on the semiconductor substrate; Forming a tunnel oxide film on the semiconductor substrate; Forming a first polysilicon layer pattern on the tunnel oxide film; Sequentially forming an inter-gate insulating film, a second polysilicon layer, a sacrificial oxide film, and a third polysilicon layer on the entire surface of the structure; Patterning the third polysilicon layer to the first polysilicon layer using a mask for gate patterning to form first polycrystalline silicon layer patterns as island-shaped floating gates, and second and third polysilicon layer patterns Fair, Forming a reoxidation film on the surfaces of the first to third polysilicon layer patterns by performing a gate reoxidation process on the semiconductor substrate having the structure; Forming a spacer on sidewalls of the patterns; Filling the gaps between the patterns with an interlayer insulating film; Exposing the second polycrystalline silicon layer by removing the third polysilicon layer pattern and the sacrificial oxide film; And filling the groove from which the third polysilicon layer is removed with a metal layer. 2. The method of claim 1, wherein the inter-gate insulating film is formed of any one of an oxide film, a nitride film, and an oxide film-nitride film-oxide film stacked structure. The semiconductor device of claim 1, wherein the inter-gate insulating film is formed of any one selected from the group consisting of metal oxides, metal nitride oxides, and metal nitrides including Hf, Zr, Al, Ce, and Ta. Manufacturing method. The method of claim 1, wherein the gate reoxidation process is performed at 700-1100 ° C. in an O 2 or H 2 O atmosphere. The method of claim 1, wherein the gate reoxidation process is performed by plasma treatment at 100-700 ° C. in an atmosphere containing O 2. The method of claim 1, wherein a gate buzz big oxidation occurs during the gate reoxidation process. The method of claim 1, wherein the spacer has an oxide film, a nitride film, or a laminated film structure. The method of claim 1, wherein the metal layer is formed of any one selected from the group consisting of W, Mo, Ta, Co, Ti, Cu, and Pt. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a diffusion barrier film before the metal layer forming step. 10. The method of claim 9, wherein the diffusion barrier layer is formed to a thickness of 10-100 kHz. 10. The method of claim 9, wherein the diffusion barrier is made of metal nitride film WNx, MoNx, TiNx, HfNx, TaNx, W-Si-N, Ti-Si-N, Ti-Al-N and Ta-Si-N (x = 0.05-2.0) A method for manufacturing a semiconductor device, characterized in that consisting of any one selected from the group consisting of. 10. The method of claim 9, wherein a W, Mo, Ti, Hf, Ta or WSix, MoSix, TiSix, HfSix, TaSix (x = 0.05-2.0) film having a thickness of 10-50 mm is further inserted into the diffusion barrier layer. To form a double diffusion barrier.

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