KR20060027749A - Nonvolatile semiconductor memory devices and methods of fabricating the same - Google Patents

Abstract

Provided are nonvolatile semiconductor memory devices having a plurality of three-dimensional unit cells. The unit cell includes a semiconductor substrate and a source region and a drain region formed on the semiconductor substrate and spaced apart from each other. An upper control gate line is disposed across the horizontal channel region between the source / drain regions. A horizontal charge storage layer pattern is positioned between the upper control gate line and the horizontal channel region. A plurality of side control gate lines are provided that traverse the outer portions of the plurality of vertical channel regions, respectively, between the source / drain regions, and are arranged side by side on each side of the upper control gate line. And a plurality of vertical charge storage layer patterns vertically disposed between the plurality of side control gate lines and the vertical channel regions. Methods of forming the nonvolatile semiconductor memories are also provided.

Nonvolatile Semiconductor Memory, Tunneling Insulation, Control Gate Line

Description

Nonvolatile semiconductor memory devices and methods of fabricating the same

1 is a cross-sectional view showing a conventional nonvolatile semiconductor memory device.

2 to 4 are cross-sectional views taken along the line I-I of FIG. 11, which are cross-sectional views illustrating horizontal cell transistors and a method of manufacturing the same.

5 through 10 are cross-sectional views taken along the line II-II of FIG. 11, and are cross-sectional views illustrating vertical cell transistors and a method of manufacturing the present invention.

11 is a schematic perspective view of a semiconductor memory device according to an embodiment of the present invention.

12A is a schematic layout diagram of semiconductor memory devices according to an application example of the present invention.

12B is an equivalent circuit diagram of the semiconductor memory devices shown in FIG. 12A.

13 is a schematic layout diagram of semiconductor memory devices according to another application example of the present invention.

14 is a schematic layout diagram of semiconductor memory devices according to still another application example of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices and methods of manufacturing the same, and more particularly, to three-dimensional non-volatile semiconductor memory devices having a cell transistor forming a horizontal channel between a plurality of cell transistors forming a vertical channel. It relates to manufacturing methods.

  Flash memory devices are widely used to store charge as non-volatile memory devices. Such a flash memory device requires a new method or device structure because the scaling down characteristic is not easy unlike a DRAM memory device.

1 is a cross-sectional view showing a conventional nonvolatile memory storage device.

Referring to FIG. 1, source / drain regions 12 may be formed to be spaced apart from each other in a predetermined region of the semiconductor substrate 10. A channel region is formed between the source / drain regions 12 spaced apart from each other. A tunneling oxide film 14 is formed on the channel region, and the floating electrode 16, the gate oxide film 18, and the control electrode 20 are sequentially stacked on the tunneling oxide film 14.

In the nonvolatile semiconductor memory device configured as described above, a tunneling oxide film 14 is disposed below the floating electrode 16. As the nonvolatile semiconductor memory device, especially the flash memory device, is scaled down, the channel length, the gate height, or the depth of the junction are reduced, and accordingly, the thickness of the tunneling oxide film 14 must also be reduced. However, there is a limit to thinning the thickness of the tunneling oxide film 14. The reason is that the charge in the channel cannot reduce the thickness of the tunneling oxide film 14 tunneling to move to the floating electrode 16 to 7 nm or 8 nm or less. If the thickness of the tunneling oxide film 14 is made thin, the charge stored in the floating electrode 16 escapes back to the channel, thereby deteriorating memory retention characteristics.

In addition, such flash memory devices are disposed on the same plane. In order to increase the degree of integration, the flash memory devices utilize a scaling down characteristic as described above or a method of reducing the number of devices. However, reducing the number of devices disposed on the same plane to increase the degree of integration results in a decrease in memory storage capacity by that amount.

In order to improve the scale-down characteristics of the flash memory device, a device having a fin channel has been studied. A flash memory device forming the fin channel region is introduced in US Pat. No. 6,768,158. However, since the device having such a fin-like channel is also disposed on the same plane, there is a limit to increase the degree of integration by reducing the arrangement space of the device.

An object of the present invention is to provide a three-dimensional nonvolatile semiconductor memory device having a multi-bit storage capacity per unit memory cell.                         

In addition, another technical problem to be achieved by the present invention is to provide methods for manufacturing a three-dimensional nonvolatile semiconductor memory device suitable for realizing high integration.

According to one aspect of the present invention, there are provided three-dimensional highly integrated nonvolatile semiconductor memories suitable for storing at least six bits of data in one unit cell. The unit cell includes a semiconductor substrate and a source region and a drain region formed on the semiconductor substrate and spaced apart from each other. An upper control gate line is disposed across the horizontal channel region between the source / drain regions. A horizontal charge storage layer pattern is positioned between the upper control gate line and the horizontal channel region. A plurality of side control gate lines are provided that traverse the outer portions of the plurality of vertical channel regions, respectively, between the source / drain regions, and are arranged side by side on each side of the upper control gate line. And a plurality of vertical charge storage layer patterns vertically disposed between the plurality of side control gate lines and the vertical channel regions.

In some embodiments of the present invention, the unit cell of the present invention further includes interlayer insulating layer patterns interposed between the upper control gate line and the side control gate lines.

In other embodiments, flash memory devices including a cell transistor forming a horizontal channel between a plurality of cell transistors forming a vertical channel are included. The unit cell of the flash memory devices may include the plurality of vertical channel type cell transistors and the horizontal channel type cell transistors. Three-dimensional first and second impurity regions are shared by the vertical channel type cell transistors and the horizontal channel type cell transistors.

In still other embodiments, the horizontal channel cell transistor is disposed on the horizontal channel region formed between the three-dimensional first and second impurity regions spaced apart from each other, and the first and second impurities are disposed. The vertical channel transistors may be disposed at sides of a plurality of vertical channel regions formed between regions.

In still other embodiments of the present invention, the semiconductor substrate and the three-dimensional first and second impurity regions formed to be spaced apart from each other with a channel region interposed therebetween may be provided. A horizontal channel type cell transistor may be disposed on the channel region forming the horizontal channel. A plurality of vertical channel type cell transistors may be disposed on sides of the plurality of channel regions forming the vertical channel, respectively. The first and second impurity regions are shared by the horizontal channel type cell transistor and the vertical channel type cell transistors.

In another embodiment of the present invention, the horizontal channel type cell transistor is disposed on a channel region formed between the first and second impurity regions, and the plurality of horizontal channel type cell transistors are disposed on both sides of the horizontal channel type cell transistor. Vertical channel type cell transistors may be disposed.

In other embodiments of the present invention, the horizontal channel type cell transistors may be formed side by side on the horizontal channel region between the first and second impurity regions spaced apart from each other. A horizontal tunneling insulating layer pattern may be formed on the horizontal channel region to be parallel to the horizontal channel length direction. A horizontal charge storing layer pattern, a horizontal gate insulating layer pattern, and a horizontal conductive layer pattern may be sequentially stacked on the horizontal tunneling insulating layer pattern. A horizontal interlayer insulating layer pattern may be formed on the horizontal conductive layer pattern. A plurality of first interlayer insulating layer patterns may be formed to respectively cover the sidewalls of the horizontal tunneling insulating layer pattern, the horizontal charge storage layer pattern, the horizontal gate insulating layer pattern, and both sidewalls of the horizontal conductive layer pattern. have. The horizontal conductive layer pattern may serve as an upper control gate line of the horizontal channel type cell transistor.

In example embodiments, the horizontal conductive layer pattern may be formed to cover sidewalls and an upper portion of the plurality of first interlayer insulating layer patterns.

In still other embodiments of the present invention, the plurality of vertical channel type cell transistors may be disposed in parallel with sides of the vertical channel regions between the first and second impurity regions spaced apart from each other. Vertical tunneling insulating layer patterns may be formed on sides of the vertical channel regions, respectively. Vertical charge storage layer patterns may be formed in parallel with sidewalls of the vertical tunneling insulating layer patterns. Vertical gate insulating layer patterns may be formed in parallel to sides of the vertical charge storage layer patterns. Vertical conductive layer patterns may be formed in parallel on sides of the vertical gate insulating layer patterns. The vertical conductive layer patterns may serve as side control gate lines of the vertical channel transistors.

In another embodiment of the present invention, the horizontal or vertical charge storage layer patterns may be a silicon oxide-silicon nitride-silicon oxide (ONO) laminated film, silicon nanocrystals, or a combination thereof. Or a floating gate composed of a conductive film.

According to another aspect of the present invention, there is provided a method of manufacturing three-dimensional non-volatile semiconductor memory device having a cell transistor to form a horizontal channel between a plurality of cell transistors, each forming a plurality of vertical channels. These methods include forming a horizontal channel type cell transistor and then forming a plurality of vertical channel type cell transistors on both sidewalls of the horizontal channel type cell transistor, respectively.

In some embodiments of the present invention according to the above aspect, the manufacturing method of the present invention includes providing a semiconductor substrate containing a predetermined concentration of impurities. A horizontal tunneling insulating film is formed on the semiconductor substrate. A horizontal charge storage layer, a horizontal gate insulating film, and a lower horizontal conductive film are sequentially formed on the horizontal tunneling insulating film. The semiconductor film is exposed through both sides of the laminated film pattern by successively patterning a stacked film including the lower horizontal conductive film, the horizontal gate insulating film, the horizontal charge storage layer, and the horizontal tunneling insulating film. Impurity ions are implanted into the substrate to form first and second impurity regions. First interlayer insulating layers may be formed on the substrate to cover both sidewalls of the stacked layer pattern. A conductive film is further stacked on the entire surface of the substrate to form an upper horizontal conductive film covering the lower horizontal conductive film and the first interlayer insulating films. A horizontal interlayer insulating film is formed on the upper horizontal conductive film. The horizontal interlayer insulating film, the horizontal conductive film, and the first interlayer insulating film are successively patterned. Vertical channel type cell transistors are disposed on sides of the vertical channel areas formed between the first and second impurity regions.

In another embodiment, disposing the vertical channel type cell transistors on each side of the vertical channel areas may include the horizontal tunneling insulating film pattern, the horizontal charge storage layer pattern, the horizontal gate insulating film pattern, And sequentially etching the lower and upper horizontal conductive film patterns and the horizontal stacked film pattern in which the horizontal interlayer insulating film pattern is sequentially formed to expose the substrates on both sides of the horizontal stacked film pattern. Second interlayer insulating layers respectively covering sidewalls of the horizontal stacked layer pattern may be formed on the substrate. The substrate formed on both sides of the second interlayer insulating layers is etched back to a predetermined depth. Vertical tunneling insulating layers covering one side of the vertical channel regions may be formed on the substrate, respectively. Vertical charge storage layers covering one side portions of the vertical tunneling insulating layers may be formed on the substrate, respectively. Vertical gate insulating layers covering sides of the vertical charge storage layers may be formed on the substrate, respectively. Vertical conductive layers covering one side of the vertical gate insulating layer may be formed on the substrate. The second interlayer insulating layers, the vertical tunneling insulating layers, the vertical charge storage layers, the vertical gate insulating layers, and the vertical conductive layers are successively patterned to form a vertical stacked layer pattern. The vertical conductive layer patterns may serve as side control gate lines.

In another embodiment of the present invention, the horizontal stacked film pattern is continuously etched to expose the substrates on both sides of the horizontal stacked film pattern, wherein the width of the horizontal stacked film pattern is equal to the first or second width. The substrate may be exposed by etching the horizontal stacked layer pattern to be equal to or smaller than a width of two impurity regions.

In another embodiment of the present invention, etching back the substrate formed on both sides of the second interlayer insulating layer patterns to a predetermined depth may include a depth at which vertical channel regions are formed between the first and second impurity regions. Until the semiconductor substrate can be etched back.

In another embodiment of the present invention, after patterning the vertical gate insulating layers to expose the semiconductor substrate on which the first and second impurity regions are formed, impurities may be further injected into the first and second impurity regions. have.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments introduced below are provided to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the present invention may be embodied in other forms without being limited to the embodiments described below. In the drawings, lengths, thicknesses, and the like of layers and regions may be exaggerated for convenience of description. In addition, where a line or layer is said to be on another line, or on another layer, it may be formed directly on the other line or another layer, or a third layer may be interposed therebetween.

2 to 4 are cross-sectional views taken along the line I-I of FIG. 11, which are cross-sectional views illustrating horizontal cell transistors and a method of manufacturing the same.

5 through 10 are cross-sectional views taken along the line II-II of FIG. 11, and are cross-sectional views illustrating vertical cell transistors and a method of manufacturing the present invention.

11 is a schematic perspective view of a semiconductor memory device according to an embodiment of the present invention. 12A is a schematic layout diagram of a semiconductor memory device according to an application example of the present invention. FIG. 12B is an equivalent circuit diagram of the semiconductor memory device shown in FIG. 12A. 13 is a schematic layout diagram of a semiconductor memory device according to another application example of the present invention. 14 is a schematic layout diagram of a semiconductor memory device according to still another application example of the present invention.

2 and 11, a horizontal tunneling insulating layer 110 is formed on the semiconductor substrate 100 into which impurities of a predetermined concentration are implanted. The horizontal tunneling insulating layer 110 may be formed of a silicon oxide film, a high dielectric film, or a combination thereof. A horizontal charge storage layer 120 is formed on the substrate 100 on which the horizontal tunneling insulating layer 110 is formed. The horizontal charge storage layer may be a silicon oxide-silicon nitride-silicon oxide (ONO) stacked film, silicon nanocrystals, or a combination thereof, or may be formed of a floating gate formed of a conductive film. A horizontal gate insulating layer 130 is formed on the substrate 100 on which the horizontal charge storage layer 120 is formed. The horizontal gate insulating layer 130 may be formed of a silicon oxide layer, a high dielectric layer, or a combination thereof. A lower horizontal conductive layer 140 is formed on the substrate 100 on which the horizontal gate insulating layer 130 is formed.

3 and 11, the lower horizontal conductive layer 140, the horizontal gate insulating layer 130, the horizontal charge storage layer 120, and the horizontal tunneling insulating layer 110 may be formed. The flat stacked layer 160 is continuously patterned to expose the semiconductor substrate through both sides of the horizontal stacked layer pattern. As a result, first and second impurity regions 150s and 150d are defined in the substrate 100. Source / drain regions 150s and 150d are formed by implanting impurities into the substrate 100 in which the first and second impurity regions 150s and 150d are defined. The source / drain regions 150s and 150d may be three-dimensionally formed in the substrate 100. Accordingly, the lower horizontal conductive layer pattern 140a, the horizontal gate insulating layer pattern 130a, and the number are disposed on the horizontal channel region 155 formed between the source / drain regions 150s and 150d. A horizontal stacked layer pattern 160a including the balanced charge storage layer pattern 120a and the horizontal tunneling insulating layer pattern 110a is disposed. Before the impurity implantation process is performed, a capping layer pattern formed of an insulating layer may be disposed on the lower horizontal conductive layer 140. In this case, during the impurity implantation process, the capping layer pattern may be used as an ion implantation mask, and then the capping layer pattern may be removed.

4 and 11, the lower horizontal conductive film pattern 140a, the horizontal gate insulating film pattern 130a, the horizontal charge storage layer pattern 120a, and the horizontal tunneling insulating film pattern. A first interlayer insulating layer 170 covering both sidewalls of the stacked layer pattern 160a formed of 110a is formed on the substrate. An upper horizontal conductive film and a horizontal interlayer insulating film are sequentially formed on the substrate on which the stacked film pattern 160a and the first interlayer insulating film 170 are formed. The horizontal interlayer insulating film and the upper horizontal conductive film are successively patterned. As a result, the upper horizontal conductive layer pattern 141a covers the upper portion of the lower horizontal conductive layer pattern 140a and the upper portion of the first interlayer insulating layer 170. The upper horizontal conductive layer pattern 141a may be formed of the same material layer as the lower horizontal conductive layer pattern 140a. The lower and upper horizontal conductive layer patterns 140a and 141a may be formed of a polysilicon layer or a metal layer. As a result of the process, source / drain regions 150s and 150d and the upper horizontal conductive film pattern 140a or the lower horizontal conductive film pattern 141a are isolated from each other by the first interlayer insulating film 170. . A horizontal interlayer insulating layer pattern 180a is formed on the upper horizontal conductive layer pattern 141a.

In the above embodiments, the stacked layer 160 including the lower horizontal conductive layer 140, the horizontal gate insulating layer 130, the horizontal charge storage layer 120, and the horizontal tunneling insulating layer 110 is formed. After the formation, the upper horizontal conductive film 141 is formed. However, the formation of the lower horizontal conductive film 140 is omitted, and after forming the first interlayer insulating film 170, a horizontal conductive film including the lower and upper horizontal conductive films 140 and 141 is formed. You could do it.

The preliminary horizontal cell transistor is arranged on the horizontal channel region by the above process.

Subsequently, the vertical cell transistors of the present invention and methods of manufacturing the same will be described.

As shown in FIG. 5, after the preliminary horizontal cell transistor is disposed on the substrate 100, the vertical cell transistors may be disposed on both sides of the preliminary horizontal cell transistor.

5, 6, and 11, the horizontal interlayer insulating layer pattern 180a, the upper horizontal conductive layer pattern 141a, and the lower horizontal conductive layer pattern 140a formed on the substrate 100. ), Both sides of the horizontal stacked film pattern 161a including the horizontal gate insulating film pattern 130a, the horizontal charge storage layer pattern 120a, and the horizontal tunneling insulating film pattern 110a are continuously etched. . As a result, the width of the horizontal stacked layer pattern 161a is reduced by the etched width to form the horizontal stacked layer pattern 161b shown in FIG. 6. That is, the horizontal stacked layer pattern 161b includes a horizontal tunneling insulating layer pattern 110b, a horizontal charge storage layer pattern 120b, a horizontal gate insulating layer pattern 130b, and a lower horizontal conductive layer pattern ( 140b), an upper horizontal conductive film pattern 141b, and a horizontal interlayer insulating film pattern 180b. This completes the manufacturing process of the horizontal cell transistor. Substrates 100 on both sides of the horizontal stacked layer pattern 161b are exposed by the etching process. In this case, it may be preferable to etch both sides of the horizontal stacked film pattern 161a such that the width of the horizontal stacked film pattern 161b is equal to or smaller than the width of the first and second impurity regions. Lower and upper horizontal conductive layer patterns 140b and 141b among the components of the horizontal stacked layer pattern 161b serve as the upper control gate line 142.

7 and 11, second interlayer insulating layers 190 and 190 ′ covering both sidewalls of the horizontal stacked layer pattern 161b are formed on the substrate 100, respectively.

8 and 11, both sides of the substrate 100 are formed to a predetermined depth by using the horizontal interlayer insulating layer pattern 180b and the second interlayer insulating layers 190 and 190 ′ as etch masks, respectively. Etch back. At this time, the substrate 100 is etched back to a depth where vertical channel regions are formed between the first and second impurity regions.

10 and 11, vertical tunneling insulating layers 200 and 200 ′ covering both sidewalls of the substrate 100 and outer walls of the second interlayer insulating layers 190 and 190 ′ may be formed. 100 and vertically formed on each. The substrate 100 is exposed by etching back the vertical tunneling insulating layers 200 and 200 ′. As a result, the vertical tunneling insulating layers 200 and 200 ′ are formed at sides of the vertical channel regions 157 and 157 ′ formed between the first and second impurity regions, respectively. The vertical tunneling insulating layers 200 and 200 ′ may be formed of the same material layer as the horizontal tunneling insulating layer pattern 110a. Vertical charge storage layers 210 and 210 ′ covering the outer walls of the vertical tunneling insulating layers 200 and 200 ′ are vertically formed on the substrate 100, respectively. The substrate 100 is exposed by etching back the vertical charge storage layers 210 and 210 ′, respectively. The vertical charge storage layers 210 and 210 ′ may be formed of the same material layer as the horizontal charge storage layer pattern 120a. Vertical gate insulating layers 220 and 220 ′ covering the outer sidewalls of the vertical charge storage layers 210 and 210 ′ are vertically formed on the substrate 100. The substrate 100 is exposed by etching back the vertical gate insulating layers 220 and 220 ′, respectively. The vertical gate insulating layers 220 and 220 ′ may be formed of the same material layer as the horizontal gate insulating layer pattern 130a. Next, impurity ions may be further implanted into the substrate exposed on both sides of the vertical gate insulating layers 220 and 220 ′.

10 and 11, each of the outer sidewalls of the vertical gate insulating layers 220 and 220 ′ and the vertical conductive layers 230 and 230 ′ covering the substrate 100 may be formed on the substrate. It is formed vertically on the 100 respectively. The vertical conductive layers 230 and 230 ′ may be formed of the same material layer as the lower and upper horizontal conductive layers 140 and 141.

Accordingly, the vertical tunneling insulating layers 200 and 200 ′, the vertical charge storage layers 210 and 210 ′, the vertical gate insulating layers 220 and 220 ′, and the vertical conductive layers 230 are formed. , And a plurality of vertical stacked films in which 230 'are vertically stacked in order are disposed on both sides of the horizontal stacked film pattern 161b. The plurality of vertical stacked films are patterned to form a plurality of first and second vertical stacked film patterns 240a and 240a 'on both sides of the horizontal stacked film pattern 161b. The first and second vertical stacked layer patterns 240a and 240a 'may include first and second vertical tunneling insulating layer patterns 200a and 200a', and first and second vertical charge storage layer patterns, respectively. (210a, 210a '), first and second vertical gate insulating layer patterns 220a and 220a', and first and second vertical conductive layer patterns 230a and 230a '. As a result, the first and second vertical stacked layer patterns 240a and 240a 'are disposed on sidewalls of the vertical channel regions 157 and 157', respectively. The first and second vertical conductive layer patterns 230a and 230a 'serve as first and second side control gate lines, respectively. This is the end of the manufacturing process for the unit cell of the flash memory devices of the present invention.

Now, nonvolatile semiconductor memory devices according to embodiments of the present invention will be described with reference to FIGS. 11, 12A, and 12B. In FIGS. 12A and 12B, portions denoted by reference numeral “C” denote unit cell regions, and FIG. 11 corresponds to a schematic perspective view of the unit cell region C. In FIG.

11, 12A and 12B, a plurality of impurity regions parallel to each other are provided in the semiconductor substrate 100. The impurity regions include source regions 150s and drain regions 150d that are arranged parallel to the y-axis and alternately arranged alternately with each other. The source / drain regions 150s and 1150d serve as reference voltage lines such as bit lines or ground lines. A plurality of parallel first and second side control gate lines 230a and 230a 'are vertical along a vertical channel length direction of the vertical channel region between the source region 150s and the drain region 150d adjacent to each other. To be placed. That is, the first and second side control gate lines 230a and 230a 'are disposed parallel to the x-axis. An upper control gate line 142 parallel to the side control gate lines 230a and 230a 'is provided between the first and second side control gate lines 230a and 230a' adjacent to each other. A horizontal charge storage layer pattern 120b is horizontally disposed between the source / drain regions 150s and 150d. An upper control gate line 142 is disposed on the horizontal charge storage layer pattern 120b. The horizontal charge storage layer pattern 120b is positioned between the first and second side control gate lines 230a and 230a 'adjacent to each other. First and second vertical charge storage layer patterns 210a and 210a 'are respectively disposed between the horizontal charge storage layer pattern 120b and the first and second side control gate lines 230a and 230a'. It is arranged vertically. Second interlayer insulating layer patterns 190a and 190a 'are disposed between the horizontal charge storage layer pattern 120b and the first and second vertical charge storage layer patterns 210a and 210a', respectively. As a result, the horizontal charge storage layer pattern 120b and the first and second vertical charge storage layer patterns 210a and 210a 'are mutually formed by the second interlayer insulating layer patterns 190a and 190a'. Electrically isolated. In addition, the second interlayer insulating layers 230a and 230a 'extend between the upper control gate line 142 and the first and second side control gate lines 230a and 230a', respectively. As a result, the upper control gate line 142 and the first and second side control gate lines 230a and 230a 'are electrically isolated from each other by the second interlayer insulating layer patterns 190a and 190a'. .

As described above, the unit cell of the nonvolatile semiconductor memory device of the present invention includes a horizontal charge storage layer pattern 120b formed between the source / drain regions 150s and 150d and the horizontal charge storage layer pattern 120b. A horizontal cell transistor TR1 including an upper control gate line 142 disposed on an upper portion of the horizontal cell transistor TR1; The first vertical charge storage layer pattern 210a and the vertical charge storage layer pattern positioned between the source / drain regions 150s and 150d and positioned on one side of the horizontal charge storage layer pattern 120b ( A first vertical cell transistor TR2 including a first vertical control gate line 230a disposed at one side of 210a; And a second vertical charge storage layer pattern 210a ′ between the source / drain regions 150s and 150d and located at the other side of the horizontal charge storage layer pattern 120b and the vertical charge storage layer. The second vertical cell transistor TR3 includes a second vertical control gate line 230a 'disposed at one side of the pattern 210a'.

The unit cell of the semiconductor device of the present invention configured as described above may be applied as the cell array shown in FIGS. 12A and 12B.

In addition, the unit cell of the semiconductor device of the present invention may be applied as the cell array shown in FIGS. 13 and 14. The present invention can also be applied to a cell array that shares a vertical side control gate and drain region as shown in FIG.

In addition to the above application examples, the unit cells of the semiconductor memory device of the present invention may be arrayed by various methods.

Hereinafter, methods for driving the cells of the semiconductor memory device described above will be described.

It is assumed that the horizontal or vertical charge storage layer is formed of a silicon oxide film-silicon nitride film-silicon oxide film ONO.

The horizontal cell transistor of the semiconductor memory device, that is, the first cell transistor TR1 is selected. There are two methods of storing data in the memory cell, namely, FN tunneling and hot carrier injection, but for convenience of description, hot carrier injection is used.

The program method of the first cell transistor TR1 applies a program voltage to the upper control gate line 142. A reference voltage (eg, a ground voltage) is applied to the source region 150s, and a drain voltage is applied to the drain region 150d. When the voltages are applied, hot carriers are generated in the channel region adjacent to the drain region 150d so that electrons are trapped and stored in the horizontal charge storage layer close to the drain region 150d. On the contrary, a program voltage is applied to the upper control gate line 142. A reference voltage (for example, a ground voltage) is applied to the drain region 150d, and a source voltage is applied to the source region 150s. When the voltages are applied, hot carriers are generated in the channel region adjacent to the source region 150s, and electrons are trapped and stored in the horizontal charge storage layer close to the source region 150s.

In the memory cell erasing method of the horizontal cell transistor, a reference voltage (for example, a ground voltage) is applied to the source region 150s. An erase voltage is applied to the upper control gate line 142 and a drain voltage is applied to the drain region 150d. Electrons trapped in the horizontal charge storage layer by the erase voltage and the drain voltage are tunneled to be discharged into the drain region 150d, or holes are tunneled from the drain region to combine with the trapped electrons. As a result, the memory cell is erased. On the contrary, a reference voltage (for example, a ground voltage) is applied to the drain region 150d. An erase voltage is applied to the upper control gate line 142, and a source voltage is applied to the source region 150s. Electrons trapped in the horizontal charge storage layer by the erase voltage and the source voltage are tunneled to be emitted to the source region 150s, or holes are tunneled from the source region 150s to combine with the trapped electrons. .

During the read operation of the memory cell of the horizontal cell transistor, a read voltage is applied to the upper control gate line 142. Accordingly, when electrons are trapped in the horizontal charge storage layer, no current flows between the source / drain regions 150s and 150d. On the contrary, when electrons are not trapped or holes are trapped in the horizontal charge storage layer, current flows between the source / drain regions 150s and 150d. As a result, it is possible to check whether data of the memory cell of the horizontal cell transistor is stored.

As described above, the horizontal cell transistor of the present invention has two bits of memory cells.

The first and second vertical cell transistors are also operated in the same manner as the operation method. Therefore, the first and second vertical cell transistors of the present invention also have memory cells of two bits. As a result, the unit cells of the semiconductor memory devices of the present invention can be operated with a total of 6 bit memory cells.

According to the present invention constructed and manufactured as described above, a single transistor is horizontally disposed in a unit cell region of a nonvolatile semiconductor memory device, and a plurality of transistors are disposed on both sides of the horizontal transistor, respectively, to achieve high integration of the memory cell. In addition, the scaling down characteristic can be significantly improved. In addition, the present invention can improve memory performance because it can have a memory storage capacity of at least 6 bits per unit cell.

Claims (5)

In a non-volatile semiconductor memory having a plurality of unit cells, the unit cell is Semiconductor substrates; Source and drain regions formed on the semiconductor substrate and spaced apart from each other; An upper control gate line across the horizontal channel region between the source / drain regions; A horizontal charge storage layer pattern between the upper control gate line and the horizontal channel region; A plurality of side control gate lines that traverse outer portions of the plurality of vertical channel regions between the source / drain regions, respectively, and are disposed side by side on both sides of the upper control gate line; And And a plurality of vertical charge storage layer patterns disposed vertically between the plurality of side control gate lines and the vertical channel regions, respectively. The nonvolatile semiconductor memory device of claim 1, further comprising interlayer insulating layer patterns interposed between the upper control gate line and the side control gate lines. Providing a semiconductor substrate, Forming a horizontal tunneling insulating film on the semiconductor substrate, A horizontal charge storage layer, a horizontal gate insulating film, and a lower horizontal conductive film are sequentially formed on the horizontal tunneling insulating film, Successively patterning a laminated film including the lower horizontal conductive film, the horizontal gate insulating film, the horizontal charge storage layer, and the horizontal tunneling insulating film to expose the semiconductor substrate through both sides of the laminated film pattern, Implanting impurity ions into the substrate to form first and second impurity regions, Forming first interlayer insulating layers covering both sidewalls of the laminate pattern on the substrate, Further stacking a conductive film on the entire surface of the substrate to form an upper horizontal conductive film covering the lower horizontal conductive film and the first interlayer insulating films; Forming a horizontal interlayer insulating film on the upper horizontal conductive film, Continuously patterning the horizontal interlayer insulating film, the horizontal conductive film, and the first interlayer insulating film, and And arranging vertical channel cell transistors on each of side portions of the vertical channel regions formed between the first and second impurity regions. 4. The method of claim 3, wherein disposing the vertical channel type cell transistors on each of the vertical channel regions sides. The horizontal stacked film pattern in which the horizontal tunneling insulating film pattern, the horizontal charge storage layer pattern, the horizontal gate insulating film pattern, the lower and upper horizontal conductive film patterns, and the horizontal interlayer insulating film pattern are sequentially formed Etching to expose the substrates on both sides of the horizontal stacked film pattern; Second interlayer insulating layers covering sidewalls of the horizontal stacked layer pattern are formed on the substrate, Etching back the substrate formed on both sides of the second interlayer insulating films, Vertical tunneling insulating layers respectively covering one side of the vertical channel regions are formed on the substrate, Forming vertical charge storage layers on the substrate to cover one side of the vertical tunneling insulating layers, Vertical gate insulating layers covering sides of the vertical charge storage layers are respectively formed on the substrate, Forming vertical conductive films on the substrate covering one side of the vertical gate insulating film, and The second interlayer insulating layers, the vertical tunneling insulating layers, the vertical charge storage layers, the vertical gate insulating layers, and the vertical conductive layers may be successively patterned to form a vertical stacked layer pattern. A method of manufacturing a nonvolatile semiconductor memory device.  The semiconductor device of claim 3, wherein the horizontal charge storage layer or the vertical charge storage layers are formed of a silicon oxide-silicon nitride-silicon oxide film, a silicon nanocrystals, Or a combination thereof or a conductive film.

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