KR20060011591A - LCD Display - Google Patents

Abstract

Disclosed are a liquid crystal display device and a method of driving the same, which are driven by a back gate method and two gate low voltages to improve a horizontal line phenomenon.

In the liquid crystal display of the present invention, a plurality of gate lines and a plurality of data lines are arranged in a matrix form, a thin film transistor is connected to the gate line and the data line, and is stored between a pixel electrode and a rear gate line connected to the thin film transistor. A liquid crystal panel on which capacitors are formed; A gate driver driving the gate line in the order of a second gate low voltage, a gate high voltage, and a first gate low voltage; And a data driver for driving the data line.

Back Gate, LOG B Type, Horizontal Line Phenomenon, 2VGL, Storage Capacitor

Description

Liquid crystal display device

1 is a block diagram showing a conventional LOG type liquid crystal display device.

2 is a view showing the lower substrate of FIG.

3 is an internal circuit diagram of a gate driver IC of the 2VGL type liquid crystal display device of FIG.

4 is a waveform diagram of gate voltages of FIG. 3;

5 is a block diagram showing a liquid crystal display device according to the present invention;

6 is a view showing the lower substrate of FIG.

FIG. 7 is an internal circuit diagram of a 2VGL-type gate driver IC of FIG. 5.

8 is a waveform diagram of gate voltages of the liquid crystal display device of the present invention;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of improving image quality by improving problems such as a horizontal line phenomenon between gate lines.

A typical liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, the gate lines and the data lines are arranged in an intersection, and the liquid crystal cells are positioned in an area where the pixels defined by the gate lines and the data lines are provided in the intersection. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to one of the data lines via the source and drain terminals of the thin film transistor TFT, which is a switching element. The gate terminal of the thin film transistor TFT is connected to any one of the gate lines through which the pixel voltage signal is applied to the pixel electrodes of one line.

The driving circuit supplies a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for controlling the gate driver and the data driver, and various driving voltages used in the liquid crystal display device. It is provided with a power supply. The timing controller controls driving timing of the gate driver and the data driver, and supplies a pixel data signal to the data driver. The power supply unit generates driving voltages such as a common voltage Vcom, a gate high voltage VGH, a gate low voltage VGL, and the like, which are required by the liquid crystal display using the input power. The gate driver sequentially supplies the gate high voltage VGH to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel data signal to each of the data lines whenever the gate high voltage VGH is supplied to one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting the light transmittance by an electric field generated between the pixel electrode and the common electrode according to the pixel data signal for each liquid crystal cell.

Among them, the data driver and the gate driver directly connected to the liquid crystal panel are integrated into a plurality of integrated circuits (ICs). Each of the integrated data driver IC and the gate driver IC are mounted on a tape carrier package (TCP) and connected to the liquid crystal panel by a tape automated bonding (TAB) method or mounted on a liquid crystal panel by a chip on glass (COG) method.

Recently, even when the driver ICs are connected to the liquid crystal panel by the TAB method, the liquid crystal display device is further thinned by adopting the LOG type method and eliminating the gate PCB. In particular, the gate PCB is eliminated by forming the signal lines connected to the gate driver ICs that require relatively few signal lines on the liquid crystal panel in a LOG type manner. In other words, the TAB type gate driver ICs are connected in series through signal lines formed on the lower glass of the liquid crystal panel, and receive control signals and driving voltage signals (hereinafter, referred to as gate driving signals) in common. do.

In practice, the liquid crystal display device in which the gate PCB is removed by using the LOG type signal lines has a plurality of data TCPs connected between the liquid crystal panel 1 and the liquid crystal panel 1 and the data PCB 12 as shown in FIG. (8), a plurality of gate TCPs 14 connected to the other side of the liquid crystal panel 1, data driver ICs 10 extended to each of the data TCPs 8, and gate TCP Gate driver ICs 16 mounted on each of the holes 14;

The liquid crystal panel 1 includes a lower substrate 2 having a thin film transistor array together with various signal lines, an upper substrate 4 having a color filter array formed therebetween, and a lower substrate 2 and an upper substrate 4 therebetween. It includes the injected liquid crystal. The liquid crystal panel 1 is provided with an image display area 5 composed of liquid crystal cells formed at each intersection of the gate lines 20 and the data lines 18 to display an image. Data pads (not shown) extending from the data lines 18 and gates extending from the gate lines 20 are formed in the outer region of the lower substrate 2 positioned at the outer portion of the image display area 5. Pads (not shown) are placed. Also, in the outer region of the lower substrate 2, a LOG signal line group 26 for transmitting the gate driving signals supplied to the gate driver IC 16 is located.

The data driver IC 10 is mounted on the data TCP 8. The input pads 24 and the output pads 25 to which the data driver IC 10 is electrically connected are electrically connected to the data pads on the lower substrate 2. In particular, the first data TCP 8 is further formed with a gate drive signal transmission group 22 electrically connected to the LOG type signal line group 26 on the lower substrate 2. The gate driving signal transmission group 22 supplies the gate driving signals supplied from the timing controller (not shown) and the power supply unit (not shown) to the LOG type signal line group 26 via the data PCB 12. .

The data driver ICs 10 convert a digital pixel data signal into a pixel voltage signal, which is an analog signal, and supply the same to the data lines on the liquid crystal panel 1.                         

The gate driver IC 16 is mounted on the gate TCP 14, and a gate drive signal transmission line group 28, input pads 29, and output pads electrically connected to the gate driver IC 16 are provided. 30 is formed. The gate driving signal transmission line group 28 is electrically connected to the LOG type signal line group 26 on the lower substrate 2, and the input pads 29 are electrically connected to the gate driving signal transmission line group 28. The output pads 30 are electrically connected to the gate pads on the lower substrate 2.

The gate driver ICs 16 sequentially supply a scan signal, that is, a gate high contact signal VGH, to the gate lines in response to the gate driving signals. In addition, the gate driver ICs 16 supply the gate low voltage signal VGL to the gate lines in a period other than the period in which the gate high voltage signal VGH is supplied.

The structure and dynamics of the gate driver ICs 16 will be described later in detail with reference to FIG. 3.

FIG. 2 is a diagram illustrating the lower substrate of FIG. 1.

As shown in FIG. 2, the lower substrate 4 includes a plurality of gate lines GL (n−1) to GL (n + 1) arranged in a first direction and the gate lines GL (n). A plurality of data lines DL (m-1) to DL (m + 2) arranged in a second direction perpendicular to −1 to GL (n + 1), and the gate lines GL (n). -1) to GL (n + 1)) and the thin film transistor connected to the data lines DL (m-1) to DL (m + 2), a pixel electrode connected to the thin film transistor, A storage capacitor Cst is formed between the front gate lines.                         

When the n-th gate line GL (n) is driven by the gate high voltage VGH, a data voltage is applied to the pixel electrode on the n-th gate line GL (n), and the data voltage is stored in the storage capacitor. (Cst) is charged. In this case, the gate low voltage VGL is applied to the n−1 th gate line GL (n−1). In this case, the n−1 th gate line (ie, the front gate line) GL (n−) by the data voltage charged in the storage capacitor Cst on the n th gate line (ie, the rear gate line) GL (n). The gate low voltage VGL applied to 1)) is distorted. The data voltage charged in the storage capacitor on the front gate line GL (n−1) is distorted by the gate low voltage VGL. The charged data voltage of the storage capacitor on the n−1 th gate line GL (n−1) affects the gate low voltage of the n−2 th gate line (not shown). As a result, the data voltage charged in the storage capacitor on the n-th gate line (not shown) is distorted. Thus, during one frame, the data voltage charged to the storage capacitor on each gate line affects the gate low voltage of the front gate lines, and the gate low voltage of these front gate lines again charges the story capacitor on the front gate lines. By distorting the data voltage, problems such as a horizontal line phenomenon have occurred.

FIG. 3 shows an internal circuit diagram of the 2VGL gate driver IC of FIG. 1.

As shown in FIG. 3, the gate driver IC 16 includes a plurality of D-flip flops 31, 32, and 33, and a NAND gate connected to the plurality of D-flip flops 31, 32, and 33, respectively. And the first C-MOS transistors 61, 63, and 65 for outputting a predetermined gate signal according to the output signals of the NAND gates 41, 42, and 43, respectively. A plurality of NOT gates 51 and 52 for inverting an output signal of a subsequent NAND gate and first or second gate low voltages VGL1 and VGL2 according to output signals of the plurality of NOT gates 51 and 52. ) Is composed of second C-MOS transistors (62, 64). The operation of the gate driver IC 16 is described as follows. When the first GSP signal 1 is input in synchronization with the GSC signal 1, the first D flip-flop 31 outputs an output signal of 1. Subsequently, the first NAND gate 41 outputs an output signal of 0 to the first C-MOS transistor 61 by the output signal of 1 and the GSC signal 1. Accordingly, as shown in FIG. 4, the gate high voltage VGH is applied from the first C-MOS transistor 61 to the n−1 th gate line GL (n−1).

When the second GSP signal 1 is input in synchronization with the GSC signal 1, the second D flip-flop 32 outputs an output signal of 1. Subsequently, the second NAND gate 42 outputs an output signal of 0 to the first C-MOS transistor 63 by the output signal of 1 and the GSC signal 1. Accordingly, as shown in FIG. 4, the gate high voltage VGH is applied from the first C-MOS transistor 63 to the n-th gate line GL (n). At the same time, the signal output as 0 from the second NAND gate 42 is input to the first NOT gate 51 and output as 1. At this time, the signal output to 1 is input to the second C-MOS transistor 62. Accordingly, as shown in FIG. 4, the second gate low voltage VGL2 is output from the second C-MOS transistor 62. At this time, the first GSP signal becomes 0, and accordingly, 1 is output by the first NAND gate 41. Therefore, the second gate low voltage VGL2 output from the second C-MOS transistor 62 is applied to the n−1 th gate line GL (n−1).

When the second GSP signal 0 is input in synchronization with the GSC signal 1, the second D flip-flop 32 outputs zero. Subsequently, the second NAND gate 42 has an output signal of 0 and an output signal of 1 by the GSC signal 1 being input to the first NOT gate 51 and outputted as 0 to the second C-MOS transistor 62. do. Accordingly, as shown in FIG. 4, the first gate low voltage VGL1 is applied from the second C-MOS transistor 62 to the n−1 th gate line GL (n−1). When the third GSP signal 1 is input in synchronization with the GSC signal 1, the third D flip-flop 33 outputs an output signal of 1. Subsequently, the third NAND gate 43 outputs an output signal of 0 to the first C-MOS transistor 65 by the output signal of 1 and the GSC signal 1. Accordingly, as shown in FIG. 4, the gate high voltage VGH is applied from the first C-MOS transistor 65 to the n + 1th gate line GL (n + 1). At the same time, an output signal of 0 output from the third NAND gate 43 is input to the second NOT gate 52 and output to 1. At this time, the signal output as 1 is input to the second C-MOS transistor 64. Accordingly, as shown in FIG. 4, the second gate low voltage VGL2 is applied to the n-th gate line GL (n) from the second C-MOS transistor 64. Accordingly, the gate high voltage VGH is applied to the n−1 th gate line GL (n−1) during the first 1H period, and then the gate high voltage VGH is applied to the n th gate line GL (n). Applied during the second 1H interval. At this time, the second gate low voltage VGL2 is simultaneously applied to the n−1 th gate line GL (n−1) during the second 1H period. When the gate high voltage VGH is applied to the n + 1 th gate line GL (n + 1) during the third 1H period, the first gate is applied to the n−1 th gate line GL (n-1). The low voltage VGL1 is applied, and the second gate low voltage VGL2 is applied to the n-th gate line GL (n). As described above, the liquid crystal panel of the front gate type can be driven by the 2VGL type.

As described above, the front gate type liquid crystal display affects the gate low voltage of the front gate line due to the data voltage charged in the storage capacitor on the rear gate line, and the gate low voltage is applied to the storage capacitor on the front gate line. There is a problem in that the image quality is deteriorated because the horizontal data is generated by distorting the charged data voltage.

The present invention provides a liquid crystal display device having improved image quality by preventing a horizontal line phenomenon by changing to a rear gate method for generating a storage capacitor between a rear gate line and a front pixel electrode and using two gate low voltages (2VGL). The purpose is.

According to a preferred embodiment of the present invention for achieving the above object, a liquid crystal display device has a plurality of gate lines and a plurality of data lines arranged in a matrix form, a thin film transistor is connected to the gate line and the data line, the thin film A liquid crystal panel in which a storage capacitor is formed between the pixel electrode connected to the transistor and the rear gate line, the gate driver and the data line driving the gate line in the order of the second gate low voltage, the gate high voltage, and the first gate low voltage. A data driver is provided.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

5 is a block diagram illustrating a liquid crystal display according to the present invention.

As shown in FIG. 5, the liquid crystal display device of the present invention includes a liquid crystal panel 101 in which liquid crystal cells are arranged in a matrix, and a plurality of data TCPs connected between the liquid crystal panel 101 and the data PCB 112. 80, a plurality of gate TCPs 114 connected to the other side of the liquid crystal panel 101, data driver ICs 100 mounted on each of the data TCPs 80, and gate TCPs (114) a power supply unit (not shown) for generating driving voltages supplied to the gate driver ICs 116 mounted on each of the gate driver ICs 116 and the data driver ICs 100, And a timing controller (not shown) for controlling the gate driver ICs 116 and the data driver ICs 100.

The liquid crystal panel 101 includes a lower substrate 102 having a thin film transistor array together with various signal lines, an upper substrate 104 having a color filter array formed therein, the lower substrate 102 and the upper substrate 104. It includes a liquid crystal injected in between. The liquid crystal panel 101 is provided with an image display area 105 for displaying an image by liquid crystal cells formed at intersections of gate lines and data lines. Data pads (not shown) extended from data lines and gate pads (not shown) extended from data lines are disposed in the outer area of the lower substrate 102 positioned at the outer portion of the image display area 105. Will be located. In the outer region of the lower substrate 102, a LOG signal line group 126 for transmitting gate driving signals supplied to the gate driver ICs 116 is located.

6 illustrates a lower substrate of the liquid crystal panel 101.

As shown in FIG. 6, the lower substrate 102 includes a plurality of gate lines GL (n-1) to GL (n + 1) arranged in a first direction, and the gate lines GL (n). A plurality of data lines DL (m-1) to DL (m + 2) arranged in a second direction perpendicular to −1 to GL (n + 1), and the gate lines GL (n). -1) to GL (n + 1)) and thin film transistors connected to the data lines DL (m-1) to DL (m + 2), a pixel electrode connected to the thin film transistor, a pixel electrode and a rear end The storage capacitor Cst is formed between the gate lines.

As shown in FIG. 6, when the n−1 th gate line GL (n−1) is driven, a data voltage is applied to the storage capacitor Cst on the n−1 th gate line GL (n). Is charged. In this case, the gate low voltage VGL is applied to the n-2th gate line (that is, the front gate line) (not shown). In other words, as the n-th gate line (that is, the rear gate line GL (n-1)) is driven, the storage capacitor Cst on the rear gate line GL (n-1) is charged. The data voltage affects the gate low voltage VGL of the nth gate line GL (n). That is, in the case of a liquid crystal display device driven by a rear gate method in which a storage capacitor is generated between a pixel electrode on the rear gate line and the front gate line, the horizontal line phenomenon is caused by affecting the gate low voltage of the rear stage rather than the front stage as in the prior art. It is not completely removed. Thus, the internal circuit structure of the conventional gate driver IC is changed to completely eliminate the horizontal line phenomenon. When the internal circuit structure of the conventional gate driver IC is changed, the above-described horizontal line phenomenon is completely eliminated, thereby solving the problem of image quality. Detailed description thereof will be described with reference to FIG. 7.

The data driver ICs 100 convert a digital pixel data signal into an analog signal and supply the same to the data lines on the liquid crystal panel 101.

As described above, in the rear gate method, the data voltage charged in the storage capacitor on the n-1 th gate line GL (n-1) affects the gate low voltage of the n th gate line GL (n). Crazy Therefore, as shown in FIG. 7, the second gate low voltage is driven only by two gate low voltages in order to completely eliminate the horizontal line phenomenon generated in the rear gate method, and only during the 1H period than the gate high voltage VGH. A circuit of the gate driver IC to which (VGL2) is applied first is constructed.

FIG. 7 is an internal circuit diagram of the 2VGL gate driver IC of FIG. 5.

The gate driver ICs 116 may include a plurality of D-flip flops 71, 72, and 73 and NAND gates 81, 82, and 83 connected to the plurality of D-flip flops 71, 72, and 73, respectively. And inverts the first C-MOS transistors 161, 163 and 165 for outputting a predetermined gate signal according to the output signals of the NAND gates 81, 82 and 83, and the GSP signal input to the D-flip flop of the previous stage. Outputting the first or second gate low voltages VGL1 and VGL2 according to the plurality of NOT gates 91, 92 and 93 and output signals of the plurality of NOT gates 91, 92 and 93. 2 C-MOS transistors 162, 164, 166. The operation of the gate driver IC 16 is described as follows.                     

As shown in Fig. 7, when the first GSP 1 is input in synchronization with the GSC signal 1, the first D flip-flop 71 outputs an output signal of 1. Subsequently, the first NAND gate 81 is inputted to the first C-MOS transistor 161 by an output signal of 1 and an output signal of 0 by the GSC (1) signal. Accordingly, as shown in FIG. 8, the gate high voltage VGH is applied from the first C-MOS transistor 161 to the n−1 th gate line GL (n−1). At the same time, the first GSP signal 1 input to the first D flip-flop 71 is input to the second NOT gate 92 and output as 0. The signal output to 0 is input to the second C-MOS transistor 164. Accordingly, as shown in FIG. 8, the second gate low voltage VGL2 is applied to the n-th gate line GL (n) from the second C-MOS transistor 164. When the second GSP signal 1 is input in synchronization with the GSC signal 1, the second D flip-flop 72 outputs an output signal of 1. Subsequently, the second NAND gate 82 is inputted to the first C-MOS transistor 163 by an output signal of 1 and an output signal of 0 by the GSC signal 1. Accordingly, as shown in FIG. 8, the gate high voltage VGH is applied from the first C-MOS transistor 163 to the n-th gate line GL (n). At the same time, the second GSP (1) signal input to the second D flip-flop 72 is input to the third NOT gate 93 and output as 0. The signal output as 0 is input to the second C-MOS transistor 166. Accordingly, as shown in FIG. 8, the second gate low voltage VGL2 is applied from the second C-MOS transistor 166 to the n + 1 th gate line GL (n + 1). At the same time, in the case of the second GSP signal 1 input to the second D-flop flop, the first GSP signal 0 is input to the first D-flip flop. The first GSP signal 0 is input to the second NOT gate 92 and output as 1. The signal output to 1 is input to the second C-MOS transistor 164. Accordingly, as shown in FIG. 8, the first gate low voltage VGL1 is applied from the second C-MOS transistor 164 to the n−1 th gate line GL (n−1). When the third GSP signal 1 is input in synchronization with the GSC signal 1, the third D flip-flop 73 outputs an output signal of 1, and then the third NAND gate 83 outputs an output signal of 1 and An output signal of 0 is input to the first C-MOS transistor 165 by the GSC signal 1. Accordingly, as shown in FIG. 8, the gate high voltage VGH is applied from the first C-MOS transistor 165 to the n + 1th gate line GL (n + 1). As such, when the gate high voltage VGH is applied to the n−1 th gate line GL (n−1), the second gate low voltage VGL2 is applied to the n th gate line GL (n). . When the gate high voltage VGH2 is applied to the n-th gate line GL (n), the first gate low voltage VGL1 is applied to the n-th gate line GL (n-1), and n The second gate low voltage VGL2 is applied to the + 1th gate line GL (n + 1). As a result, the gate voltages of the nth gate line GL (n) and the n + 1th gate line GL (n + 1) are sequentially driven with a delay time equivalent to that of the GOE signal. At this time, the data voltage charged in the storage capacitor on the nth gate line GL (n) affects the gate low voltage of the n + 1th gate line GL (n + 1), but the two gate low voltages ( The first gate low voltage VGL1 and the second gate low voltage VGL2 may be driven to remove distortion of the gate low voltage on the n + 1 th gate line GL (n + 1). That is, as shown in FIG. 8, when the gate high voltage VGH is applied to the n−1 th gate line GL (n−1) during the first 1H period, the n th gate line GL (n) The second gate low voltage VGL2 is applied during the second 1H period. In this case, the data voltage charged in the storage capacitor on the n−1 th gate line GL (n−1) affects the second gate low voltage VGL2 applied to the n th gate line GL (n). Therefore, distortion is caused to the second gate low voltage VGL2. At this time, when the gate high voltage VGH is applied to the n-th gate line GL (n) with the delay time as much as the GOE signal, the distorted first The 2 gate low voltage VGL2 is not applied to the nth gate line GL (n). Thus, the distorted second gate low voltage VGL2 no longer affects the n-th gate line GL (n).

As described above, the horizontal capacitor lines are formed by the gate driver IC driven by the front gate GSP signal to drive the rear gate gate and the rear gate gate to generate the storage capacitor Cst between the pixel electrodes on the rear gate line and the front gate line. The image quality can be improved by improving the phenomenon.

As described above, according to the liquid crystal display device according to the present invention, the defects of the horizontal line phenomenon easily occurring in the front gate method are driven by driving the rear gate method and the two gate low voltages, thereby improving defects such as the horizontal line phenomenon. You can improve the picture quality.

Claims (11)

A liquid crystal panel in which a plurality of gate lines and a plurality of data lines are arranged in a matrix form, a thin film transistor is connected to the gate line and the data line, and a storage capacitor is formed between a pixel electrode connected to the thin film transistor and a rear gate line; A gate driver driving the gate line in the order of a second gate low voltage, a gate high voltage, and a first gate low voltage; And A data driver for driving the data line Liquid crystal display device comprising a. The method of claim 1, And a data voltage supplied by a front gate line is charged in the storage capacitor. The method of claim 2, And the gate high voltage is applied to the front gate line before the rear gate line. The method of claim 1, The gate driver,  A plurality of D-flip flops for outputting sequentially input GSP signals; A plurality of NAND gates for NAND gate processing the output signal of the D-flip-flop; A plurality of first C-MOS transistors outputting the second gate low voltage, the gate high voltage, or the first gate low voltage according to output signals of the plurality of NAND gates; A plurality of NOT gates for inverting the GSP signal input to the D-flip flop at the front end; And A plurality of second C-MOS transistors outputting the first gate low voltage or the second gate low voltage according to an output signal of the NOT gate  Liquid crystal display comprising a. The method of claim 1, And the gate high voltage and the second gate low voltage are supplied during a horizontal period. The method of claim 1, And the first gate low voltage is supplied for the remaining sections except for the section in which the gate high voltage and the second gate low voltage are supplied. Preparing a plurality of gate lines and a plurality of data lines in the thin film transistor in a matrix form; In the liquid crystal display device including a storage capacitor between the pixel electrode connected to the thin film transistor and the rear gate line, Driving the gate line in the order of a second gate low voltage, a gate high voltage, and a first gate low voltage; And Driving the data line Method of driving a liquid crystal display device comprising a. The method of claim 7, wherein       And storing the data voltage supplied by the front gate line in the storage capacitor. The method of claim 7, wherein And wherein the gate high voltage is applied to the front gate line before the rear gate line. The method of claim 7, wherein And the gate high voltage and the second gate low voltage are supplied during a horizontal period. The method of claim 7, wherein And supplying the first gate low voltage for the remaining sections except for the sections in which the gate high voltage and the second gate low voltage are supplied.

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