KR20060002617A - Semiconductor storage devices employing cell switching transistors having multiple channel regions and methods of manufacturing the same - Google Patents

Abstract

Semiconductor storage devices employing cell switching transistors having multiple channel regions and methods of fabrication thereof are provided. The semiconductor memory devices have semiconductor memory cells. Each of the semiconductor memory cells has an integrated circuit substrate and a switching element formed on the integrated circuit substrate. The switching element has multiple channel regions neighboring each other. The switching element is electrically connected to a data storage element. The data storage element may be a programmable resistor such as a phase change resistor or a magnetic tunnel junction structure. Methods of manufacturing the semiconductor memory device are also provided.

Description

Semiconductor memory devices employing cell switching transistors having multiple channel regions and methods of fabricating the same

1 is a schematic view illustrating a programmable memory device according to embodiments of the present invention.

2 is a plan view illustrating a portion of a phase change memory device according to example embodiments.

3A to 9A and FIGS. 10 to 14 are cross-sectional views taken along line II ′ of FIG. 2 to explain phase change memories and manufacturing methods thereof according to embodiments of the present invention.

3B to 9B are cross-sectional views taken along line II-II 'of FIG. 2 to explain phase change memories and manufacturing methods thereof according to embodiments of the present invention.

FIG. 15 is a cross-sectional view taken along line II ′ of FIG. 2 to explain phase change memory devices and a method of manufacturing the same according to other embodiments of the present disclosure.

FIG. 16 is a plan view illustrating a photoresist mask pattern used in fabrication of cell switching transistors of phase change memory devices according to other exemplary embodiments.

FIG. 17 is a cross-sectional view illustrating a cell switching transistor having triple channel pins manufactured using the photoresist mask pattern of FIG. 16.

18A and 18B are cross-sectional views illustrating methods of fabricating cell switching transistors of phase change memory devices according to other exemplary embodiments.

FIG. 19 is a schematic block diagram illustrating a portable electronic device employing phase change memory devices according to embodiments of the present invention.

FIG. 20 is a graph illustrating contact resistance measurement results between GST films and lower electrodes of phase change memory cells fabricated according to the related art and embodiments of the present invention.

FIG. 21 is a graph illustrating measurement results of set / reset characteristics of phase change memory cells manufactured according to the related art.

FIG. 22 is a graph illustrating measurement results of set / reset characteristics of phase change memory cells manufactured according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices and methods of manufacturing the same, and more particularly, to semiconductor memory devices employing cell switching transistors having multiple channels and methods thereof.

Nonvolatile memory devices have a feature that data stored therein is not destroyed even if their power supply is cut off. Accordingly, the nonvolatile memory devices are widely adopted in computers, mobile communication systems, and memory cards.

Flash memory devices are widely used as the nonvolatile memory devices. The flash memory device mainly employs memory cells having a stacked gate structure. The stacked gate structure includes a tunnel oxide layer, a floating gate, an inter-gate dielectric layer, and a control gate electrode sequentially stacked on the channel region. In order to improve the reliability and program efficiency of the flash memory cell, the film quality of the tunnel oxide layer should be improved and the coupling ratio of the cell should be increased.

Instead of the flash memory device, new nonvolatile memory devices such as phase change memory devices have recently been proposed. The unit cell of the phase change memory device may include a switching device (ie, a cell transistor) and a data storage element that is serially connected to the switching device. The data storage element has a lower electrode electrically connected to the switching element and a phase change material layer in contact with the lower electrode. In general, the lower electrode acts as a heater. When a write current (program current) flows through the switching element and the lower electrode, joule heat is generated at an interface between the phase change material film and the lower electrode. This joule heat converts the phase change material film into an amorphous state or a crystalline state. In order to improve the phase transition efficiency of the phase change material film, the contact area between the lower electrode and the phase change material film should be reduced.

The method for minimizing the contact area of the lower electrode is described in US Pat. No. 6,147,395 as "Method for fabricating a small area of contact between electrodes." It has been disclosed by. According to Gilgen, a fine tip serving as a lower electrode (heater) of the phase change memory device is formed by using an isotropic etching process. A phase change material film is formed on the fine tip. As a result, the contact area between the phase change material film and the fine tip (heater) can be minimized.

On the other hand, despite the reduction in the contact area of the lower electrode, the phase transition of the phase change material film requires a large programming current of about 1 mA. Thus, the cell transistor should be designed to have sufficient current drivability to provide the program current. However, in order to improve the current driving capability of the cell transistor, the area occupied by the cell transistor must be increased. In particular, when the cell transistor is a planar MOS transistor, the program current is directly related to the channel width of the planar MOS transistor. Therefore, there is a limit to improving the integration density of the phase change memory device.

 SUMMARY OF THE INVENTION The present invention has been made in an effort to provide semiconductor memory cells suitable for improving the degree of integration and the improvement of program characteristics.

Another technical problem to be solved by the present invention is to provide programmable memory cells suitable for improving the program characteristics as well as the degree of integration.

Another technical problem to be achieved by the present invention is to provide high performance programmable memory devices suitable for improving the integration characteristics as well as the program characteristics.

Another technical problem to be achieved by the present invention is to provide a high performance phase change memory device suitable for improving the integration characteristics as well as the program characteristics.

Another technical problem to be achieved by the present invention is to provide electronic devices employing a high performance programmable memory device suitable for the improvement of the program characteristics as well as the integration.

Another object of the present invention is to provide methods for manufacturing a programmable memory cell that can improve the integration and program characteristics.

Another object of the present invention is to provide methods for manufacturing a phase change memory device capable of improving the degree of integration and program characteristics.

According to one aspect of the present invention, semiconductor memory cells are provided. The semiconductor memory cells include an integrated circuit board and a switching element formed on the integrated circuit board. The switching element has multiple channel regions neighboring each other. The switching element is electrically connected to a data storage element.

In some embodiments of the present invention, the switching element includes at least two channel fins protruding from the integrated circuit substrate and spaced apart from each other, and first and second impurity regions formed in the substrate and spaced apart from each other by the channel fins. And an insulated gate electrode covering the channel pins. In this case, the data storage element may be electrically connected to either one of the first and second impurity regions.

In other embodiments, the data storage element may be a programmable resistor. The programmable resistor may include a first electrode electrically connected to one of the first and second impurity regions, a programmable material film on the first electrode, and a second electrode on the programmable material film. The programmable material film may be a phase change material film such as a chalcogenide film.

According to another aspect of the present invention, programmable memory cells are provided. The programmable memory cells include an integrated circuit board and a pin body protruding from the integrated circuit board. First and second impurity regions spaced apart from each other are provided in the fin body. The fin body between the first and second impurity regions is covered with an insulated gate electrode. One of the first and second impurity regions is electrically connected to a programmable resistor.

In some embodiments of the present invention, the fin body may include at least one channel fin protruding from the substrate. In this case, the gate electrode may be disposed to cross while covering the channel fin.

In other embodiments, the programmable resistor may be a phase change resistor.

According to another aspect of the present invention, programmable memory elements are provided. The programmable memory devices include an integrated circuit board having a cell array region and a peripheral circuit region. A cell switching device is provided on the integrated circuit board in the cell array region. The cell switching element has multiple channel regions. The cell switching element is electrically connected to a programmable resistor. A peripheral circuit MOS transistor is provided in the integrated circuit board in the peripheral circuit region.

In some embodiments of the present disclosure, the cell switching device may include a fin body protruding from the integrated circuit board in the cell array region, first and second cell impurity regions formed in the fin body and spaced apart from each other, and And an insulated cell gate electrode covering the fin body between the first and second cell impurity regions. In this case, the programmable resistor may be electrically connected to any one of the first and second cell impurity regions. The fin body may have at least two channel fins protruding from the substrate. In this case, the cell gate electrode may be disposed to cross the channel fins.

In other embodiments, the programmable resistor may be a phase change resistor.

In other embodiments, the peripheral circuit MOS transistor may have a planar-type single channel region.

In example embodiments, the peripheral circuit MOS transistor may include a peripheral active region defined in the integrated circuit board in the peripheral circuit region, first and second peripheral impurity regions formed at both ends of the peripheral active region, and the A peripheral gate electrode may be disposed between the first and second peripheral impurity regions to cross the upper portion of the peripheral active region. In addition, a cell gate insulating layer may be interposed between the cell gate electrode and the fin body, and a peripheral gate insulating layer may be interposed between the peripheral gate electrode and the peripheral active region.

In another embodiment, the thickness of the peripheral gate insulating layer may be the same as or different from the thickness of the cell gate insulating layer. In addition, the width of the peripheral gate electrode may be the same as or different from the width of the cell gate electrode.

In other embodiments, the programmable resistor may include first and second electrodes as well as a programmable material layer interposed between the electrodes. Furthermore, either one of the first and second electrodes may be electrically connected to the bit line.

According to another aspect of the present invention, phase change memory elements are provided. The phase change memory devices include an integrated circuit board having a cell array region and a peripheral circuit region. A first fin body is provided on the integrated circuit board in the cell array region. The first fin body has first and second connections that connect both ends of the first group of channel pins protruding from the integrated circuit board and the first group of channel pins, respectively. Top surfaces and sidewalls of the first group of channel fins are covered with a first cell gate electrode. Cell source regions and cell drain regions are provided in the first and second connectors, respectively. The cell drain region is electrically connected to the lower electrode, and the lower electrode is surrounded by a molding film. In addition, the molding film has a surface step so as to have a protrusion. A phase change material film pattern is disposed in or on the molding film. An upper electrode pattern is provided on the phase change material film pattern.

In some embodiments of the present invention, the first group of channel pins may include at least two channel pins.

In other embodiments, the phase change material film pattern may be a GST (GeSbTe) alloy film doped with at least one of nitrogen and silicon.

In other embodiments, the upper electrode pattern may include an upper electrode, a glue layer pattern, and a hard mask pattern that are sequentially stacked.

In other embodiments, the molding layer may be an insulating layer having a higher thermal conductivity than that of the silicon oxide layer.

In still other embodiments, the molding layer may be an insulating layer serving as an oxygen barrier layer.

In other embodiments, the sidewall of the lower electrode may be surrounded by the contact spacer.

In example embodiments, the protrusion of the molding layer may be self-aligned with the phase change material layer pattern.

In example embodiments, the lower electrode may penetrate the protrusion of the molding layer.

In another embodiment, when the phase change material layer pattern is disposed on the molding layer, the sidewall of the protrusion and the sidewall of the phase change layer pattern may be covered with an oxygen barrier layer.

In another embodiment, when the phase change material layer pattern is disposed on the molding layer, the sidewalls of the protrusion, the sidewall of the phase change material layer pattern, and the upper electrode pattern may be covered with an oxygen barrier layer. have.

In another embodiment, when the phase change material layer pattern is disposed in the molding layer, the sidewalls of the protrusion and the upper electrode pattern may be covered with an oxygen barrier layer.

In still other embodiments, a peripheral active region may be defined in a predetermined region of the integrated circuit board in the peripheral circuit region, and a peripheral circuit MOS transistor may be provided in the peripheral active region. The peripheral circuit MOS transistor may include a peripheral gate electrode which crosses an upper portion of the peripheral channel region between the peripheral source / drain regions as well as peripheral source and peripheral drain regions formed at both ends of the peripheral active region, respectively. . The peripheral channel region may be a flat single channel region. The width of the peripheral gate electrode may be greater than the width of the first cell gate electrode.

In other embodiments, a cell gate insulating layer may be interposed between the first cell gate electrode and the channel fins, and a peripheral gate insulating layer may be interposed between the peripheral gate electrode and the peripheral channel region. The thickness of the peripheral gate insulating layer may be greater than the thickness of the cell gate insulating layer.

In other embodiments, a peripheral metal silicide layer may be provided on at least the peripheral source / drain regions of the first cell gate electrode, the cell source / drain regions, the peripheral gate electrode, and the peripheral source / drain regions. Can be.

According to yet another aspect of the present invention, electronics are provided that employ programmable memory elements. The electronics may include at least one programmable memory device used as a data storage media, a processor connected to the programmable memory device to process code and data, and bus structures through bus architectures. An input / output device for performing data communication. The programmable memory device includes an integrated circuit board and a pin body protruding from the board. Cell source regions and cell drain regions spaced apart from each other are provided in the fin body. An upper surface and sidewalls of the fin body between the cell source region and the cell drain region are covered with a cell gate electrode. The cell drain region is electrically connected to a programmable resistor.

In some embodiments of the present invention, the programmable resistor may be a phase change resistor. The phase change resistor may have a lower electrode electrically connected to the cell drain region, a phase change material film pattern stacked on the lower electrode, and an upper electrode stacked on the phase change material film pattern.

In other embodiments, the substrate having the programmable resistor may be covered with an oxygen barrier film.

According to another aspect of the present invention, methods of manufacturing programmable memory cells are provided. The methods include forming a pin body protruding from an integrated circuit board. A cell gate electrode is formed across the upper portion of the fin body to cover the upper surface and sidewalls of the fin body. A cell source region and a cell drain region are formed in the fin body adjacent to both sidewalls of the cell gate electrode. An interlayer insulating film is formed on the substrate having the cell gate electrode and the cell source / drain regions. A programmable resistor electrically connected to the cell drain region is formed on the interlayer insulating film.

According to another aspect of the present invention, methods of manufacturing a phase change memory device are provided. These methods include preparing an integrated circuit substrate having a cell array region and a peripheral circuit region. A preliminary cell device isolation film and a peripheral device isolation film are formed on the integrated circuit board in the cell array region and the integrated circuit board in the peripheral circuit region, respectively. The preliminary cell isolation layer and the peripheral isolation layer define a cell active region and a peripheral active region, respectively. The preliminary cell device isolation layer is partially etched to form a recessed cell device isolation layer and simultaneously protrudes the cell active region. The protruding cell active region serves as a fin body. A pair of cell gate electrodes covering the top surface and sidewalls of the fin body and crossing the upper portion of the fin body is formed to form a peripheral gate electrode crossing the upper portion of the peripheral active region. Impurity ions are implanted into the fin body by using the cell gate electrodes as an ion implantation mask to form a common source region in the fin body between the cell gate electrodes and at the same time, a cell drain region at both ends of the fin body. Form them. The peripheral gate electrode is used as an ion implantation mask to implant impurity ions into the peripheral active region to form a peripheral source region and a peripheral drain region. A molding film is formed on the substrate having the cell drain regions, the common source region, and the peripheral source / drain regions. Lower electrodes penetrating the molding layer are formed. The lower electrodes are electrically connected to the cell drain regions. A phase change material film and an upper electrode film are sequentially formed on the substrate having the lower electrodes. The upper electrode layer and the phase change material layer are patterned to form a phase change material layer pattern and an upper electrode sequentially stacked on the lower electrodes. The phase change material layer pattern and the upper electrode constitute a phase change resistor pattern, and the molding layer forms the phase change resistor patterns to have protrusions protruding relatively below the phase change resistor patterns. It can be etched. An oxygen barrier layer is formed on the substrate having the phase change resistor patterns and the protrusions.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout the specification.

1 is a schematic view for describing a semiconductor memory device according to example embodiments. The semiconductor memory device may be a programmable memory device such as a phase change memory device or a magnetic random access memory device (MRAM device).

Referring to FIG. 1, the semiconductor memory device (ie, the programmable memory device) includes a cell array region CA and a peripheral circuit region PCA. The cell array area CA includes a plurality of word lines WL, a plurality of bit lines BL orthogonal to the word lines WL, and the word lines WL and the bit lines And a plurality of programmable memory cells 100 arranged at intersections of the BL. The programmable memory cells 100 may correspond to phase change memory cells or magnetic RAM cells. In addition, the peripheral circuit area PCA includes first and second integrated circuits PCA1 and PCA2 for driving the programmable memory cells 100. The first integrated circuit PCA1 may include a row decoder for selecting one of the word lines WL, and the second integrated circuit PCA2 may include the bit lines BL. It may include a column decoder and a sense amplifier for selecting any one of the.

Each of the programmable memory cells 100 includes a programmable resistor RP electrically connected to any one of the bit lines BL and a switching element electrically connected to the programmable resistor RP. . The programmable resistor RP may include first and second electrodes as well as a programmable material layer interposed between the electrodes. For example, when the programmable resistor RP is a phase change resistor, the programmable material film corresponds to a phase change material film. In addition, when the programmable resistor RP is a magnetic tunnel junction structure, the programmable material layer may include a pinned layer, a tunneling insulating layer, and a free layer that are sequentially stacked. The switching element may correspond to an access MOS transistor TA having a gate electrode and source / drain regions.

In the present exemplary embodiment, for convenience of description, it is assumed that the programmable memory cells 100 are the phase change memory cells and the programmable resistors RP are the phase change resistors. In this case, the first terminal of the phase change resistor RP is electrically connected to the drain region of the access MOS transistor TA, and the second terminal of the phase change resistor RP is connected to the bit line. Is electrically connected to BL). In addition, the gate electrode of the access MOS transistor TA is electrically connected to any one of the word lines WL, and the source region of the access MOS transistor TA is a common source line CSL; Is electrically connected).

To selectively store data in any one of the phase change memory cells 100, the bit connected to the access MOS transistor TA of the selected cell CL and connected to the selected cell CL is turned on. A write current Iw, that is, a program current, is applied through the line BL. In this case, the electrical resistance of the phase change resistor RP may vary depending on the amount of the writing current Iw. For example, when the phase change material is heated by the write current Iw to a temperature between its crystallization temperature and a melting point and the heated phase change material is cooled, The phase change material is transformed into a crystalline state. In contrast, when the phase change material is heated to a temperature higher than the melting point by the write current Iw and the molten phase change material is quenched, the phase change material is changed into an amorphous state. The resistivity of the phase change material having the crystalline state is lower than that of the phase change material having the amorphous state. Accordingly, by detecting the current flowing through the phase change material in the read mode, it is possible to determine whether the information stored in the phase change resistor RP is logic "1" or logic "0". As a result, the access MOS transistor TA must provide sufficient write current to cause a phase transition of the phase change material. In addition, the access MOS transistor TA is preferably designed to have a structure suitable for realization of high integration density in addition to high current drivability.

In embodiments of the present invention, the access MOS transistor TA may be a MOS transistor having multiple channel regions formed to be adjacent to each other. For example, the access MOS transistor TA may be a MOS transistor having a three-dimensional structure having at least two channel pins. In this case, channel regions may be formed in each of the channel fins.

The MOS transistor of the three-dimensional structure is formed on each of the plurality of channel fins formed on an integrated circuit substrate and spaced apart from each other, a gate electrode covering the plurality of channel fins and insulated from the substrate by a gate insulating film, respectively. Source / drain regions adjacent the channel regions and spaced apart from each other by the channel regions. The plurality of channel fins may be formed in a body protruding from the substrate. Alternatively, the access MOS transistor TA may be a fin field effect transistor having a single channel fin. The fin field effect transistor includes a fin body protruding from an integrated circuit board, source / drain regions formed in the fin body and spaced apart from each other, and an upper portion of the fin body (ie, channel fin) between the source / drain regions. A gate electrode covering the face and sidewalls. Even in this case, the fin field effect transistor may have multiple channel regions formed on the horizontal top surface and the vertical sidewalls of the channel fin.

FIG. 2 is a plan view showing a portion of the programmable memory device, that is, the phase change memory device shown in FIG. 1. 3A to 9A and FIGS. 10 to 14 are cross-sectional views taken along line II ′ of FIG. 2 to explain methods of manufacturing phase change memory devices according to example embodiments. FIGS. 3B to 9B are FIGS. Are cross-sectional views taken along line II-II 'of FIG. 2 to explain methods of manufacturing phase change memory devices according to example embodiments.

2, 3A, and 3B, an integrated circuit board 1 having a cell array area CA and a peripheral circuit area PCA is prepared. The pad oxide film 103 and the trench mask film are formed on the integrated circuit board 1. The trench mask layer may be formed of a material layer having an etch selectivity with respect to the integrated circuit board 1. For example, when the integrated circuit board 1 is a semiconductor substrate such as a silicon substrate, the trench mask film may be formed of a silicon nitride film. The trench mask layer is patterned to form a cell trench mask pattern 105c and a peripheral trench mask pattern 105p in the cell array region CA and the peripheral circuit region PCA, respectively. The pad oxide layer 103 may also be etched while the trench mask layer is patterned.

The integrated circuit board 1 is etched using the trench mask patterns 105c and 105p as etch masks, so that the cell trench region and the peripheral trench region are respectively formed in the cell array region CA and the peripheral circuit region PCA. To form. The cell trench region may be formed to have a different depth from that of the peripheral trench region. The cell trench region defines a cell active region 109c in the cell array region CA, and the peripheral trench region defines a peripheral active region 109p in the peripheral circuit region PCA. Subsequently, an insulating film is formed on the substrate having the trench regions, and the insulating film is planarized to form a preliminary cell isolation layer 107c and a peripheral isolation layer 107p respectively filling the cell trench region and the peripheral trench region. At least the preliminary cell device isolation layer 107c of the device isolation layers 107c and 107p may be formed to have an upper surface that is the same as or lower than the surface of the cell active region 109c.

The first photoresist pattern 110 is formed on the substrate having the device isolation layers 107c and 107p. The first photoresist pattern 110 is formed to have a first opening 110a that crosses a central portion of the cell trench mask pattern 105c. Alternatively, the first photoresist pattern 110 may be formed to have second openings 110b exposing both ends of the cell trench mask pattern 105c in addition to the first opening 110a.

2, 4A, and 4B, the cell trench mask pattern 105c is etched using the first photoresist pattern 110 as an etch mask to form a pair of pairs on the cell active region 109c. A pair of preliminary reverse fin mask patterns 105c 'are formed. Subsequently, the first photoresist pattern 110 is removed. A second photoresist pattern 111 is formed on the substrate from which the first photoresist pattern 110 is removed to expose the cell array region CA. The preliminary reverse fin mask patterns 105c 'are isotropically etched using the second photoresist pattern 111 as an etch mask to form final reverse fin mask patterns 105c ″. When the inverse fin mask patterns 105c 'are formed of a silicon nitride film, the isotropic etching process may be performed using a phosphoric acid solution (H ₃ PO ₄ ) Next, the second photoresist pattern 111 may be used. Remove it.

In other embodiments of the present invention, the final reverse fin mask patterns 105c ″ and the second photoresist pattern 111 are used as ion implantation masks before removing the second photoresist pattern 111. Impurity ions IM may be implanted into the cell active region 109c to form channel impurity regions CH. The channel impurity regions CH may be formed in a subsequent process. Alternatively, the impurity ions IM may be implanted to the entire surface of the cell active region 109c using the second photoresist pattern 111 as an ion implantation mask. In this case, the impurity ions IM are implanted with high energy to pass through the final reverse pin mask patterns 105c ″. The impurity ions IM may be implanted after removing the second photoresist pattern 111. In this case, the peripheral trench mask pattern 105p may also serve as an ion implantation mask. After implanting the impurity ions IM, a heat treatment process may be performed. The heat treatment process is performed to activate the impurity ions in the channel impurity regions CH.

2, 5A, and 5B, an insulating film is formed on the substrate from which the second photoresist pattern 111 is removed. The insulating layer may be formed of the same material layer as the isolation layers 107c and 107p. For example, the insulating film may be formed of a silicon oxide film using chemical vapor deposition (CVD) technology. An additional peripheral isolation layer 113p covering the peripheral device isolation layer 107p by planarizing the insulating layer until the peripheral trench mask pattern 105p and the reverse pin mask patterns 105c ″ are exposed. And a fin mask pattern 113c filling a region between the inverted fin mask patterns 105c ″. Subsequently, the peripheral trench mask pattern 105p and the reverse pin mask patterns 105c ″ are removed to expose the peripheral active region 109p and simultaneously expose two regions of the cell active region 109c. The peripheral trench mask pattern 105p and the reverse pin mask patterns 105c ″ may also be removed using a phosphoric acid solution. The pad oxide layer 103 under the mask patterns 105p and 105c ″ may also be removed while the mask patterns 105p and 105c ″ are removed.

A third photoresist pattern 115 exposing the cell array region CA is formed on the substrate from which the peripheral trench mask pattern 105p and the reverse pin mask patterns 105c ″ are removed. FIGS. 4A and 4B. When the formation of the channel impurity regions CH described with reference to FIG. 4B is omitted, the third photoresist pattern 115 and the fin mask pattern 113c may be used as ion implantation masks. Impurity ions may be implanted into the active region 109c to form channel impurity regions, whereas the entire surface of the cell active region 109c may be formed using only the third photoresist pattern 115 as an ion implantation mask. Impurity ions may be implanted to form a channel impurity region The impurity ions in the channel impurity regions may also be diffused through a heat treatment process.

The exposed regions of the cell active region 109c are selectively etched using the third photoresist pattern 115 and the fin mask pattern 113c as etch masks, ie, a pair of fin trench regions, ie First and second fin trench regions 117t 'and 117t "are formed. The first trench regions 117t' are respectively disposed along sidewalls thereof, as shown in FIG. 5B. 119a and a second channel fin 119b. Similarly, the second trench region 117t " also has first channel fins (< / RTI > 119c and the second channel pin 119d. In addition, the first and second fin trench regions 117t 'and 117t "may have a first connection 109a corresponding to the center of the cell active region 109c as shown in FIG. 5A. In addition, second and third connection parts 109b 'and 109b "corresponding to both ends of the cell active region 109c are defined. That is, ends of the first and second channel fins 119a and 119b adjacent to the first fin trench region 117t 'are defined by the first and second connectors 109a and 109b'. And end portions of the first and second channel fins 119c and 119d of FIG. 2, which are adjacent to the second fin trench region 117t ″, by the first and third connections 109a and 109b ″. Connected.

In addition to the first and second channel fins 119a and 119b adjacent to the first fin trench region 117t ', the first and second connection portions 109a and 109b' may include a first double fin body (a first). double fin body; 109d ') and the first and third connection portions 109a and 109b in addition to the first and second channel fins 119c and 119d adjacent to the second fin trench region 117t ″. &Quot;) constitutes a second double fin body 109d. As a result, the first and second double fin bodies 109d ', 109d " Share it.

Meanwhile, when the isotropically etch time of the preliminary inverse fin mask patterns 105c 'shown in FIGS. 4A and 4B is appropriately adjusted, the channel fins 119a, 119b, 119c, and 119d are formed in the photographic process. It may be formed to have fine widths W smaller than the resolution limit.

In another embodiment, the substrate 1 under the fin trench regions 117t 'and 117t "using the third photoresist pattern 115 and the fin mask pattern 113c as an ion implantation mask. Impurity ions may be implanted into the channel stop layer 121c, and the channel stop layer 121c may be formed by implanting impurity ions having the same conductivity type as the substrate 1. have.

2, 6A, and 6B, the fin mask pattern 113c is removed to expose upper surfaces of the fin bodies 109d ′ and 109d ″, and the preliminary cell isolation layer 107c is partially formed. Etching is performed to form a recessed cell device isolation layer 107c '. As a result, outer walls of the fin bodies 109d' and 109d "are exposed to relatively protrude the fin bodies. When the fin mask pattern 113c is formed of the same material film as the preliminary cell device isolation layer 107c, the fin mask pattern 113c and the preliminary cell device isolation layer 107c may be a single etching process. Can be etched using The top surface of the recessed cell device isolation layer 107c 'may be positioned at the same level as the bottom surfaces of the fin trench regions 117t' and 117t ″. Alternatively, the recessed cell device isolation layer may be disposed at the same level. The top surface of 107c 'may be higher or lower than the bottom surfaces of the fin trench regions 117t' and 117t ". After forming the recessed cell device isolation layer 107c ', the third photoresist pattern 115 is removed.

In other embodiments of the inventive concept, an etching process for forming the recessed cell device isolation layer 107c ′ may be performed after removing the third photoresist pattern 115. In this case, the additional peripheral device isolation film 113p may be etched while forming the recessed cell device isolation film 107c '.

In example embodiments, the fin mask pattern 113c and the additional peripheral device isolation layer in the cell array region CA and the peripheral circuit region PCA may be removed after the third photoresist pattern 115 is removed. Simultaneously etching the entire surface 113p and partially etching the preliminary cell device isolation layer 107c and the peripheral device isolation layer 107p to form a recessed cell device isolation layer 107c 'and a recessed peripheral device isolation layer (not shown). can do. In this case, not only the outer walls of the fin bodies 109d 'and 109d ", but also the outer walls of the peripheral active region 109p are exposed. That is, the fin bodies may also be formed in the peripheral circuit region PCA. have.

According to still other embodiments of the present invention, one channel pin is configured instead of the pair of dual pin bodies 109d ', 109d ", which are composed of the four channel pins 119a, 119b, 119c, and 119d. A pair of single fin bodies may be formed, specifically, the trench mask patterns 105c and 105p, the peripheral device isolation layer 107p, and the ones shown in FIGS. 3A and 3B. After the preliminary cell isolation layer 107c is formed, a photoresist covering the peripheral circuit region PCA and exposing the cell array region CA instead of using the first photoresist pattern 110 shown in FIG. 3A. It is also possible to directly recess only the preliminary cell isolation layer 107c using a pattern, that is, according to the present embodiments, the process of forming the fin trench regions 117t 'and 117t "of FIG. 5A is omitted. Can be. Accordingly, since the whole of the cell active region 109c is relatively protruded, a pair of single fin bodies connected to each other are formed in the cell array region CA.

2, 7A, and 7B, the surface of the substrate having the recessed cell device isolation layer 107c ′ is cleaned. The cleaning process may be performed using a chemical solution containing hydrofluoric acid. The additional peripheral device isolation layer 113p may be etched during the cleaning process. As a result, a final peripheral isolation layer 107p 'surrounding the peripheral active region 109p is formed.

The cell gate insulating layer 123c and the peripheral gate insulating layer 123p are formed on the surfaces of the fin bodies 109d 'and 109d ″ and the surface of the peripheral active region 109p, respectively. The cell gate insulating layer 123c The peripheral gate insulating layer 123p may have a thickness different from that of the peripheral gate insulating layer 123p. For example, when the peripheral gate insulating layer 123p corresponds to the gate insulating layer of the high voltage MOS transistor, the peripheral gate insulating layer 123p may be formed. The peripheral gate insulating layer 123p may be formed to be thicker than the cell gate insulating layer 123c. In contrast, when the peripheral gate insulating layer 123p corresponds to a gate insulating layer of a low voltage MOS transistor, the peripheral gate insulating layer 123p may be formed in the cell gate insulating layer 123c. It may be formed to have the same thickness as 123c.

A gate conductive layer is formed on a substrate having the gate insulating layers 123c and 123p and the gate conductive layer is patterned to pass through the peripheral gate electrode 125p and the fin trench regions crossing the upper portion of the peripheral active region 109p. (A pair of cell gate electrodes 125c covering (117t ', 117t "in FIGS. 6A and 6B)). In particular, the cell gate electrodes 125c form the channel fins 119a, 119b, 119c, It is formed to cover the upper surfaces and the side walls of the 119d, thereby increasing the channel width compared to planar MOS transistors within a limited area. In this case, the cell gate electrodes 125c may serve as word lines WL of FIG. 1. In addition, the peripheral gate electrode 125p may be formed to extend across the fin bodies. Different from the cell gate electrodes 125c For example, when the peripheral gate electrode 125p is a low voltage PMOS transistor or a high voltage MOS transistor, the width (corresponding to a peripheral channel length; Lp) of the peripheral gate electrode 125p is The width Lp of the peripheral gate electrode 125p may be greater than the width of the cell gate electrodes 125c (corresponding to the cell channel length Lc). Alternatively, when the peripheral gate electrode 125p is a low voltage NMOS transistor, the peripheral gate width Lp may be equal to the cell gate width Lc.

According to still other embodiments of the present disclosure, the recess process of the preliminary cell isolation layer 107c described with reference to FIGS. 6A and 6B may be omitted. That is, after removing the pin mask pattern 113c, the recess process of the preliminary cell device isolation layer 107c may be omitted. In this case, the preliminary cell device isolation layer 107c corresponds to the final cell device isolation layer. If the recess process of the preliminary cell device isolation layer 107c is omitted, the cell gate electrodes 125c may be easily patterned as illustrated in FIGS. 18A and 18B.

2, 8A, and 8B, the peripheral active region (109p of FIG. 7A) and the fin bodies 109d ′, 109d ″ using the gate electrodes 125c and 125p as ion implantation masks. N-type impurity ions may be implanted into the N-type low-concentration impurity regions 127. When the peripheral gate electrode 125p corresponds to the gate electrode of the PMOS transistor, the N-type impurity ions may be formed. Can be selectively implanted only into the fin bodies 109d ', 109d ". Subsequently, gate spacers 129 are formed on sidewalls of the gate electrodes 125c and 125p. The gate spacers 129 may be formed of an insulating film, such as a silicon oxide film or a silicon nitride film.

 The fin bodies 109d ′, 109d ″, that is, the first to third connection portions, using the gate spacers 129 on the cell gate electrodes 125c and their sidewalls as ion implantation masks. N-type impurity ions are implanted into 109a, 109b ', and 109b "of FIG. 7A to form N-type high concentration impurity regions having a higher concentration than the N-type low concentration impurity region 127. As a result, cell source regions 131s are formed in the first connectors 109a, and cell drain regions 131d are formed in the second and third connectors 109b 'and 109b ″. The source region 131s serves as a common source region.

Subsequently, P-type or N-type impurity ions are implanted into the peripheral active region 109p by using the spacer 129 on the peripheral gate electrode 125p and its sidewalls as ion implantation masks to thereby surround the peripheral source region. 133s and the peripheral drain region 133d are formed.

When the peripheral circuit MOS transistor TP is an NMOS transistor, the cell source / drain regions 131s and 131d and the peripheral source / drain regions 133s and 133d are subjected to a single ion implantation process (a single step). It can be formed simultaneously using of ion implantation process.

As a result, a pair of access MOS transistors TA including the cell gate electrodes 125c and the cell source / drain regions 131s and 131d in the fin bodies in the cell array region CA, That is, a pair of fin field effect transistors are formed, and the peripheral circuit MOS transistor TP including the peripheral gate electrode 125p and the peripheral source / drain regions 133s and 133d is formed in the peripheral active region 109p. Is formed.

When the upper surface of the peripheral device isolation layer 107p 'is the same as or higher than the upper surface of the peripheral active region 109p, the peripheral circuit MOS transistor TP corresponds to a planar-type MOS transistor. In other words, the peripheral circuit MOS transistor TP is formed to have a planar-type single channel region. However, when the upper surface of the peripheral device isolation layer 107p 'is lower than the upper surface of the peripheral active region 109p, the peripheral circuit MOS transistor TP corresponds to a fin field effect transistor having a single fin body.

Meanwhile, each of the access MOS transistors TA manufactured by the above-described embodiments has multiple channel regions as a channel between the cell source region 131s and the cell drain regions 131d. . For example, a first access MOS transistor TA formed in the first fin body 109d 'of FIG. 6A may be spaced apart from each other by the first fin trench region 117'. First and second channel regions formed at 119a and 119b, respectively. Specifically, the first channel region may include two vertical channel portions formed on both sidewalls of the first channel fin 119a and a horizontal channel portion formed on an upper surface of the first channel fin 119a. The second channel region may include two vertical channel portions formed on both sidewalls of the second channel fin 119b and a horizontal channel portion formed on an upper surface of the second channel fin 119b. . Similarly, the second access MOS transistor TP formed in the second fin body 109d ″ of FIG. 6A may also have the first and second channel fins spaced apart from each other by the second fin trench region 117 ″. Four vertical channel portions and two horizontal channel portions formed in 119c and 119d may be included. As a result, each of the access MOS transistors TA may include six channel parts.

18A and 18B, when the cell isolation layer 107c is not recessed, the first access MOS transistor TA contacts the first fin trench region 117 ′. Two vertical channel portions formed on the inner walls of the first and second channel fins 119a and 119b and two horizontal channel portions formed on the upper surfaces of the first and second channel fins 119a and 119b. It may include four channel parts configured. In this case, the second access MOS transistor TP may also include four channel units.

Furthermore, in the case where the process of forming the channel blocking layers 121c is omitted, horizontal channel regions are further formed below the bottom surfaces of the first and second fin trench regions 117t 'and 117t ". As a result, according to the present embodiments, each of the access MOS transistors TA is formed to have multiple channel regions, although embodiments of the present invention will be described by taking a phase change memory device as an example. The access MOS transistors TA having the multi-channel regions may be applied to programmable memory devices other than the phase change memory device, for example, the access MOS transistors TA having the multi-channel regions. May be applied to the switching transistors of the magnetic RAM cell.

Subsequently, the peripheral metal silicide layer 135p may be selectively formed on at least the peripheral source / drain regions 133s and 133d using conventional salicide (self-aligned silicide) techniques. For example, after forming a silicidation blocking layer (not shown) covering the cell array region CA and exposing the peripheral circuit region PCA, the peripheral gate electrode 125p and The peripheral metal silicide layer 135p may be selectively formed on the peripheral source / drain regions 133s and 133d. When a capping layer made of an insulating layer is formed on the peripheral gate electrode 125p, the peripheral metal silicide layer 135p may be selectively formed only on the peripheral source / drain regions 133s and 133d. The silicided stop layer may be formed of a silicon nitride layer.

According to another exemplary embodiment of the present invention, the cell metal silicide layer 135c and the peripheral metal silicide layer (131c) are disposed on the cell source / drain regions 131s and 131d and the peripheral source / drain regions 133s and 133d, respectively. 135p) may be selectively formed. According to another embodiment of the present invention, as shown in FIGS. 8A and 8B, the gate electrodes 125c and 125p and the source / drain regions 131s, 131d, 133s, and 133d are selectively provided. The metal silicide layers 135c and 135p may be formed.

The lower etch stop layer 137 is formed on the substrate including the metal silicide layers 135c and 135p. The lower etch stop layer 137 may be formed of a silicon nitride layer having an etching selectivity with respect to an insulating layer such as a silicon oxide layer.

2, 9A, and 9B, a planarized lower insulating layer 139 is formed on the lower etch stop layer 137. The lower insulating layer 139 may be formed of a silicon oxide layer. The lower etch stop layer 137 and the lower insulating layer 139 form a lower interlayer insulating layer 141. The process of forming the lower etch stop layer 137 may be omitted. Patterning the lower interlayer insulating layer 141 to expose the cell metal silicide layers 135c on the cell source / drain regions 131s and 131d, together with the cell source / drain contact holes 141s 'and 141d'. Peripheral source / drain contact holes 141s "and 141d" exposing the peripheral metal silicide layers 135p on the peripheral source / drain regions 133s and 133d are formed.

Cell source / drain contact plugs 143s' and 143d in the cell source / drain contact holes 141s' and 141d 'and the peripheral source / drain contact holes 141s "and 141d" respectively using a conventional method. And peripheral source / drain contact plugs 143s ", 143d". The source / drain contact plugs 143s ', 143s ", 143d', and 143d" may be formed of a tungsten film. An upper interlayer insulating layer 26 is formed on a substrate having the source / drain contact plugs 143s ', 143s ", 143d', and 143d". The upper interlayer insulating layer 26 may be formed by sequentially stacking the upper etch stop layer 23 and the upper insulating layer 25. In this case, the upper etch stop layer 23 is preferably formed of an insulating film having an etch selectivity with respect to the upper insulating film 25. For example, when the upper insulating layer 25 is formed of a silicon oxide layer, the upper etch stop layer 23 may be formed of a silicon nitride layer. The process of forming the upper etch stop layer 23 may be omitted. The upper interlayer insulating layer 26 and the lower interlayer insulating layer 141 constitute an interlayer insulating layer.

2 and 10, cell drain pads 27d ′ and a common source line (eg, by using a conventional damascene process in the upper interlayer insulating layer 26 in the cell array region CA). common source line (27s'). In addition, the peripheral drain pad 27d " and the peripheral parts of the upper interlayer insulating film 26 in the peripheral circuit area PCA are formed while forming the cell drain pads 27d 'and the common source line 27s'. Source pads 27s "may be formed. The cell drain pads 27d ', the common source line 27s', the peripheral drain pad 27d ", and the peripheral source pad 27s" may be formed of a metal film such as a tungsten film, and the common source line 27s' may be formed to be parallel to the cell gate electrodes 125c. The cell drain pads 27d 'and the common source line 27s' are formed to contact the cell drain contact plugs 143d 'and the cell source contact plug 143s', respectively, and the peripheral drain pad. 27d ″ and the peripheral source pad 27s ″ are formed to contact the peripheral drain contact plug 143d ″ and the peripheral source contact plug 143s ″, respectively. As a result, the common source line 27s 'and the cell drain pads 27d' are electrically connected to the cell source region 131s and the cell drain regions 131d, respectively, and the peripheral source pad 27s. &Quot;) and the peripheral drain pad 27d " are electrically connected to the peripheral source region 133s and the peripheral drain region 133d, respectively.

A molding layer 29 is formed on the substrate having the cell drain pads 27d ', the common source line 27s', the peripheral drain pad 27d ", and the peripheral source pad 27s". The molding film 29 is preferably formed of an insulating film having a higher thermal conductivity than a silicon oxide film used as a conventional interlayer insulating film. In addition, the molding layer 29 may be formed of an insulating layer serving as an oxygen barrier layer. For example, the molding layer 29 may be formed of a nitride layer such as a silicon oxynitride layer (SiON layer) or a silicon nitride layer. This improves the cooling efficiency, that is, the quenching efficiency for phase transition of the phase change material film formed in a subsequent process, between the phase change material film and the upper and lower electrodes in contact therewith. This is to prevent the oxygen atoms from penetrating into the interfaces. Subsequently, the molding layer 29 is patterned to form phase change resistor contact holes 29a exposing the cell drain pads 27d '.

2 and 11, a conformal contact spacer layer 34 may be formed on a substrate having the phase change resistor contact holes 29a. The contact spacer layer 34 is preferably formed under the use of oxygen gas under vacuum. If the contact spacer layer 34 is formed using a process gas containing oxygen gas, the contact spacer layer 34 is formed at a temperature as low as possible in order to suppress oxidation of the exposed cell drain pads 27d '. It is preferably formed from.

The contact spacer layer 34 may be formed of a single contact spacer layer or a double contact spacer layer. The double contact spacer layer may be formed by sequentially stacking a lower contact spacer layer 31 and an upper contact spacer layer 33. In this case, the lower contact spacer layer 31 may be formed of a silicon oxynitride layer using a plasma CVD technique performed at a temperature lower than 500 ° C., and the upper contact spacer layer 33 may be higher than 500 ° C. It can be formed into a silicon nitride film using a low pressure CVD technique carried out in. The single contact spacer film may be formed of a silicon nitride film using a low pressure CVD technique or a plasma CVD technique.

2 and 12, the contact spacer layer 34 is anisotropically etched to expose the cell drain pads 27d ′. As a result, contact spacers 34a are formed on sidewalls of the phase change resistor contact holes 29a. When the contact spacer layer 34 is formed by sequentially stacking the lower contact spacer layer 31 and the upper contact spacer layer 33, each of the contact spacers 34a may be formed as shown in FIG. 12. The outer contact spacer 31a covering the sidewall of the phase change resistor contact hole 29a and the inner contact spacer 33a covering the inner sidewall of the outer contact spacer 31a are formed. In this case, a lower portion of the outer contact spacer 31a may be exposed after the anisotropic etching process. The effective diameter of the phase change resistor contact holes 29a may be smaller than the resolution limit of the photographing process due to the presence of the contact spacer 34a. That is, according to the present embodiment, the formation of the contact spacers 34a is accompanied by a reduction in the size of the initial phase change resistor contact holes 29a and the oxidation of the cell drain pads 27d '. May lead to the suppression of.

Subsequently, a lower electrode layer is formed on the substrate including the contact spacers 34a to fill the phase change resistor contact holes 29a. The lower electrode layer may be formed of a conductive layer such as a titanium nitride layer or a titanium aluminum nitride layer (TiAlN). Subsequently, the lower electrode layer is planarized to expose the molding layer 29. As a result, lower electrodes 35 are formed in the phase change resistor contact holes 29a surrounded by the contact spacers 34a. During the planarization of the lower electrode layer, the lower electrode layer may be excessively etched to form recessed lower electrodes in the phase change resistor contact holes 29a.

The phase change material layer 37 and the upper electrode layer 39 are sequentially formed on the substrate having the lower electrodes 35. The phase change material layer 37 may be formed of a chalcogenide layer. For example, the phase change material layer 37 may be made of germanium (Ge), stevidium (Sb), and tellurium (Te). ) Alloy layer (Te _x Sb _y Ge _{(100- (x + y))} alloy film (hereinafter referred to as "GST alloy film"). Here, "x" may be 20 to 80, and "y" may be 5 to 50. In other words, the GST alloy film is composed of tellurium (Te) having a concentration of 20 atomic% to 80 atomic%, stevirium (Sb) having a concentration of 5 atomic% to 50 atomic%, and greater than 0 atomic% and 75 atomic% It may contain germanium (Ge) having a concentration less than or equal to. Furthermore, the phase change material layer 37 may be formed of a GST alloy layer doped with at least one of nitrogen and silicon. In this case, the doped GST alloy layer has a higher resistivity than the undoped GST alloy layer. Accordingly, the doped GST alloy film generates higher joule heat than the undoped GST alloy film at the same current level. As a result, when the phase change material film 37 is formed of the doped GST alloy film, phase transition efficiency of the phase change material film 37 may be improved. The upper electrode film 39 may be formed of a conductive film such as a titanium nitride film.

A hard mask layer 43 may be further formed on the upper electrode layer 39. In this case, it is preferable to further form a glue layer 41 on the upper electrode film 39 before the hard mask film 43 is formed. The glue film 41 is formed to improve the adhesion between the upper electrode film 39 and the hard mask film 43. The hard mask layer 43 may be formed of a silicon oxide layer, and the glue layer 41 may be formed of a silicon nitride layer.

2 and 13, the hard mask layer 43 is patterned to form hard mask patterns 43a positioned on the lower electrodes 35. Subsequently, the glue film (41 in FIG. 12), the upper electrode film (39 in FIG. 12) and the phase change material film (37 in FIG. 12) are successively using the hard mask patterns 43a as etching masks. Etching forms phase change resistor patterns 44a on the lower electrodes 35. As a result, each of the phase change resistor patterns 44a is formed to have the phase change material film pattern 37a, the upper electrode 39a, and the glue film pattern 41a sequentially stacked. The phase change material layer pattern 37a and the upper electrode 39a sequentially stacked on the lower electrode 35 together with the lower electrode 35 constitute a programmable resistor, that is, a phase change resistor.

Furthermore, after the phase change resistor patterns 44a are formed, the molding layer 29 may be partially etched. Accordingly, the neighboring phase change material layer patterns 37a are completely separated, and the molding layer 29 is self-aligned with the phase change material layer patterns 37a. Have protrusions. As a result, after the phase change resistor patterns 44a are formed, the molding layer 29 may have a surface step difference (S).

An oxygen barrier layer 48 is formed on the substrate having the phase change resistor patterns 44a. As a result, the oxygen barrier layer 48 is formed to cover the sidewalls of the protrusions of the molding layer 29 as well as the upper surfaces and sidewalls of the phase change resistor patterns 44a. The oxygen barrier film 48 may be formed of a nitride film such as a silicon oxynitride film or a silicon nitride film. In addition, the oxygen barrier layer 48 may be formed as a single oxygen barrier layer or a double oxygen barrier layer. The double oxygen barrier layer may be formed by sequentially stacking the lower oxygen barrier layer 45 and the upper oxygen barrier layer 47. The oxygen barrier layer 48 may include the phase change material layer patterns 37a and the upper electrodes as well as interfaces between the phase change material layer patterns 37a and the lower electrodes 35 in a subsequent process. It is formed to prevent oxygen atoms from penetrating into the interfaces between 39a. This is because when the oxygen atoms penetrate the interfaces between the phase change material film patterns 37a and the electrodes 35 and 39a, the phase change material film patterns 37a are oxidized or contaminated, and thus their inherent characteristics. (their own property) is lowered. As a result, the oxygen barrier layer 48 completely surrounds the sidewalls and the upper surfaces of the phase change resistor patterns 44a together with the sidewalls of the protrusions of the molding layer 29 and the phase change resistor patterns 44a. The lower surfaces of the substrates may be in contact with the molding layer 29 which serves as an oxygen barrier layer, thereby preventing external oxygen atoms from penetrating into the interfaces of the phase change material layer patterns 37a.

In addition, even when the oxygen barrier layer 48 is formed, oxygen atoms must not penetrate along the top / bottom surfaces of the phase change material layer patterns 37a. The oxygen barrier layer 48 may be formed using an in-situ process without a vacuum break after an etching process for forming the phase change resistor patterns 44a. Further, when the oxygen barrier film 48 is formed of the single oxygen barrier film, the single oxygen barrier film is a nitride film such as a silicon oxynitride film or a silicon nitride film using a plasma CVD technique performed at a temperature lower than 350 ° C. It can be formed as. Alternatively, the single oxygen barrier film may be formed of a nitride film such as a silicon oxynitride film or a silicon nitride film using an atomic layer deposition technique (ALD technique) performed at a temperature lower than 350 ° C.

On the other hand, when the oxygen barrier film 48 is formed of the double oxygen barrier film, the lower oxygen barrier film 45 may be formed of the same material film as the single oxygen barrier film deposited at a temperature lower than 350 ° C. The upper oxygen barrier film 47 may be formed of a nitride film such as a silicon oxynitride film or a silicon nitride film using a plasma CVD technique or a low pressure CVD technique performed at a temperature higher than 350 ° C.

2 and 14, an insulating film, such as a silicon oxide film, is formed on the oxygen barrier film 48. Subsequently, the insulating layer is planarized to form a planarized lower interlayer insulating layer 49 exposing the oxygen barrier layer 48 on the phase change resistor patterns 44a. The oxygen barrier layer 48 prevents oxygen atoms from penetrating along upper and lower surfaces of the phase change material layer patterns 37a while forming the lower interlayer insulating layer 49. In other words, the oxygen barrier layer 48 is deteriorated at the interface between the upper and lower electrodes 39a and 35 of the phase change resistor patterns 44a and the phase change material layer patterns 37a. prevent.

The upper electrodes may be patterned by patterning the lower interlayer insulating layer 49, the exposed oxygen barrier layer 48, the hard mask patterns 43a, the glue layer patterns 41a, and the molding layer 29. A drain wiring contact hole 49d "and a source wiring contact hole 49s exposing the peripheral drain pad 27d" and the peripheral source pad 27s "as well as the contact holes 49a exposing the 39a. Form "). Contact plugs 51, drain wiring contact plugs 51d ", and source wiring contact plugs 51s" in the contact holes 49a, drain wiring contact holes 49d ", and source wiring contact holes 49s", respectively. ). The contact plugs 51, 51d ″, and 51s ″ may be formed of a conductive film such as a tungsten film. Bit line pads 53 and a drain wiring line forming a lower metal layer on a substrate having the contact plugs 51, 51d ″, and 51s ″, and patterning the lower metal layer to cover the contact plugs 51. A drain wiring 53d "covering the contact plug 51d" and a source wiring 53s "covering the source wiring contact plug 51s" are formed. The lower metal film may be formed of a metal film such as an aluminum film or an aluminum alloy film.

An upper interlayer insulating film 55 is formed on a substrate having the bit line pad 53, a drain wiring 53d ″, and a source wiring 53s ″, and the upper interlayer insulating film 55 is patterned to form the bit. Bit line contact holes 55a exposing the line pads 53 are formed. An upper metal layer is formed on the substrate having the bit line contact holes 55a, and the upper metal layer is patterned to cover the bit line contact holes 55a to cross the upper portions of the cell gate electrodes 7c. It forms the squeezing bitline 57. The upper metal film may also be formed of a metal film such as an aluminum film or an aluminum alloy film. The passivation film 62 is formed on the substrate having the bit line 57. The passivation film 62 may be formed by sequentially stacking the silicon oxide film 59 and the silicon nitride film 61.

FIG. 15 is a cross-sectional view taken along line II ′ of FIG. 2 to explain a method of forming phase change memory devices according to other embodiments of the inventive concept.

2 and 15, the peripheral circuit MOS transistor (TP), the pin field effect on the integrated circuit board 1 using the same methods as described with reference to Figures 3a-9a, 10 and 11 Transistors, source / drain pads 27s ', 27s ", 27d', 27d", molding film 29, phase change resistor contact holes 29a, and spacer film 34 are formed. Next, the spacer layer 34 is anisotropically etched to form contact spacers 34a shown in FIG. 12. The process of forming the contact spacers 34a may be omitted. A phase change material film is formed on the substrate having the contact spacers 34a to fill the phase change resistor contact holes 29a. The phase change material film is formed of the same material film as the phase change material film 37 described with reference to FIG. 12. The phase change material layer is planarized to expose the surface of the molding layer 29. As a result, fine phase change material film patterns 201 are formed in the phase change resistor contact holes 29a.

An upper electrode layer is formed on the substrate having the phase change material layer patterns 201. The upper electrode film may be formed of a conductive film such as a titanium nitride film. A hard mask layer may be further formed on the upper electrode layer. In this case, it is preferable to further form a glue layer on the upper electrode film before forming the hard mask film. The glue film is formed to improve the adhesion between the upper electrode film and the hard mask film. The hard mask layer may be formed of a silicon oxide layer, and the glue layer may be formed of a silicon nitride layer.

The hard mask layer, the glue layer, and the upper electrode layer are etched to form upper electrode patterns on the phase change material layer patterns 201. As a result, each of the upper electrode patterns is formed to have the upper electrode 203, the glue film pattern 205, and the hard mask pattern 207 stacked in order. In addition, after the upper electrode patterns are formed, the molding layer 29 may be partially etched. Accordingly, the neighboring upper electrodes 203 are completely separated, and the molding layer 29 has protrusions self-aligned with the upper electrode patterns. As a result, after forming the upper electrode patterns, the molding layer 29 may have a surface step difference (S). The oxygen barrier film 48 described with reference to FIG. 13 is formed on a substrate having the upper electrode patterns. The processes performed after the oxygen barrier film 48 is formed are the same as those described with reference to FIG. 14.

According to the embodiments shown in FIG. 15, the phase change material film patterns 201 are formed in the molding film 29 serving as an oxygen barrier film. That is, the phase change material film patterns 201 are formed in place of the lower electrodes 35 shown in FIG. 14. In this case, the cell drain pads 27d 'serve as lower electrodes. As a result, the cell drain pad 27d ′, the phase change material film pattern 201, and the upper electrode 203 constitute a programmable resistor, that is, a phase change resistor. Therefore, when a write current flows through the fine phase change material layer patterns 201, Joule heat generated by the write current may be increased. In other words, the write efficiency of phase change memory cells can be improved.

Now, phase change memory elements having phase change memory cells according to embodiments of the present invention will be described.

Referring again to FIGS. 2, 9B and 14, an integrated circuit board 1 having a cell array region CA and a peripheral circuit region PCA is provided. A peripheral device isolation layer 107p 'is provided in a predetermined region of the integrated circuit board 1 in the peripheral circuit region PCA. The peripheral device isolation layer 107p ′ defines a peripheral active region (109p in FIG. 2). In addition, a cell device isolation film 107c 'recessed in a predetermined region of the integrated circuit board 1 in the cell array region CA is provided. The recessed cell device isolation layer 107c ′ defines fin bodies that protrude relatively from the integrated circuit board 1. The fin bodies may comprise a pair of single fin bodies or a pair of multi-fin bodies. For example, the fin bodies may include first and second double fin bodies (109d ′ and 109d ″ in FIG. 6A).

The first dual pin body 109d 'may be connected to both ends of the first group of channel pins (ie, the first and second channel pins 119a and 119b) and the both ends of the first group of channel pins 119a and 119b. First and second connecting portions 109a and 109b 'of FIG. 6A, respectively, for connecting. The second double pin body 109d ″ shares the first connection portion 109a. That is, the second double pin body 109d ″ includes the first connection portion 109a and the first connection portion 109a. A third connection connecting the second group of channel pins (ie, first and second channel pins 119c and 119d in FIG. 2) and the ends of the second group of channel pins 119c and 119d extending from 109b ″ of FIG. 6A).

A pair of cell gate electrodes 125c is provided to traverse an upper portion of the pair of dual fin bodies 109d 'and 109d ", that is, one of the cell gate electrodes 125c is A top surface and sidewalls of the first group of channel fins 119a and 119b, and the other of the cell gate electrodes 125c is a top surface of the channel fins 119c and 119d of the second group. And cover the sidewalls and sidewalls.

The cell gate electrodes 125c are insulated from the fin bodies 109d 'and 109d ″ by a cell gate insulating layer 123c. In the first connection 109a between the cell gate electrodes 125c. A cell source region 131s, that is, a common source region, is provided, and cell drain regions 131d are provided in the second and third connectors 109b ′ and 109b ″. As a result, the pair of fin bodies are provided with a pair of access MOS transistors, that is, a pair of pin field effect transistors.

Channel blocking layers (1) on the surface of the substrate 1 between the channel fins 119c and 119d of the second group as well as the surface of the substrate 1 between the channel fins 119a and 119b of the first group. 121c) may be provided. The channel blocking layers 121c may be regions doped with impurities of the same conductivity type as the substrate 1. In addition, the channel blocking layers 121c may have a higher impurity concentration than the substrate 1.

Each of the access MOS transistors TA has multiple channel regions between the cell source region 131s and the cell drain region 131d. For example, a first access MOS transistor TA formed in the first fin body 109d 'of FIG. 6A may be spaced apart from each other by the first fin trench region 117t'. First and second channel regions formed at 119a and 119b, respectively. The first channel region may include two vertical channel portions formed on both sidewalls of the first channel fin 119a and a horizontal channel portion formed on an upper surface of the first channel fin 119a. The second channel region may include two vertical channel portions formed on both sidewalls of the second channel fin 119b and a horizontal channel portion formed on an upper surface of the second channel fin 119b. Similarly, the second access MOS transistor TP formed in the second fin body 109d ″ of FIG. 6A may also include four vertical channel portions and two horizontal channel portions. As a result, the access MOS transistor Each of the fields TA may include six channel portions.

Meanwhile, in other embodiments, if the cell isolation layer 107c is not recessed as shown in FIGS. 18A and 18B, the first access MOS transistor TA may be formed in the first fin trench region 117t. Two vertical channel portions formed in the inner walls of the first and second channel fins 119a and 119b in contact with ') and upper surfaces of the first and second channel fins 119a and 119b. It may include four channel portions consisting of two horizontal channel portions. Similarly, the second access MOS transistor TP formed in the second fin body 109d ″ of FIG. 6A also has the first and second channel fins spaced apart from each other by the second fin trench region 117t ″. It may include four channel portions formed in (119c and 119d of FIG. 2).

Furthermore, when the channel blocking layers 121c are not provided, the channel fins 119c of the second group together with the surface of the substrate 1 between the channel fins 119a and 119b of the first group. , Horizontal channel regions may be further formed on the surface of the substrate 1 between 119d. As a result, according to the present embodiments, each of the access MOS transistors TA has multiple channel regions.

Although the above-described embodiments of the present invention are described by taking a phase change memory device as an example, the access MOS transistors TA having the multi-channel regions may be applied to programmable memory devices other than the phase change memory device. . For example, the access MOS transistors TA having the multi-channel regions may be applied to switching transistors of a magnetic RAM cell.

A peripheral circuit MOS transistor (TP in FIG. 7A) is provided in the peripheral active region 109p. The peripheral circuit MOS transistor TP is disposed between the peripheral source / drain regions 133s and 133d together with the peripheral source region 133s and the peripheral drain region 133d respectively formed at both ends of the peripheral active region 109p. A peripheral gate electrode 125p across the top of the channel region of the substrate. As a result, the peripheral circuit MOS transistor TP has a planar single channel region. Alternatively, the peripheral circuit MOS transistor may be a fin type field effect transistor having a channel region formed in a single channel fin.

The peripheral gate electrode 125p is insulated from the peripheral active region 109p by the peripheral gate insulating layer 123p. The peripheral gate insulating layer 123p may have a thickness different from that of the cell gate insulating layer 123c. For example, when the peripheral circuit MOS transistor TP is a high voltage MOS transistor, the peripheral gate insulating layer 123p may be thicker than the cell gate insulating layer 123c. In contrast, when the peripheral circuit MOS transistor TP is a low voltage MOS transistor, the peripheral gate insulating layer 123p may have the same thickness as the cell gate insulating layer 123c.

Meanwhile, the width of the peripheral gate electrode 125p (corresponding to the peripheral channel length; Lp) may be the same as or different from the width of the cell gate electrode 125c (corresponding to the cell channel length; Lc). For example, when the peripheral circuit MOS transistor TP is a high voltage MOS transistor or a PMOS transistor, the peripheral gate width Lp may be larger than the cell gate width Lc. In contrast, when the peripheral circuit MOS transistor TP is a low voltage NMOS transistor, the peripheral gate width Lp may be equal to the cell gate width Lc.

A peripheral metal silicide layer 135p is provided on at least the peripheral source / drain regions 133s and 133d of the gate electrodes 125c and 125p and the source / drain regions 131s, 131d, 133s, and 133d. Can be.

The lower interlayer insulating layer 141 and the upper interlayer insulating layer 26 are sequentially stacked on the substrate having the fin field effect transistors and the peripheral circuit MOS transistor. The cell source region 131s is electrically connected to a cell source contact plug 143s ′ penetrating the lower interlayer insulating layer 141, and the cell drain regions 131d penetrate the lower interlayer insulating layer 141. Is electrically connected to the cell drain contact plugs 143d '. In addition, the peripheral source region 133s is electrically connected to a peripheral source contact plug 143s ″ passing through the lower interlayer insulating layer 141, and the peripheral drain region 133d connects the lower interlayer insulating layer 141. It is electrically connected to the peripheral drain contact plug 143d "penetrating.

The cell source contact plugs 143s' are electrically connected to a common source line 27s' disposed in the upper interlayer insulating layer 26, and the cell drain contact plugs 143d 'are electrically connected to the upper interlayer insulating layer 26. ) Is electrically connected to the cell drain pads 27d 'disposed in the. The common source line 27s ′ may be disposed to be parallel to the cell gate electrodes 125c. The common source line 27s' may be grounded. The peripheral source contact plug 143s ″ may be electrically connected to a peripheral source pad 27s ″ disposed in the upper interlayer insulating layer 26, and the peripheral drain contact plug 143d ″ may be electrically connected to the upper interlayer insulating layer 26. It may be electrically connected to the peripheral drain pad 27d ″ disposed in the insulating film 26.

A molding film 29 is stacked on the common source line 27s ', the cell drain pads 27d', the peripheral drain pad 27d ″, the peripheral source pad 27s ″, and the upper interlayer insulating layer 26. . The molding layer 29 may have a surface step S to have protrusions on the cell drain pads 27d ′. The molding layer 29 is preferably an insulating layer having a higher thermal conductivity than the silicon oxide layer. In addition, the molding film 29 is preferably an insulating film that serves as an oxygen barrier film. For example, the molding layer 29 may be a nitride layer such as a silicon oxynitride layer or a silicon nitride layer. The cell drain pads 27d ′ are electrically connected to lower electrodes 35 passing through the protrusions of the molding layer 29. Sidewalls of the lower electrodes 35 may be surrounded by contact spacers 34a.

Each of the contact spacers 34a includes an inner contact spacer 33a surrounding a sidewall of the lower electrode 35 and an outer contact surrounding an outer sidewall of the inner contact spacer 33a. An outer contact spacer 31a. A lower portion of the outer contact spacer 31a may extend to contact the lower electrode 35. The outer contact spacer 31a may be a plasma CVD oxynitride film formed at a temperature lower than 500 ° C., and the inner contact spacer 33a may be a low pressure CVD nitride film formed at a temperature higher than 500 ° C.

Phase change resistor patterns 44a are disposed on the protrusions of the molding layer 29. The phase change resistor patterns 44a may be self-aligned with the protrusions. Each of the phase change resistor patterns 44a is a phase change material film pattern 37a electrically connected to the lower electrode 35 and an upper electrode 39a stacked on the phase change material film pattern 37a. It may include. The lower electrode 35, the phase change material film pattern 37a, and the upper electrode 39a constitute a programmable resistor, that is, a phase change resistor. The phase change material layer pattern 37a may be a chalcogenide layer, such as an alloy layer of germanium (Ge), stevilium (Sb), and tellurium (Te). In addition, the phase change material layer pattern 37a may be a GST alloy layer doped with at least one of nitrogen and silicon.

Each of the phase change resistor patterns 44a may further include a glue film pattern 41a and a hard mask pattern 43a that are sequentially stacked on the upper electrode 39a. The glue film patterns 41a correspond to a wetting layer for improving adhesion between the hard mask patterns 43a and the upper electrodes 39a. For example, when the hard mask patterns 43a and the upper electrodes 39a are silicon oxide films and titanium nitride films, the glue film patterns 41a may be silicon nitride films.

The substrate having at least the phase change resistor patterns 44a is covered with an oxygen barrier film 48. As described above, when the molding layer 29 includes protrusions, the oxygen barrier layer 48 covers sidewalls and upper surfaces of the phase change resistor patterns 44a and the sidewalls of the protrusions. . The oxygen barrier layer 48 may be a single oxygen barrier layer or a double oxygen barrier layer. The single oxygen barrier film may be a nitride film formed using a plasma CVD technique or an atomic layer deposition technique (ALD technique) performed at a temperature lower than 350 ° C. More specifically, the nitride layer may be a silicon oxynitride layer or a silicon nitride layer.

Meanwhile, the double oxygen barrier layer may include a lower oxygen barrier layer 45 and an upper oxygen barrier layer 47 that are sequentially stacked. In this case, the lower oxygen barrier film 45 may be the same material film as the single oxygen barrier film formed at a temperature lower than 350 ° C., and the upper oxygen barrier film 45 may be plasma at a temperature higher than 350 ° C. Or a nitride film such as a silicon oxynitride film or a silicon nitride film formed using a CVD technique or a low pressure CVD technique.

A lower interlayer insulating film 49 is provided on the oxygen barrier film 48. The lower interlayer insulating layer 49 may have a flat upper surface such that the oxygen barrier layer 48 on the phase change resistor patterns 44a is exposed. The upper electrodes 39a may be electrically connected to the contact plugs 51 passing through the exposed oxygen barrier layer 48, the hard mask patterns 41a, and the glue layer patterns 41a. In addition, the peripheral drain pad 21d ″ and the peripheral source pad 21s ″ respectively pass through the lower interlayer insulating layer 49, the oxygen barrier layer 48, and the molding layer 29. It can be electrically connected to the plug 51d "and the source wiring contact plug 51s".

The contact plugs 51 may be covered with bit line pads 53. In addition, the drain wiring contact plug 51d ″ may be covered by the drain wiring 53d ″, and the source wiring contact plug 51s ″ may be covered by the source wiring 53s ″.

The substrate having the bit line pads 53, the drain wiring 53d ″, and the source wiring 53s ″ is covered with an upper interlayer insulating layer 55. The bit line 57 is disposed on the upper interlayer insulating layer 55. The bit line 57 is electrically connected to the bit line pads 53 through bit line contact holes 55a passing through the upper interlayer insulating layer 55. In addition, the bit line 57 is disposed to cross the upper portions of the cell gate electrodes 7c. The substrate having the bit line 57 is covered with a passivation film 62. The passivation layer 62 may include a silicon oxide layer 59 and a silicon nitride layer 61 that are sequentially stacked.

The phase change memory elements shown in FIG. 15 differ in the form of phase change material film patterns from the phase change memory elements described with reference to FIG. Referring to FIG. 15 again, the phase change material layer patterns 201 of the phase change memory devices according to the exemplary embodiments may be disposed to fill the phase change resistor contact holes 29a passing through the molding layer 29. do. In addition, upper electrode patterns are provided on the phase change material layer patterns 201. Each of the upper electrode patterns may include an upper electrode 203, a glue layer pattern 205, and a hard mask pattern 207 that are sequentially stacked. As a result, according to the present embodiments, the phase change material film patterns 201 are provided instead of the lower electrodes 35 shown in FIG. 14.

FIG. 16 is a photoresist mask pattern PM aligned with trench mask patterns 105p and 105c of FIG. 3A to describe a triple channel structure of an access MOS transistor of a semiconductor memory device according to still other embodiments of the inventive concept. Is a plan view showing a part of In the present embodiments, the photoresist mask pattern PM is formed instead of the first photoresist pattern 110 described with reference to FIG. 3A.

Referring to FIG. 16, the photoresist mask pattern PM may have a cross-shaped opening (a region indicated by a dotted line DL) for dividing the cell trench mask pattern 105c into four parts described with reference to FIGS. 3A and 3B. Located within; H). The photoresist mask pattern PM may further include first and second openings H1 and H2 exposing both ends of the cell trench mask pattern 105c in addition to the opening H. When the manufacturing processes described with reference to FIGS. 3A through 7A and 3B through 7B are performed using the photoresist mask pattern PM described above, three channel pins may be formed as shown in FIG. 17 corresponding to FIG. 7B. It will be apparent to those skilled in the art that a triple fin body may be formed.

Referring to FIG. 17, the triple fin body may include the first and second channel fins 119a 'and 119a', which are relatively protruding from the substrate 1. A third channel pin 119c 'positioned between 119b'). In this case, the widths W of the first and second channel fins 119a 'and 119b' may also be smaller than the limit resolution of the photolithography process as illustrated in FIG. 5B. As a result, according to the present invention, an access MOS transistor having a fin body having four or more channel fins by modifying the shape of the opening of the photoresist mask pattern PM may also be provided.

Furthermore, although not shown in the drawings, the present invention provides semiconductor memory devices by a combination of the embodiments described with reference to FIGS. 3A to 9A, 3B to 9B, 10 to 17, 18A and 18B. You can also provide For example, the semiconductor memory devices according to the present invention may include access MOS transistors having triple fin bodies while adopting the preliminary cell device isolation layer 107c as a final cell device isolation layer.

19 is a schematic block diagram of a portable electronic device 600 employing semiconductor memory devices, ie programmable memory devices, in accordance with embodiments of the present invention.

Referring to FIG. 19, the portable electronic device 600 includes at least one programmable memory device 602 serving as a data storage media and a processor 604 connected to the programmable memory device 602. Include. The programmable memory device 602 may be a magnetic RAM device or a phase change memory device that adopts a programmable resistor as a data storage element. In particular, when the programmable memory device 602 is the phase change memory device, the phase change memory device is shown in FIGS. 2, 3A to 9A, 3B to 9B, 10 to 17, and 18A. And the embodiments described with reference to FIG. 18B. The portable electronic device 600 may correspond to a portable notebook computer, a digital video camera, or a cellular phone. In this case, the processor 604 and the programmable memory device 602 are installed on a board and used as a program memory for storing code and data for execution of the processor 604. The programmable memory device 602 may be mounted on one chip together with the processor 604.

The portable electronic device 600 may exchange data with another electronic product such as a personal computer or a network of computers through the input / output device 606. The input / output device 606 may provide data to a peripheral bus line of a computer, a high speed digital transmission line, or a wireless transmission / reception antenna. The data communication between the processor 604 and the input / output device 606 as well as the data communication between the processor 604 and the programmable memory device 602 use conventional computer bus architectures. Can be done.

Experimental Examples; examples>

Hereinafter, various measurement results of samples manufactured according to the prior art and the embodiments of the present invention will be described.

20 is a graph showing lower electrode contact resistance characteristics of phase change memory cells fabricated according to the related art and embodiments of the present invention. Here, the lower electrode contact resistance means a contact resistance between the lower electrode and the phase change material film. In FIG. 20, the horizontal axis represents split groups for the oxygen barrier film, and the vertical axis represents contact resistance Rc between the GST films and the lower electrodes.

Phase change memory cells showing the measurement results of FIG. 20 were fabricated using the process conditions described in Table 1 below.

  Process parameters Prior art                  The present invention  Sample A    Sample B    Sample C    Sample D      Molding film                 Silicon oxynitride film (SiON) Outer contact spacer          Silicon oxynitride film (SiON; plasma CVD) Internal contact spacer            Silicon Nitride (SiN; Low Pressure CVD)     Bottom electrode          Titanium nitride film (TiN), diameter: 50 nm)    Phase change material film            GST alloy film (GeSbTe alloy film)     Upper electrode             Titanium Nitride (TiN)   Oxygen barrier membrane   None SiON film (200 ℃, PECVD, 200Å) SiN film 200 ° C, PECVD, 200Å) Lower SiN Film (200 ℃, PECVD, 200Å) Upper SiN Film (400 ℃, PECVD, 200Å)

20 and Table 1, phase change memory cells fabricated according to the prior art have a nonuniform lower electrode contact resistance Rc distributed within a range of about 1,000 (ohms / contact) to about 10,000 (ohms / contact). Seemed. In contrast, phase change memory cells fabricated in accordance with embodiments of the present invention exhibited a uniform bottom electrode contact resistance (Rc) distributed within a range of about 500 (ohms / contact) to about 1,200 (ohms / contact). . In particular, phase change memory cells fabricated in accordance with an embodiment of the present invention employing a double oxygen barrier film are highly stable in lower electrode contact resistance within a range between about 500 (ohms / contact) and about 600 (ohms / contact). Rc).

FIG. 21 is a graph showing set / reset characteristics of phase change memory cells fabricated according to the prior art, and FIG. 22 is a set / reset characteristics of phase change memory cells fabricated according to an embodiment of the present invention. It is a graph showing. 21 and 22, the horizontal axes represent the number of program cycles (N) of the phase change memory cells, i.e., the number of writing cycles, and the vertical axes represent the resistance of the phase change resistor per unit cell. (R _GST ). Here, the conventional phase change memory cells are manufactured using the same process conditions as those of Samples A of [Table 1], and the phase change memory cells according to the present invention are the same processes as Samples C of [Table 1]. Made using the conditions.

The respective program cycles are performed by sequentially applying a single reset pulse and one set pulse to the phase change resistors of the phase change memory cells. Each of the reset pulse and the set pulse was applied for 100 ms. In addition, the reset pulse was generated to have a write current of about 1.5 mA to convert the GST film of the phase change resistor into an amorphous state, and the set pulse was generated in the phase change resistor of the phase change resistor. It was produced to have a write current of about 0.6 mA to change the GST film into a crystalline state. In addition, the reset resistor R _RESET of the phase change resistors was _measured using a bit line voltage of 0.2 volt after applying the reset pulse, and the set resistor R _SET of the phase change resistors was set pulse. Measurements were made using a 0.2V line voltage after applying.

As can be seen from Figs. 21 and 22, both of the conventional technology and the phase change memory cells according to the present invention have a uniform set resistance R _SET of about 1000 (ohms / cell) regardless of the number of the program cycles. Seemed. However, the conventional phase change memory cells exhibited a low reset resistance (R _RESET ) of about 6,000 (ohms / cell) to about 100,000 (ohms / cell) despite about 5,000 cycles of program operations. In contrast, phase change memory cells according to the present invention exhibited a high reset resistance (R _RESET ) of about 300,000 (ohms / cell) to about 3,000,000 (ohms / cell) after about 10 cycles of program operations. This can be understood that the interface characteristics of the phase change material film patterns of the phase change memory cells according to the present invention are superior to those of the phase change material film patterns of the conventional phase change memory cells. That is, the phase transition of the phase change material film patterns of the phase change memory cells according to the present invention is the phase change of the phase change material film patterns of the conventional phase change memory cells. It can be understood that the transition occurred efficiently compared to the phase transition (phase transition from the crystalline state to the amorphous state). As a result, according to the present invention, the read margin of the phase change memory cells can be significantly improved.

As described above, according to the present invention, by forming an oxygen barrier layer covering the phase change resistors, the contact resistance of the lower electrodes and the set / reset resistance characteristics of the phase change resistors can be significantly improved. In addition, by adopting MOS transistors having multiple channel regions as cell switching elements, the integration degree of the semiconductor memory device as well as the program characteristics can be improved.

Claims (66)

Integrated circuit boards; A switching element formed on the integrated circuit substrate and having multiple channel regions adjacent to each other; And And a data storage element electrically connected to the switching element. The method of claim 1, wherein the switching device Channel regions formed in at least two channel pins protruding from the integrated circuit substrate and spaced apart from each other; First and second impurity regions formed in the substrate and spaced apart from each other by the channel fins; And And an insulated gate electrode covering the channel fins between the first and second impurity regions, wherein the data storage element is electrically connected to any one of the first and second impurity regions. Semiconductor memory cell. 3. The semiconductor memory cell of claim 2, wherein said data storage element is a programmable resistor. 4. The programmable resistor of claim 3, wherein the programmable resistor includes a first electrode electrically connected to one of the first and second impurity regions, a programmable material film on the first electrode, and a second electrode on the programmable material film. A semiconductor memory cell, characterized in that. The semiconductor memory cell of claim 4, wherein the programmable material film is a phase change material film. 6. The semiconductor memory cell of claim 5, wherein the phase change material film is a chalcogenide film. Integrated circuit boards; A pin body protruding from the integrated circuit board; First and second impurity regions formed in the fin body and spaced apart from each other; An insulated gate electrode covering the fin body between the first and second impurity regions; And And a programmable resistor electrically connected to either one of said first and second impurity regions. 8. The programmable memory cell of claim 7, wherein the fin body comprises at least one channel fin protruding from the substrate, wherein the gate electrode is disposed to cross and cover the channel fin. 8. The programmable memory cell of claim 7, wherein the programmable resistor is a phase change resistor. An integrated circuit substrate having a cell array region and a peripheral circuit region; A cell switching element formed on the integrated circuit substrate in the cell array region and having multi channel regions; A programmable resistor electrically connected to the cell switching element; And And a peripheral circuit MOS transistor formed on the integrated circuit board in the peripheral circuit region. The method of claim 10, wherein the cell switching device A pin body protruding from the integrated circuit substrate in the cell array region; First and second cell impurity regions formed in the fin body and spaced apart from each other; And And an insulated cell gate electrode covering the fin body between the first and second cell impurity regions, wherein the programmable resistor is electrically connected to any one of the first and second cell impurity regions. Programmable memory device. The programmable memory device of claim 11, wherein the fin body includes at least two channel fins protruding from the substrate, wherein the cell gate electrode is disposed to cross the channel fins. The programmable memory device of claim 10, wherein the programmable resistor is a phase change resistor. The programmable memory device of claim 10, wherein the peripheral circuit MOS transistor has a planar-type single channel region. The method of claim 11, wherein the peripheral circuit MOS transistor A peripheral active region defined in the integrated circuit substrate in the peripheral circuit region; First and second peripheral impurity regions formed at both ends of the peripheral active region; And And a peripheral gate electrode crossing the upper portion of the peripheral active region between the first and second peripheral impurity regions. The method of claim 15, A cell gate insulating layer interposed between the cell gate electrode and the fin body; And And a peripheral gate insulating layer interposed between the peripheral gate electrode and the peripheral active region. The programmable memory device of claim 16, wherein a thickness of the peripheral gate insulating layer is the same as or different from a thickness of the cell gate insulating layer. The programmable memory device of claim 16, wherein the width of the peripheral gate electrode is the same as or different from the width of the cell gate electrode. The programmable memory device of claim 10, wherein the programmable resistor includes a first material layer and a programmable material layer interposed between the electrodes. 20. The programmable memory device of claim 19, further comprising a bit line electrically connected to one of the first and second electrodes. An integrated circuit substrate having a cell array region and a peripheral circuit region; A first fin body having a first group of channel pins protruding from the integrated circuit board in the cell array region and first and second connections respectively connecting both ends of the first group of channel pins; A first cell gate electrode covering upper surfaces and sidewalls of the first group of channel fins; A cell source region formed in the first connection portion; A cell drain region formed in the second connection portion; A lower electrode electrically connected to the cell drain region; A molding film surrounding the lower electrode and having a surface step to have a protrusion; A phase change material film pattern disposed in or on the molding film; And And a top electrode pattern disposed on the phase change material layer pattern. The method of claim 21, And the channel pins of the first group include at least two channel pins. The method of claim 21, And the phase change material film pattern is a GST (GeSbTe) alloy film doped with at least one of nitrogen and silicon. The method of claim 21, The upper electrode pattern includes a top electrode, a glue film pattern, and a hard mask pattern stacked in sequence. The method of claim 21, The molding film is a phase change memory device, characterized in that the insulating film having a higher thermal conductivity (thermal conductivity) than the silicon oxide film. 27. The phase change memory device as claimed in claim 25, wherein the molding film is a silicon oxynitride film (SiON) or a silicon nitride film. 22. The phase change memory device as claimed in claim 21, wherein the molding film serves as an oxygen barrier film. 28. The phase change memory device as claimed in claim 27, wherein the molding film is a silicon oxynitride film (SiON) or a silicon nitride film. The method of claim 21, And a contact spacer surrounding the sidewalls of the lower electrode. The method of claim 21, The protrusion of the molding layer is self-aligned with the phase change material layer pattern. The method of claim 21, And the lower electrode penetrates through the protrusion of the molding layer. The method of claim 21, And an oxygen barrier layer covering the sidewall of the protrusion and the sidewall of the phase change material layer pattern when the phase change material layer pattern is disposed on the molding layer. The method of claim 21, And the oxygen barrier layer covering the sidewall of the protrusion, the sidewall of the phase change material layer pattern, and the upper electrode pattern when the phase change material layer pattern is disposed on the molding layer. . The method of claim 21, And an oxygen barrier layer covering the sidewalls of the protrusion and the upper electrode pattern when the phase change material layer pattern is disposed in the molding layer. The method of claim 32, An interlayer insulating film covering the oxygen barrier film; And And a bit line disposed on the interlayer insulating film and electrically connected to the upper electrode pattern. The method of claim 33, wherein An interlayer insulating film covering the oxygen barrier film; And And a bit line disposed on the interlayer insulating film and electrically connected to the upper electrode pattern. The method of claim 34, wherein An interlayer insulating film covering the oxygen barrier film; And And a bit line disposed on the interlayer insulating film and electrically connected to the upper electrode pattern. The method of claim 21, A peripheral active region defined in a predetermined region of the integrated circuit board in the peripheral circuit region; And And a peripheral circuit MOS transistor formed in the peripheral active region. The method of claim 38, wherein the peripheral circuit MOS transistor Peripheral source regions and peripheral drain regions formed at both ends of the peripheral active region, respectively; And And a peripheral gate electrode crossing the upper portion of the peripheral channel region between the peripheral source / drain regions, wherein the peripheral channel region is a flat single channel region. The method of claim 39, And the width of the peripheral gate electrode is greater than the width of the first cell gate electrode. The method of claim 39, A cell gate insulating layer interposed between the first cell gate electrode and the channel fins; And And a peripheral gate insulating layer interposed between the peripheral gate electrode and the peripheral channel region. 42. The method of claim 41 wherein And the thickness of the peripheral gate insulating film is greater than the thickness of the cell gate insulating film. 40. The peripheral metal silicide layer of claim 39, wherein a self-aligned peripheral metal silicide layer is formed on at least the peripheral source / drain regions of the first cell gate electrode, the cell source / drain regions, the peripheral gate electrode, and the peripheral source / drain regions. Phase change memory device characterized in that it further comprises. At least one programmable memory device used as a data storage medium, a processor connected to the programmable memory device to process code and data, and an input / output device for performing data communication with the processor through bus architectures In the electronic product comprising a, the programmable memory device is Integrated circuit boards; A pin body protruding from the substrate; A cell source region and a cell drain region formed in the fin body and spaced apart from each other; A cell gate electrode covering upper surfaces and sidewalls of the fin body between the cell source region and the cell drain region; And An electronic product comprising a programmable resistor electrically connected to the cell drain region. The method of claim 44, The programmable resistor is an electronic product, characterized in that the phase change resistor. The method of claim 45, The phase change resistor may include a lower electrode electrically connected to the cell drain region, a phase change material film pattern stacked on the lower electrode, and an upper electrode stacked on the phase change material film pattern. product. The method of claim 44, And an oxygen barrier film covering the substrate having the programmable resistor. Forming a pin body protruding from the integrated circuit board, Forming a cell gate electrode across the top of the fin body and covering the top surface and sidewalls of the fin body, Forming a cell source region and a cell drain region in the fin body adjacent to both sidewalls of the cell gate electrode, Forming an interlayer insulating film on the substrate having the cell gate electrode and the cell source / drain regions, Forming a programmable resistor on said interlayer insulating film, wherein said programmable resistor is electrically connected to said cell drain region. 49. The method of claim 48 wherein And the pin body is formed to have a plurality of channel fins, and wherein the cell gate electrode is formed to cover upper surfaces and sidewalls of the plurality of channel fins. 49. The method of claim 48 wherein The programmable resistor is a method of manufacturing a programmable memory cell, characterized in that the phase change resistor. 51. The method of claim 50, wherein forming the phase change resistor Forming a molding film on the interlayer insulating film, Forming a lower electrode penetrating the molding layer, the lower electrode being electrically connected to the cell drain region; A phase change material film and an upper electrode film are sequentially formed on the substrate having the lower electrode, Patterning the upper electrode layer and the phase change material layer to form a phase change material layer pattern and an upper electrode sequentially stacked on the lower electrode, wherein the phase change material layer pattern and the upper electrode are phase change resistor patterns And wherein the molding film has a protrusion which is etched during the formation of the phase change resistor pattern to protrude relatively to the lower portion of the phase change resistor pattern. Preparing an integrated circuit substrate having a cell array region and a peripheral circuit region; A preliminary cell device isolation layer and a peripheral device isolation layer are formed on the integrated circuit board in the cell array region and the integrated circuit board in the peripheral circuit region, respectively, wherein the preliminary cell device isolation layer and the peripheral device isolation layer are respectively active cell and peripheral To define the active area, The preliminary cell device isolation layer is partially etched to form a recessed cell device isolation layer and simultaneously protrudes the cell active region, and the protruding cell active region serves as a fin body. Forming a peripheral gate electrode across the top of the peripheral active region together with a pair of cell gate electrodes covering the top and sidewalls of the fin body and across the top of the fin body, Impurity ions are implanted into the fin body using the cell gate electrodes as an ion implantation mask to form a common source region in the fin body between the cell gate electrodes and at the same time, a cell drain region at both ends of the fin body. Form the fields, Implanting impurity ions into the peripheral active region using the peripheral gate electrode as an ion implantation mask to form a peripheral source region and a peripheral drain region, Forming a molding film on the substrate having the cell drain regions, the common source region and the peripheral source / drain regions, Forming lower electrodes penetrating the molding layer, the lower electrodes being electrically connected to the cell drain regions; A phase change material film and an upper electrode film are sequentially formed on the substrate having the lower electrodes, The upper electrode layer and the phase change material layer are patterned to form a phase change material layer pattern and an upper electrode sequentially stacked on the lower electrodes, respectively, wherein the phase change material layer pattern and the upper electrode form a phase change resistor pattern. And wherein the molding film has protrusions which are etched during the formation of the phase change resistor patterns and protrude relatively to the bottom of the phase change resistor patterns, And forming an oxygen barrier layer on the substrate having the phase change resistor patterns and the protrusions. The method of claim 52, wherein Forming an interlayer insulating film on the substrate having the cell drain regions, the common source region and the peripheral source / drain regions before forming the molding film, Forming cell drain pads electrically connected to the cell drain regions in the interlayer insulating layer, wherein the lower electrodes are formed to contact the cell drain pads. . The method of claim 52, wherein And forming a self-aligned peripheral metal silicide film on at least the peripheral source / drain regions of the peripheral gate electrode and the peripheral source / drain regions. The method of claim 52, wherein On at least the peripheral source / drain regions, the common source region and the cell drain regions of the cell gate electrodes, the peripheral gate electrode, the peripheral source / drain regions, the common source region and the cell drain regions. And forming a self-aligned metal silicide film on the phase change memory device. The method of claim 53 wherein And forming contact spacers surrounding sidewalls of the lower electrodes. The method of claim 56, wherein Forming the contact spacers Patterning the molding layer to form phase change resistor contact holes exposing the cell drain pads, Forming a lower contact spacer film and an upper contact spacer film sequentially and conformally on the substrate having the phase change resistor contact holes, Continuously anisotropically etching the upper contact spacer layer and the lower contact spacer layer to form outer contact spacers covering sidewalls of the phase change resistor contact holes and inner contact spacers covering an inner wall of the outer contact spacers. A method of manufacturing a phase change memory device characterized in that. The method of claim 57, The lower contact spacer layer is formed of a silicon oxynitride layer using a plasma CVD technique performed at a temperature lower than 500 ° C., and the upper contact spacer layer is formed using a low pressure CVD technique performed at a temperature higher than 600 ° C. A method of manufacturing a phase change memory device, characterized in that it is formed of a silicon nitride film. The method of claim 52, wherein And the phase change material layer is formed of a GST (GeSbTe) alloy layer doped with at least one of nitrogen and silicon. The method of claim 52, wherein And forming a glue layer and a hard mask layer sequentially on the upper electrode layer, wherein the phase change resistor pattern is configured to pattern the hard mask layer, the glue layer, the upper electrode layer, and the phase change material layer. A method of manufacturing a phase change memory device, characterized in that formed by. The method of claim 60, And said hard film is formed of a silicon nitride film and said hard mask film is formed of a silicon oxide film. The method of claim 52, wherein The oxygen barrier film is formed using an in-situ process after the etching process for forming the phase change resistor patterns and the protrusions. The method of claim 52, wherein The oxygen barrier film is a method of manufacturing a phase change memory device, characterized in that formed by a single oxygen barrier film or a double oxygen barrier film. The method of claim 63, wherein The single oxygen barrier film may be formed of a silicon oxynitride film or a silicon nitride film using a plasma CVD technique performed at a temperature lower than 350 ° C. or an atomic layer deposition technique performed at a temperature lower than 350 ° C. Manufacturing method. 66. The method of claim 63, wherein forming the double oxygen barrier film A lower oxygen barrier layer is formed on the substrate having the phase change resistor patterns using a plasma CVD technique or an atomic layer deposition technique, which is performed at a temperature lower than 350 ° C., and the lower oxygen barrier layer is formed of a silicon oxynitride layer or a silicon nitride layer. , Forming an upper oxygen barrier film on the lower oxygen barrier film using a plasma CVD technique or a low pressure CVD technique performed at a temperature higher than 350 ° C., wherein the upper oxygen barrier film is formed of a silicon oxynitride film or a silicon nitride film. A method of manufacturing a phase change memory device characterized in that. The method of claim 52, wherein Forming an interlayer insulating film on the oxygen barrier film, And forming a bit line electrically connected to the phase change resistor patterns on the interlayer insulating film.

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