[go: up one dir, main page]

KR20060001489A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
KR20060001489A
KR20060001489A KR1020040050620A KR20040050620A KR20060001489A KR 20060001489 A KR20060001489 A KR 20060001489A KR 1020040050620 A KR1020040050620 A KR 1020040050620A KR 20040050620 A KR20040050620 A KR 20040050620A KR 20060001489 A KR20060001489 A KR 20060001489A
Authority
KR
South Korea
Prior art keywords
active region
active
protrusion
bit line
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020040050620A
Other languages
Korean (ko)
Inventor
김동석
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020040050620A priority Critical patent/KR20060001489A/en
Publication of KR20060001489A publication Critical patent/KR20060001489A/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0128—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명의 목적은 DRAM 셀에서 셀면적을 감소시키면서 충분한 공정마진을 확보하여 수율 및 신뢰성을 향상시키는 것이다.It is an object of the present invention to secure sufficient process margins while reducing cell area in DRAM cells to improve yield and reliability.

본 발명의 목적은 반도체 기판; 기판에 제 1 방향으로 정의된 일자형의 액티브 영역; 액티브 영역 위에 제 1 방향에 수직인 제 2 방향으로 형성된 다수개의 워드라인들; 워드라인 위에 액티브 영역 사이를 가로지르면서 제 1 방향으로 형성되고 일부가 제 2 방향으로 연장되어 액티브 영역과 오버랩하는 돌출부를 구비한 다수개의 비트라인들; 및 돌출부와 액티브 영역 사이에 형성된 비트라인콘택층을 포함하는 반도체 소자에 의해 달성될 수 있다. 여기서, 액티브 영역은 1F의 간격으로 서로 이격되어 배치되며, F가 최소선폭을 나타내고, 하나의 액티브 영역 위에는 각각 2개의 워드라인들이 상기 액티브 영역을 가로지르면서 형성된다.
An object of the present invention is a semiconductor substrate; A linear active region defined in a first direction on the substrate; A plurality of word lines formed in a second direction perpendicular to the first direction on the active area; A plurality of bit lines formed in a first direction on the word line and extending in a first direction and partially extending in a second direction, the bit lines having a protrusion overlapping the active area; And a bit line contact layer formed between the protrusion and the active region. Here, the active regions are spaced apart from each other at intervals of 1F, F represents a minimum line width, and two word lines are formed on one active region while crossing the active region.

액티브 영역, 워드라인, 비트라인, 돌출부, 일자형, 비트라인콘택층Active area, word line, bit line, protrusion, straight, bit line contact layer

Description

반도체 소자{SEMICONDUCTOR DEVICE} Semiconductor device {SEMICONDUCTOR DEVICE}             

도 1은 종래 DRAM 셀의 레이아웃 구조를 나타낸 도면.1 is a view showing a layout structure of a conventional DRAM cell.

도 2는 본 발명의 실시예에 따른 DRAM 셀의 레이아웃 구조를 나타낸 도면.2 illustrates a layout structure of a DRAM cell according to an embodiment of the present invention.

도 3은 본 발명의 실시예에 따른 DRAM 셀의 단면도로서, 도 2의 Ⅲ-Ⅲ' 선에 따른 단면도.3 is a cross-sectional view of a DRAM cell according to an embodiment of the present invention, taken along line III-III 'of FIG.

※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing

20 : 반도체 기판 21 : 필드 산화막20: semiconductor substrate 21: field oxide film

22 : 액티브 영역 23 : 워드라인22: active area 23: word line

24, 26 : 절연막 25a, 25b : 랜딩 플러그24, 26: insulating film 25a, 25b: landing plug

27 : 비트라인 콘택층 28 : 비트라인27: bit line contact layer 28: bit line

28a : 돌출부
28a: protrusion

본 발명은 반도체 소자에 관한 것으로, 특히 셀 면적을 감소시킬 수 있는 DRAM 셀의 레이아웃 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a layout structure of a DRAM cell capable of reducing cell area.

디램(Dynamic Random Access Memory; DRAM)과 같은 메모리 소자의 대용량화에 따라 칩(Chip) 크기가 점점 증가하면서 웨이퍼(wafer) 당 칩의 수가 점점 감소하고 있다.As the size of chips increases with the increase in the capacity of memory devices such as DRAM (Dynamic Random Access Memory (DRAM)), the number of chips per wafer is gradually decreasing.

이에 따라, 셀의 레이아웃 변화를 통해 셀 면적을 감소시켜 칩 크기를 감소시키는 방법에 대한 연구가 활발히 진행되고 있다.Accordingly, research on a method of reducing the chip size by reducing the cell area through the layout change of the cell is being actively conducted.

도 1은 종래 DRAM 셀의 8F2 레이아웃 구조를 나타낸 도면으로서, 도 1에 나타낸 바와 같이, 반도체 기판(미도시)에 필드산화막(11)에 의해 제 1 방향으로 3F(여기서, F는 최소선폭을 나타낸다)의 간격으로 서로 이격되어 액티브 영역(12)이 정의되고, 액티브 영역(12) 위에는 다수개의 워드라인(13)들이 게이트 절연막(미도시)의 개재하에 제 1 방향에 수직인 제 2 방향으로 1F의 간격으로 서로 이격되어 형성된다. 이때, 하나의 액티브 영역(12) 위에는 각각 2개의 워드라인(13)들이 액티브 영역(12)을 가로지르면서 형성된다. 워드라인(13) 위에는 절연막(미도시)의 개재하에 제 1 방향으로 1F의 간격으로 서로 이격되어 액티브 영역(12) 사이를 가로지르면서 비트라인(18)들이 형성된다. 또한, 워드라인(13)들 사이의 액티브 영역(12)에는 스토리리지노드용 제 1 랜딩플러그(15a)와 비트라인용 제 2 랜딩플러그(미도시)가 절연막(미도시)에 의해 서로 분리되어 각각 형성되고, 비트라인(18)과 제 2 랜딩플러그는 이들 사이에서 콘택패드를 통해 비트라인(18)과 오버랩되어 콘택(17)된다. FIG. 1 is a view illustrating an 8F 2 layout structure of a conventional DRAM cell. As shown in FIG. 1, 3F (where F denotes a minimum line width in a first direction by a field oxide film 11 on a semiconductor substrate (not shown). The active regions 12 are defined to be spaced apart from each other at intervals, and a plurality of word lines 13 are disposed on the active regions 12 in a second direction perpendicular to the first direction through intervening a gate insulating film (not shown). It is formed spaced apart from each other at intervals of 1F. In this case, two word lines 13 are formed on one active region 12 while crossing the active region 12. The bit lines 18 are formed on the word line 13 while intersecting the active regions 12 at intervals of 1F in the first direction with an insulating film (not shown) interposed therebetween. In addition, the first landing plug 15a for the storage node and the second landing plug for the bit line (not shown) are separated from each other by an insulating film (not shown) in the active region 12 between the word lines 13. Each is formed, and the bit line 18 and the second landing plug are in contact with and overlap the bit line 18 via a contact pad therebetween.

그런데, 8F2 레이아웃 구조의 DRAM 셀에서는 액티브 영역(12)들이 3F의 간격으로 이격되어 형성됨에 따라 오버레이 마진(overlay margin) 확보가 용이하지만, 셀 면적이 커진다는 단점이 있다.By the way, in the DRAM cell of the 8F 2 layout structure, as the active regions 12 are formed spaced at intervals of 3F, it is easy to secure an overlay margin, but there is a disadvantage that the cell area becomes large.

따라서, 셀면적을 감소시키기 위해서는 디자인룰(design rule)을 감소시켜 패턴들 사이의 간격을 점점 더 좁혀야 하나, 마스크 공정의 한계와 공정기술의 복잡화 및 수율 저하 등의 문제로 인하여 적용하는데 어려움이 있다.
Therefore, in order to reduce the cell area, it is necessary to narrow the gap between patterns by reducing the design rule, but it is difficult to apply due to problems such as the limitation of the mask process, the complexity of the process technology, and the yield reduction. have.

본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, DRAM 셀에서 셀면적을 감소시키면서 충분한 공정마진을 확보하여 수율 및 신뢰성을 향상시키는데 그 목적이 있다.
The present invention has been proposed to solve the above problems of the prior art, and has an object of improving the yield and reliability by securing a sufficient process margin while reducing the cell area in the DRAM cell.

상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 반도체 기판; 기판에 제 1 방향으로 정의된 일자형의 액티브 영역; 액티브 영역 위에 제 1 방향에 수직인 제 2 방향으로 형성된 다수개의 워드라인들; 워드라인 위에 액티브 영역 사이를 가로지르면서 제 1 방향으로 형성되고 일부가 제 2 방향으로 연장되어 액티브 영역과 오버랩하는 돌출부를 구비한 다수개의 비트라인들; 및 돌출부와 액티브 영역 사이에 형성된 비트라인콘택층을 포함하는 반도체 소자에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, the object of the present invention is a semiconductor substrate; A linear active region defined in a first direction on the substrate; A plurality of word lines formed in a second direction perpendicular to the first direction on the active area; A plurality of bit lines formed in a first direction on the word line and extending in a first direction and partially extending in a second direction, the bit lines having a protrusion overlapping the active area; And a bit line contact layer formed between the protrusion and the active region.

여기서, 액티브 영역은 1F의 간격으로 서로 이격되어 배치되며, F는 최소선폭이며, 하나의 액티브 영역 위에는 각각 2개의 워드라인들이 상기 액티브 영역을 가로지르면서 형성된다.The active regions are spaced apart from each other at intervals of 1 F, F is a minimum line width, and two word lines are formed on one active region while crossing the active region.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

도 2 및 도 3을 참조하여 본 발명의 실시예에 따른 DRAM 셀의 레이아웃 구조를 설명한다.A layout structure of a DRAM cell according to an embodiment of the present invention will be described with reference to FIGS. 2 and 3.

도 2 및 도 3을 참조하면, 반도체 기판(20)에 필드 산화막(21)에 의해 제 1 방향으로 1F의 간격으로 서로 이격되어 일자형의 액티브 영역(22)이 정의되고, 액티브 영역(22) 위에는 다수개의 워드라인(23)들이 게이트 절연막(미도시)의 개재하에 제 1 방향에 수직인 제 2 방향으로 1F의 간격으로 서로 이격되어 형성된다. 이때, 하나의 액티브 영역(22) 위에는 각각 2개의 워드라인(23)들이 액티브 영역(22)을 가로지르면서 형성된다. 2 and 3, the field oxide film 21 is spaced apart from each other by 1F in the first direction on the semiconductor substrate 20 to define a linear active region 22. The active region 22 is defined above. The plurality of word lines 23 are formed to be spaced apart from each other at intervals of 1F in a second direction perpendicular to the first direction through the gate insulating layer (not shown). In this case, two word lines 23 are formed on one active region 22 while crossing the active region 22.

워드라인(23) 위에는 절연막(미도시)의 개재하에 제 1 방향으로 1F의 간격으로 서로 이격되어 액티브 영역(22) 사이를 가로지르면서 일부가 제 2 방향으로 연장되어 액티브 영역(22)과 오버랩하는 돌출부(28a)를 구비한 비트라인(28)들이 형성된다. 워드라인(23)들 사이의 액티브 영역(22)에는 스토리리지노드용 제 1 랜딩플러그(25a)와 비트라인용 제 2 랜딩플러그(25b)가 절연막(24)에 의해 서로 분리되 어 각각 형성되고, 비트라인(28)은 돌출부(28a)와 제 2 랜딩플러그(25b) 사이에 형성된 비트라인콘택층(27)에 제 2 랜딩플러그(25b)와 전기적으로 연결된다.The word line 23 is spaced apart from each other at intervals of 1F in the first direction with an insulating film (not shown) intersecting between the active regions 22 and partially extending in the second direction to overlap the active region 22. Bit lines 28 having protrusions 28a are formed. In the active region 22 between the word lines 23, the first landing plug 25a for the storage node and the second landing plug 25b for the bit line are separated from each other by the insulating layer 24, respectively. The bit line 28 is electrically connected to the second landing plug 25b to the bit line contact layer 27 formed between the protrusion 28a and the second landing plug 25b.

상기 실시예에 의하면, 액티브 영역이 1F 간격으로 형성되어 2개의 셀이 차지하는 면적이 6F×2F로 하나의 셀이 6F2 크기를 가지므로 종래 8F2 레이아웃 구조에 비해 셀면적을 약 25% 정도 감소시킬 수 있어 고집적화 구현이 용이해진다. According to the above embodiment, since the active areas are formed at intervals of 1F and the area occupied by two cells is 6F × 2F, and one cell has a size of 6F 2 , the cell area is reduced by about 25% compared to the conventional 8F 2 layout structure. This makes it easy to implement high integration.

또한, 액티브 영역이 일자형을 가짐에 따라 공정마진 확보가 용이하여 수율 및 신뢰성 확보도 용이해진다.In addition, as the active region has a straight shape, it is easy to secure process margins, thereby securing yield and reliability.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.
The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

전술한 본 발명은 DRAM 셀에서 셀면적을 감소시킬 수 있을 뿐만 아니라 충분한 공정마진을 확보할 수 있으므로 수율 및 신뢰성을 향상시킬 수 있다.As described above, the present invention can not only reduce the cell area of a DRAM cell but also ensure sufficient process margin, thereby improving yield and reliability.

Claims (3)

반도체 기판;Semiconductor substrates; 상기 기판에 제 1 방향으로 정의된 일자형의 액티브 영역;A linear active region defined in a first direction on the substrate; 상기 액티브 영역 위에 상기 제 1 방향에 수직인 제 2 방향으로 형성된 다수개의 워드라인들; A plurality of word lines formed in a second direction perpendicular to the first direction on the active area; 상기 워드라인 위에 상기 액티브 영역 사이를 가로지르면서 상기 제 1 방향으로 형성되고 일부가 상기 제 2 방향으로 연장되어 상기 액티브 영역과 오버랩하는 돌출부를 구비한 다수개의 비트라인들; 및 A plurality of bit lines formed on the word line and intersecting between the active regions and having protrusions partially extending in the second direction and overlapping the active region; And 상기 돌출부와 상기 액티브 영역 사이에 형성된 비트라인콘택층을 포함하는 반도체 소자.And a bit line contact layer formed between the protrusion and the active region. 제 1 항에 있어서, The method of claim 1, 상기 액티브 영역은 1F의 간격으로 서로 이격되어 배치되며, 여기서 F는 최소선폭인 것을 특징으로 하는 반도체 소자.The active regions are spaced apart from each other at intervals of 1F, where F is a minimum line width. 제 1 항에 있어서, The method of claim 1, 하나의 액티브 영역 위에는 각각 2개의 워드라인들이 상기 액티브 영역을 가 로지르면서 형성되는 것을 특징으로 하는 반도체 소자.Two word lines are formed on one active region while crossing the active region.
KR1020040050620A 2004-06-30 2004-06-30 Semiconductor device Withdrawn KR20060001489A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020040050620A KR20060001489A (en) 2004-06-30 2004-06-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020040050620A KR20060001489A (en) 2004-06-30 2004-06-30 Semiconductor device

Publications (1)

Publication Number Publication Date
KR20060001489A true KR20060001489A (en) 2006-01-06

Family

ID=37104624

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020040050620A Withdrawn KR20060001489A (en) 2004-06-30 2004-06-30 Semiconductor device

Country Status (1)

Country Link
KR (1) KR20060001489A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100900136B1 (en) * 2007-10-17 2009-06-01 주식회사 하이닉스반도체 1-transistor DRAM
US7778071B2 (en) 2007-12-21 2010-08-17 Hynix Semiconductor Inc. Phase change memory device having decentralized driving units

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100900136B1 (en) * 2007-10-17 2009-06-01 주식회사 하이닉스반도체 1-transistor DRAM
US7778071B2 (en) 2007-12-21 2010-08-17 Hynix Semiconductor Inc. Phase change memory device having decentralized driving units
US7957180B2 (en) 2007-12-21 2011-06-07 Hynix Semiconductor Inc. Phase change memory device having decentralized driving units

Similar Documents

Publication Publication Date Title
JP3575988B2 (en) Semiconductor storage device
US8878285B2 (en) Vertical semiconductor device, module and system each including the same, and method for manufacturing the vertical semiconductor device
KR100683295B1 (en) Layout and Wiring Design of Memory Cells with Vertical Transistors
TWI453868B (en) Memory array, semiconductor structure and electronic system, and method of forming memory array, semiconductor structure and electronic system
US8637990B2 (en) Semiconductor device and method for fabricating the same
US20230267263A1 (en) Space Optimization Between SRAM Cells and Standard Cells
JP2638487B2 (en) Semiconductor storage device
US6953959B2 (en) Integrated circuit devices including self-aligned contacts with increased alignment margin
US8507994B2 (en) Semiconductor device
KR20060001489A (en) Semiconductor device
US8072077B2 (en) Semiconductor memory device
KR20090044481A (en) Semiconductor devices
KR100395910B1 (en) Semiconductor DRAM cell
KR20010073289A (en) A dram device
JP3252817B2 (en) Semiconductor storage device
KR20100038975A (en) Capacitor-less dram device
KR101168391B1 (en) Semiconductor device
CN100438041C (en) Memory cell of dynamic random access memory and array structure thereof
US7138676B2 (en) Semiconductor device and manufacturing the same having multiple trenches formed in plural element regions or trench groups
KR20000003883A (en) Semiconductor memory device
KR100811415B1 (en) Manufacturing Method of Semiconductor Device
JP2002328458A (en) Semiconductor memory device
KR20060036650A (en) Semiconductor dram element
JP2876665B2 (en) Semiconductor memory
US20090101981A1 (en) One-transistor type dram

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20040630

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid