KR20050112838A - Display apparatus and driving method thereof - Google Patents

Abstract

In an organic EL display device, a first pixel and a second pixel share one data line, a selection scan line, and a driving element, and one frame is divided into a first field and a second field to be driven. The organic EL element of the first pixel is connected to the driving element through the first transistor, and the organic EL element of the second pixel is connected to the driving element through the second transistor. The first and second transistors are respectively driven by the first emission scan line and the second emission scan line, and the selection scan line has a low level pulse in the first field and the second field, respectively. The first light emitting scan line has a low level pulse in a first field, and the second light emitting scan line has a low level pulse in a second field. In this way, the number of data lines and the number of integrated circuits for driving data can be reduced. For this driving, a selection scan driver for driving a selection scan line and a light emission scan driver for driving a first light emission scan line and a second light emission scan line are used.

Description

Display device and driving method thereof {DISPLAY APPARATUS AND DRIVING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a driving method thereof, and more particularly to a scan driver of a display device.

A plurality of selective scan lines extending in a row direction and a plurality of data lines extending in a column direction are formed in a display area of an active driving display device such as a liquid crystal display and an organic electroluminescent display. A pixel region is defined by two neighboring selection scan lines and two neighboring data lines, and pixels are formed in a matrix form in the pixel region. In one pixel, an active element, that is, a transistor, which transfers a data signal from the data line is formed in response to the selection signal transmitted from the selection scan line. Accordingly, such a display device requires a scan driver for driving the selection scan line and a data driver for driving the data line.

In such a display device, an R pixel emitting red light (hereinafter, referred to as "R"), a G pixel emitting green light (hereinafter, referred to as "G"), and a blue color (hereinafter, referred to as "B") are described. Various colors are expressed by the combination of the brightness of the B pixels emitting light. Therefore, in the display device, in general, R, G, and B pixels are continuously arranged in a row direction, and separate data lines are connected to each of the R, G, and B pixels.

Since the data driver converts a digital data signal into an analog signal and applies it to all data lines, the data driver must have an output terminal corresponding to the number of data lines. However, in general, the data driver is made of a plurality of integrated circuits. Since the number of output terminals of one integrated circuit is limited, many integrated circuits must be used to drive all the data lines. In addition, when the data lines are formed for each of the R, G, and B pixels in the limited display area, and the driving elements for driving the pixels are also formed, the aperture ratio of the pixels is reduced.

An object of the present invention is to provide a display device capable of reducing the number of integrated circuits driving data lines. Another object of the present invention is to provide a display device capable of reducing the number of data lines.

In order to solve this problem, the present invention allows two pixels to share one data line and a selection scan line.

According to an aspect of the present invention, a display device including a display area, a first driver, and a second driver is provided. The display area includes a plurality of data lines for transmitting a data signal representing an image, a plurality of first scan lines for transmitting a selection signal, a plurality of second and third scan lines for transmitting a light emission signal, and the data lines and the first scan lines. It includes a plurality of pixel areas each defined. The first driver sequentially transfers the first signal having the first pulse in the first field and the second field by the first period, respectively, to the plurality of first scan lines. The second driver sequentially transmits the second signal having the second pulse in the first field to the plurality of second scan lines while shifting the second signal by the second period, and the third signal having the second pulse in the second field. Is sequentially transmitted to the plurality of third scan lines while shifting by the second period. The pixel area includes first and second pixels that share the data line and the first scan line, wherein the first pixel emits light by the second pulse of the second signal in the first field, and the second pixel. In the field, the second pixel emits light by the second pulse of the third signal.

According to an embodiment of the present invention, the first driver, the third driver for sequentially outputting the fourth signal having a third pulse by the first period, and the fourth signal and the fourth signal is the And a fourth driver configured to output a pulse corresponding to the first pulse of the first signal in a period in which the signal shifted by the first period is the third pulse.

According to another embodiment of the present invention, the third driver includes a plurality of first flip flops in which an output of the first flip flop at the front end is an input of the first flip flop at the rear end. The first flip-flop at the rear end shifts the third pulse of the fourth signal output from the first flip-flop at the front end by the first period and outputs the third pulse to the fourth driver.

According to another embodiment of the present invention, the second period is the same as the first period.

According to another embodiment of the present invention, the second driver, the first pixel in the first field substantially the same time as the time when the first pulse of the first signal is applied to the first scan line of the first pixel. Applying a second pulse of the second signal to the second scan line of, and substantially simultaneously with the time point at which the first pulse of the first signal is applied to the first scan line of the second pixel in the second field; The second pulse of the third signal is applied to the third scan line of the second pixel.

According to another embodiment of the present invention, the second driver generates the third signal by inverting the second signal.

According to another embodiment of the present invention, the second driver includes a plurality of second flip flops in which the output of the second flip flop at the front end is the input of the second flip flop at the rear end. The second flip-flop at the rear stage shifts and outputs a pulse corresponding to the second pulse of the second signal output from the second flip-flop at the front end by the second period.

According to another embodiment of the present invention, the second driver is the first of the first pixel after the end of the first pulse of the first signal applied to the first scan line of the first pixel in the first field Applying a second pulse of the second signal to two scan lines, and after the end of the first pulse of the first signal applied to the first scan line of the second pixel in the second field; The second pulse of the third signal is applied to a third scan line.

According to another embodiment of the present invention, the second driver, the fifth driver for sequentially outputting the fifth signal having a fourth pulse by a fourth period, and the fifth signal and the fifth signal is the And a sixth driving unit configured to output a pulse corresponding to the second pulse of the second signal in a period in which the signal shifted by an integer multiple of the fourth period is the fourth pulse.

According to another embodiment of the present invention, the fifth signal has a fifth pulse at a level opposite to the fourth pulse for a period other than the fourth pulse. The second driver may be configured to generate a pulse corresponding to the second pulse of the third signal in a period in which the signal in which the fifth signal and the fifth signal are shifted by an integer multiple of the fourth period is the fifth pulse. It further includes a seventh drive unit for outputting.

According to another embodiment of the present invention, the second driving unit, the fourth pulse in which the sixth signal in which the fifth signal is inverted and the signal in which the sixth signal is shifted by an integer multiple of the fourth period are common to the fourth pulse. And a seventh driver configured to output a pulse corresponding to the second pulse of the third signal in a period having the fifth pulse having the same level as.

According to another aspect of the present invention, there is provided a display device including a plurality of first scan lines for transmitting a first signal, a plurality of second scan lines for transmitting a second signal, and a plurality of third scan lines for transmitting a third signal. do. The first signal has a first pulse for a first period in the first field and the second field respectively, the second signal has a second pulse for a second period in the first field, and the third signal is the first signal. Has the second pulse during the second period in two fields. In addition, the display device of the present invention includes a first driver that sequentially outputs the first signal to the plurality of first scan lines while shifting the first signal by a third period, and sequentially shifts the second signal by the third period. And a second driver configured to output the plurality of second scan lines and sequentially output the third signal to the plurality of third scan lines while shifting the third signal by the third period.

According to still another aspect of the present invention, there is provided a method of driving a display device including a pixel region formed by a first scan line, a second scan line, a third scan line, and a data line for transmitting a data signal representing an image. The driving method of the present invention may include outputting a first signal having a first pulse during a first period in each of the first field and the second field, wherein the first signal and the first signal are shorter than the first period. Outputting a second signal having a second pulse during a period in which the signal shifted by a second period is the first pulse in common, and outputting a third signal having a third pulse during a third period in the first field And outputting a fourth signal having the third pulse during the third period in the second field. In this case, in a pixel area in which a data signal from the data line is written when a pulse corresponding to the second pulse is applied to the first scan line, the first pixel is a third signal of the third signal to the second scan line. It emits light when a pulse corresponding to the pulse is applied, and the second pixel emits light when a pulse corresponding to the third pulse of the fourth signal is applied.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification. When a part is connected to another part, this includes not only a directly connected part but also a case where another part is connected in between.

A display device and a driving method thereof according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings. In the embodiment of the present invention, an organic electroluminescence (hereinafter referred to as "organic EL") display device using electroluminescence of an organic material will be described as an example.

1 is a schematic plan view of an organic EL display device according to a first embodiment of the present invention.

As shown in FIG. 1, the organic EL display device according to the first embodiment of the present invention includes an insulating substrate (not shown) for forming a display panel, and the insulating substrate is an area visible to the user of the display device. The display area 100 may be divided into a light emitting area and a peripheral area outside thereof, that is, a non-light emitting area. The selective scan driver 200, the light emission scan driver 300, and the data driver 400 are formed in the peripheral area.

The display area 100 includes a plurality of data lines D ₁ -D _n , a plurality of selected scan lines S ₁ -S _m , a plurality of emission scan lines E ₁₁ -E _1m , E ₂₁ -E _2m , and a plurality of It includes a pixel. The plurality of data lines D _{1 to} D _n extend in the column direction and transmit data signals representing an image to the pixels, and the plurality of selection scan lines S _{1 to} S _m and the emission scan lines E _{11 to} E _{1 m} and E _{21 to} E _2m ) extend in the horizontal direction and transmit the selection signal and the light emission signal to the pixels, respectively. The pixel region 110 is defined by two neighboring selection scan lines and two neighboring data lines, and two pixels 111 and 112 are formed in the pixel region 110. That is, the two pixels 111 and 112 of the pixel region 110 are commonly connected to one data line and one selection signal line.

In FIG. 1, two light emitting scan lines E _{11 to} E _{1 m} and E _{21 to} E _{2 m} are formed in each pixel, and a light emitting scan driver for driving these light emitting scan lines E _{11 to} E _{1 m} and E _{21 to} E _{2 m} ( It is assumed that 300 is formed. In addition, it is explained that one frame is driven by dividing into two fields, and the period of the two fields is the same.

The selection scan driver 200 sequentially applies a selection signal to the plurality of selection scan lines S _{1 to} S _m in each field. The light emission scan driver 300 sequentially applies light emission signals to the plurality of light emission scan lines E _{11 to} E _{1 m} in one field, and sequentially emits light signals to the light emission scan lines E _{21 to} E _{2 m} in another field. Is authorized. The data driver 400 applies data signals to the data lines D _{1 to} D _n , and the data lines D _{1 to} D _n pass through the pixel areas 110 arranged in the row direction, respectively. Two pixels 111 and 112 are connected at 110.

The selection and emission scan driver 200 and 300 and / or the data driver 400 may be directly mounted on the insulating substrate in the form of an integrated circuit. Alternatively, these driving units 200, 300 and / or 400 may be placed on the insulating substrate by scanning lines S _{1 to} S _m , E _{11 to} E _{1 m} , E _{21 to} E _{2 m} , data lines D _{1 to} D _n , and pixel circuits ( It may be formed of the same layers as the layer forming the transistor of 110. Alternatively, the driving units 200, 300 and / or 400 may be formed on a substrate separate from the insulating substrate, and the substrates may be electrically connected to the insulating substrate. Also, a tape carrier package (TCP) may be adhered to and electrically connected to the insulating substrate. It may be mounted in the form of a chip in a flexible printed circuit (FPC) or tape automatic bonding (TAB).

Hereinafter, a pixel according to a first exemplary embodiment of the present invention will be described in detail with reference to FIG. 2.

2 is a schematic circuit diagram of a pixel according to a first embodiment of the present invention. In FIG. 2, a pixel using electroluminescence of an organic material is illustrated as an example, and for convenience of description, the scan line S _i of the i th row and the data lines D _j and D _{j +} of the j th to (j + 2) th columns are illustrated. Three pixel regions, i.e., six pixels, respectively formed in ₁ , D _{j + 2 are} shown as representative (where i is an integer between 1 and m and j is an integer between 1 and (n-2)). In FIG. 2, the pixels are arranged in the order of R, G, and B in the row direction.

As shown in FIG. 2, in the first embodiment of the present invention, two pixels neighboring in the row direction share one data line and a driving element, and the driving element includes a driving transistor M1, a switching transistor M2, and a capacitor ( Cst). Selection scan line (S _i) and the data line two pixel (111 _ij, 112 _ij) of the pixel region (110 _ij) is formed by a (D _j) is the driving element, the two transistors (M31, M32) and the two organic electroluminescent Light emitting elements (hereinafter referred to as " organic EL elements ") (OLED1, OLED2), and the two organic EL elements OLED1, OLED2 emit light of R and G colors, respectively. Selection scan line (S _i) and the data lines (D _{j + 1)} pixel region _{(110 i (j + 1)} ) pixels _{(111 i (j + 1)} , 112 i (j + 1)) of which is formed by the FIG. The organic EL elements OLED1 and OLED2 of the pixels 111 _{i (j + 1)} and 112 _{i (j + 1)} have the same structure as those of the pixels 111 _ij and 112 _ij , respectively. It emits light. In addition, the selection scan line (S _i) and the data lines (D _{j + 2)} pixel region _{(110 i (j + 2)} ) pixels _{(111 i (j + 2)} , 112 i (j + 2)) of which is formed by The organic EL elements OLED1 and OLED2 of the pixels 111 _{i (j + 2)} and 112 _{i (j + 2)} have the same structure as those of the pixels 111 _ij and 112 _ij , respectively. Emit light.

In the pixel region 110 _ij , the source of the transistor M1 is connected to the power supply voltage VDD and the capacitor Cst is connected between the gate and the source of the transistor M1. A data voltage from the transistor (M2) to the data lines (D _j) and is connected between the gate of the transistor (M1), the selection scan lines in response to a selection signal of a low level from the (S _i) the data lines (D _j) It transfers to the gate of transistor M1. Then, between the source and the gate of the transistor (M1) has takes a voltage (V _SG) corresponding to the difference between the data voltage supply voltage (VDD), also this voltage (V _SG) is charged in the capacitor (Cst). Transistors M31 and M32 are connected between the drain of the transistor M1 and the anodes of the organic EL elements OLED1 and OLED2, respectively, and a power supply voltage VSS is connected to the cathodes of the organic EL elements OLED1 and OLED2. have. The power supply voltage VSS is lower than the power supply voltage VDD. Generally, a negative voltage and a ground voltage are used. The i-th light emission scan line E _1i is connected to the gate of the transistor M31 connected to the organic EL element OLED1, and the i-th light emission scan line E is connected to the gate of the transistor M32 connected to the organic EL element OLED2. _2i ) is connected. Low-level emission signals are applied to two emission scan lines E _1i and E _2i in two fields of one frame, respectively. When a low-level emission signal is applied to the emission scan line E _1i , the transistor M31 is turned on, and a current I _OLED as shown in Equation 1 is supplied from the transistor M1 to the organic EL element OLED1, thereby providing an organic EL. The device OLED1 emits light with an intensity of light corresponding to the magnitude of the current I _OLED . When a low level light emission signal is applied to the light emission scan line E _2i , the transistor M32 is turned on and the organic EL element OLED2 emits light. That is, in each of the two fields of one frame, the organic EL elements OLED1 and OLED2 emit light once to express colors.

Where β is a constant, V _SG is the source-gate voltage of transistor M1, and V _TH is the threshold voltage of transistor M1.

Hereinafter, a driving method of the organic EL display device according to the first embodiment of the present invention will be described in detail with reference to FIG. 3. 3 is a signal timing diagram of the organic EL display device according to the first embodiment of the present invention. The selection signals applied to each of the selection scan line (S _i) in Figure 3 to select [i] expressed as, the lighting signal applied to the emission scan line (E _1i, E _2i) each emit1 [i] and emit2 [i] (I is an integer from 1 to m). Since the data voltages are simultaneously applied to the data lines D _{1 to} D _n , only data voltages applied to the j th data line D _j are represented by data [j] in FIG. 3.

As shown in FIG. 3, the organic EL display device according to the first embodiment of the present invention is driven by dividing one frame into two fields 1F and 2F, and selecting scan lines in each field 1F and 2F. The low level select signals select [1] to select [m] are sequentially applied to S _{1 to} S _m . Two organic EL elements OLED1 and OLED2 of two pixels sharing the driving element emit light for a period corresponding to one field, respectively. In addition, the fields 1F and 2F are independently defined for each row, and FIG. 3 illustrates two fields 1F and 2F based on the selection scan line S ₁ of the first row.

In the first field 1F, the selection signal of the selection scanning line S ₁ of the first row becomes a low level pulse, and the data voltage data [j corresponding to the organic EL element OLED1 of each pixel region of the first row 1F. ]) Is transferred to the data line D _j . The light emission signal emit1 [1] of the light emission scan line E ₁₁ becomes a low level pulse and the transistor M31 is turned on. Then, a current corresponding to the data voltage data [j] in the pixel region of the first row is transferred from the transistor M1 to the organic EL element OLED1 through the transistor M31 to emit light. The light emission is performed while the light emission signal emit1 [1] is a low level pulse. In FIG. 3, the width of the low level pulse of the light emission signal emit1 [1] is equal to the period of the first field 1F.

Next, the selection signal select [2] of the selection scan line S ₂ of the second row becomes a low level pulse, and the data voltage data [corresponding to the organic EL element OLED1 of each pixel region of the second row is obtained. j]) is applied to the data line D _j . The light emission signal emit1 [2] of the light emission scan line E ₁₂ becomes a low level pulse, and the transistor M31 is turned on. The organic EL element OLED1 in the pixel area of the second row then emits light during the low level pulse period of the emission signal emit1 [2].

In the same way, the first selection of the second row from the m-th scanning line selection pulse having a low level in the (S ₁ ~S _m) signal (select [1] ~select [m ]) is applied in sequence. And i selection of the second row scanning line selection signal _{(S i) (select [i} ]) is at a low level pulse is for a data voltage corresponding to the organic EL device (OLED1) of the pixel regions (data [j]) is the data line Is applied to (D _j ). And selection scan lines emit light signals of the light-emitting scan lines (E _1i) of the selection signal (select [i]) is at a low level i the two light-emitting scan lines (E _1i, E _2i) th row, when a pulse (S _i) (emit1 [ i]) becomes a low level pulse, and the width of the low level pulse of the light emission signal emit1 [i] is the same period as the first field 1F. Then, after each row is selected in the scanning line (S _i) a selection signal (select [i]) of the low-level pulse period the organic EL device (OLED1) while corresponding to a first field (1F) is to emit light. That is, only the pixel in which the organic EL element OLED1 is formed emits light in two pixels adjacent in the row direction.

In the second field 2F, the selection signal select [1] of the selection scan line S ₁ of the first row becomes a low level pulse and corresponds to the organic EL element OLED2 of each pixel region of the first row. The data voltage data [j] is applied to the data line D _j . The light emission signal emit2 [1] of the light emission scan line E ₂₁ becomes a low level pulse, and the transistor M32 is turned on. Then, the organic EL element OLED2 in the pixel area of the first row emits light during the low level pulse period of the emission signal emit2 [1], and the width of the low level pulse of the emission signal emit2 [1] in FIG. It is equal to the period of the second field 2F.

Next, the selection signal select [2] of the selection scan line S ₂ of the second row becomes a low level pulse and corresponds to the data voltage data [j] corresponding to the organic EL element OLED2 of each pixel region of the second row. ] Is applied to the data line D _j , and the light emitting signal emit2 [2] of the light emission scanning line E ₂₂ of the second row becomes a low level pulse, thereby turning on the transistor M32. The organic EL element OLED2 in the pixel region of the second row then emits light during the low level pulse period of the emission signal emit2 [2].

In the same way, the second field (2F) in the first is from a selection signal (select [1] ~select [m ]) sequentially with a low level pulse of the m selection scan lines (S ₁ ~S _m) th row . i selection signal of the selection of the second row scanning line (S _i) (select [i]) is at a low level pulse is for a data voltage (data [j]) is a data line corresponding to the organic EL device (OLED2) of the pixel regions ( D _j ). When the selection signal select [i] of the selection scan line S _i becomes a low level pulse, the emission signal emit2 [of the emission scan line E _2i of the two emission scan lines E _1i and E _2i in the i-th row. i]) becomes a low level pulse, and the low level pulse width of the light emission signal emit2 [i] is the same period as the second field 2F. Then, each row after the selection scan lines as (S _i) a selection signal (select [i]) is the low level of the pulse period the organic EL device (OLED2) while for the second field (2F) is to emit light. That is, only the pixel in which the organic EL element OLED2 is formed emits light in two pixels adjacent in the row direction.

As described above, the organic EL display device according to the first embodiment of the present invention is driven by dividing one frame into two fields, and in one field, only the organic EL element of one pixel of two pixels in each pixel area emits light. The organic EL elements of the remaining pixels of the two pixels in the other field may emit light, and the organic EL elements of all the pixels may emit light in one frame, and thus all colors may be expressed. In addition, in the first embodiment of the present invention, the two pixels share the driving element and the data line D _j , thereby reducing the number of data lines D _j and the driving elements by half compared to the prior art. Therefore, the number of integrated circuits for driving the data line D _j can be reduced, and the arrangement of elements in the pixel region can be simplified.

Next, the selective scan driver 200 and the emission scan driver 300 capable of generating the driving waveform of FIG. 3 will be described in detail with reference to FIGS. 4 to 6.

4 is a detailed signal timing diagram of a selective scan driver of an organic EL display device according to a first embodiment of the present invention. FIG. 5A is a diagram showing a selective scan driver of the organic EL display device according to the first embodiment of the present invention, and FIG. 5B is a schematic diagram of a flip-flop used in the selective scan driver of FIG. 5A. In FIG. 5A and FIG. 5B, the inverted signal of the clock VCLK is represented by VCLKb, and the illustration of VCLKb is omitted in the driving waveform of FIG. 4. The lengths of the periods of the high level and the low level in the clock VCLK are the same.

Since the structure of the scan drivers 200 and 300 is determined by the pulse width and level of the output signal, the scan drivers 200 and 300 assume the following conditions for the output signals of the scan drivers 200 and 300. First, in order to lower the frequency of the clock VCLK, the low level pulse width of the selection signal is equal to the half clock VCLK. The number _{m of the} selected scan lines S _{1 to} S m is an even number, and accordingly, in the first embodiment, the pulse width of the light emission signal is given by an integer multiple of the clock VCLK. The flip-flop used for the shift register operation in the scan drivers 200 and 300 outputs an input signal for one clock VCLK when the clock VCLK is at a high level or a low level.

In this condition, the output pulse of the flip-flop corresponds to an integer multiple of the clock VCLK, so the output of the flip-flop cannot be directly used as the selection signal. Therefore, after delaying the output signal by a half clock (VCLK) in two adjacent flip-flops, a common portion of the two output signals is output as the selection signal.

To this end, as shown in FIG. 5A, the selective scan driver 200 includes (m + 1) flip-flops FF _{11 to} FF _{1 (m + 1} ) and m NAND gates (NAND _{11 to} NAND _1m ). It acts as a shift register. The output signals of the NAND gates NAND _{11 to} NAND _1m become the select signals select [1] to select [m], respectively. In FIG. 5A, the input signal of the first flip-flop FF ₁₁ is the start signal VSP1 of FIG. 4, and the output signal SR _1i of the i-th flip-flop FF _1i is the (i + 1) th flip-flop ( FF _{1 (i + 1)} ). i-th NAND gate (NAND _1i) is the i-th flip-flop output signal (SR _{1 (i} of the output signal (SR _1i) and (i + 1) th flip-flop (FF _{1 (i + 1))} of (FF _{1i) +1)} ) is subjected to NAND operation and output as a select signal (select [i]). As described above, since the output signals of the flip-flops FF _{11 to} FF _{1 (m + 1)} need to be shifted by half a clock VCLK, respectively, the adjacent flip-flops FF _1i and FF _{1 (i + 1} ) In clocks VCLK and VCLKb are inverted and used.

Specifically, in FIG. 5A, the flip-flop FF _1i positioned in the odd-numbered direction in the vertical direction receives the clocks VCLK and VCLKb as the internal clocks clk and clkb, respectively, and the flip-flop FF _1i positioned in the even-numbered positions. ) Receives clocks VCLKb and VCLK as internal clocks clk and clkb, respectively. The flip-flop FF _1i outputs the input signal in as it is when the clock clk is at the high level, and latches and outputs the input signal in during the low level period when the clock clk is at the low level. However, the flip-flop output signal (SR _1i) is a flip-flop _{(FF 1 (i + 1)} ) the two flip-flops _{(FF 1i, FF 1 (i} + 1)) as the input signal is near the (FF _1i) has a clock (VCLK, VCLKb) for the output signal (SR _1i) of the so inverted is input, the flip-flop output signal _{(SR 1 (i + 1)} ) is a flip-flop (FF _1i) of _{(FF 1 (i + 1)} ) It becomes a signal shifted by half clock VCLK.

As shown in FIG. 4, since the start signal VSP1 is a high level pulse during a period in which the clock VCLK is once high level, the flip-flop FF ₁₁ outputs a high level pulse for one clock VCLK. Thus, flip-flops and sequentially output as shifted by _{(FF 11 ~FF 1 (m +} 1)) is a high-level pulse _{(SR 11 ~SR 1 (m +} 1)) for a half clock (VCLK).

Since the NAND gate NAND _1i performs an NAND operation on the output signals SR _1i and SR _{1 (i + 1} ) of the flip-flops FF _1i and FF _{1 (i + 1)} , the output signals SR _1i and SR _{1 ( i + 1)} outputs a low level pulse when both are high level. The output signal _{(SR 1 (i + 1)} ) of the flip-flop _{(FF 1 (i + 1)} ) in front, as described is for the output signal (SR _1i) of the flip-flop (FF _1i) are moved by a half clock (VCLK) Since the signal is a signal, the output signal select [i] of the NAND gate NAND _1i is in the period in which the two output signals SR _1i and SR _{1 (i + 1} ) are in common a high level pulse, that is, a half clock VCLK. Have a low level pulse for that period. The two output signals SR _{1 (i + 1)} and SR _{1 (i + 2} ) are shifted by half a clock VCLK with respect to the output signals SR _1i and SR _{1 (i + 1)} , respectively. The output signal select [i + 1] of the gate NAND _{1 (i + 1)} is a signal shifted by half the clock VCLK with respect to the output signal select [i] of the NAND gate NAND _1i . . Therefore, as shown in FIG. 4, the selection scan driver 200 may sequentially output the selection signal select [i] while shifting by the half clock VCLK.

Next, an example of the flip-flop FF _1i of FIG. 5A will be described with reference to FIG. 5B.

Referring to FIG. 5B, the flip-flop FF _1i includes a three-phase inverter 211 positioned at an input terminal, an inverter 212 forming a latch, and a three-phase inverter 213. When the clock clk becomes high, the three-phase inverter 211 inverts and outputs the input signal in, and the inverter 212 inverts and outputs the output signal inv of the three-phase inverter 211. . When the clock clk becomes low, the output of the three-phase inverter 211 is cut off, the output of the inverter 212 is input to the three-phase inverter 213, and the output inv of the three-phase inverter 213 is the inverter ( A latch input to 212 is formed. The output signal of the inverter 212 becomes the output signal out of the flip-flop FF _1i , and the input signal inv of the inverter 212 is an inverted signal with respect to the output signal out. As such, the flip-flop FF _1i outputs the input signal in as it is when the clock clk is at a high level, and latches and outputs the input signal in at the high level when the clock clk is at a low level. have.

Next, the light emitting scan driver 300 capable of generating the driving waveform of FIG. 3 will be described in detail with reference to FIG. 6. 6 is a view showing a light emitting scan driver of an organic EL display device according to a first embodiment of the present invention. As shown in FIG. 3, the light emission signal emit1 [i] has a low level pulse for a period corresponding to the first field 1F, that is, a period corresponding to an integer multiple of the clock VCLK. The light emission signal may be generated only by the output of. In addition, referring to FIG. 3, since the i th two light emission signals emit1 [i] and emit2 [i] have inverted forms, one light emission signal emit1 [i] of the two light emission signals is generated and inverted. And the remaining light emission signal emit2 [i].

Referring to FIG. 6, the light emitting scan driver 300 according to the first exemplary embodiment of the present invention includes m flip-flops FF _{21 to} FF _2m and m inverters INV _{21 to} INV _2m . It works. The clock VCLK of the light emitting scan driver 300 is the same as the clock VCLK of the selective scan driver 200. The input signal in of the first flip-flop FF ₂₁ is the start signal VSP2 of FIG. 4, and the output signal out of the i-th flip-flop FF _2i is emitted from the i-th light emission scan line E _1i . The signal emit1 [i], the input signal of the (i + 1) th flip-flop FF _{2 (i + 1)} , and the input signal of the ith inverter INV _2i . The output signal of the inverter INV _2i becomes the light emission signal emit2 [i] of the i-th light emission scanning line E _2i , and the light emission signal emit2 [i] is generated by the inverter INV _2i . has an inverted form for emit1 [i]).

Since the light emission signals emit1 [1] to emit1 [m] sequentially output from the light emission scan driver 300 are shifted by a half clock VCLK, two adjacent flip-flops FF _2i and FF _{2 (i +). In 1)} ), clocks VCLK and VCLKb are inverted and used. Also, the start point of the low level pulse in the output signal emit1 [1] of the first flip-flop FF ₂₁ of FIG. 6 is high in the output signal SR ₁₁ of the first flip-flop FF ₁₁ of FIG. 5A. It is shifted by half clock VCLK with respect to the start point of the level pulse. Accordingly, unlike FIG. 5A, the odd-numbered flip-flops FF _{2i receive} the clocks VCLKb and VCLK as internal clocks clk and clkb, respectively, and the even-numbered flip-flops FF _2i receive the clocks VCLK and VCLKb. Received by internal clocks clk and clkb, respectively.

In order for the emission signal emit1 [1], which is an output signal of the first flip-flop FF ₂₁ , to have a low level pulse during the first field 1F, the clock (1) of the first field 1F may be clocked in the first field 1F. When VCLK) is at the low level, the start signal VSP2 may be at the low level. Since the light emission signal emit1 [1] is at the high level in the second field 2F, the start signal VSP2 may be at the high level when the clock VCLK is at the low level in the second field 2F.

Accordingly, the light emitting scan driver 300 may sequentially output the light emitting signal emit1 [i] having the low level pulse by the half clock VCLK during the first field 1F as shown in FIG. 3. By inverting the light emission signal emit1 [i] with the inverter INV _2i , the light emission scan driver 300 halves the light emission signal emit2 [i] having a low level pulse during the second field 2F. The output may be sequentially performed while shifting by the clock VCLK.

According to the selection scan driver 200 and the emission scan driver 300 described above, the time when the selection signal select [i] falls to the low level in each of the fields 1F and 2F is the emission scan line of the i-th row ( E _1i and E _2i are the same as the low level falling time of the light emission signals emit1 [i] and emit2 [i]. Such a driving waveform may be applied to an organic EL display device of a voltage writing method in which a data signal in the form of voltage is generally transmitted to the data line D _j and written in the capacitor Cst. That is, in the voltage writing method, since the current may be transferred from the driving transistor M1 to the organic EL element OLED1 or OLED2 simultaneously with data writing, the waveform as shown in FIG. 3 is possible. In the organic EL display device of the current write method, however, the driving transistor M1 and the organic EL element OLED1 or OLED2 generally need to be electrically cut off when data is written. Hereinafter, such an embodiment will be described in detail with reference to FIGS. 7 to 10.

7 is a schematic circuit diagram of a pixel according to a second embodiment of the present invention. The organic EL display device according to the second exemplary embodiment of the present invention is a current writing method in which a data signal in the form of a current is transmitted to the data lines D _{1 to} D _n .

As shown in Fig. 7, the structure of the pixel region 110 in the organic EL display device according to the second embodiment of the present invention is the same as that of the first embodiment except for the driving element. In detail, the driving element includes a driving transistor M1, a switching transistor M2, a diode connecting transistor M4, and a capacitor Cst. The connection between the transistors in the pixel region _{(110 ij) (M1, M2} , M31, M32), a capacitor (Cst), the selection scan line (S _i), the light-emitting scan lines (E _1i, E _2i) and the data lines (D _j) between 2 is the same as that in FIG. And a transistor (M4) is connected between the drain and the data lines (D _j) of the transistor (M1), is the selection scan line (S _i) connected to its gate.

If the selected selection signal is at a low level from the scan line (S _i), the data current from the transistor (M2, M4) is turned on the data lines (D _j) flows to the drain of the transistor (M1). As such, when a current flows in the drain of the transistor M1, the capacitor Cst is charged with a voltage, and the capacitor is charged until the current flowing in the drain of the transistor M1 is equal to the data current by the voltage charged in the capacitor Cst. Cst is charged with a voltage. The transistors M31 and M32 are turned off so that no current flows to the organic EL element OLED1 or OLED2.

Next, when the light emission signal from the light emission scan line E _1i becomes a low level, the transistor M31 is turned on so that the current I _OLED is supplied from the driving transistor M1 to the organic EL element OLED1 to supply the current I _OLED. The organic EL element OLED1 emits light at an intensity of light corresponding to the size of the? And the current (I _OLED) is applied to the emission scan lines emit signals, the data lines (D _j) when the selection signal is at a low level from the selection scan line (S _i) before the low level of the (E _1i) data current and same. Similarly, when the light emission signal from the light emission scan line E _2i becomes low level, the transistor M32 is turned on so that a current is supplied from the driving transistor M1 to the organic EL element OLED2 so that the organic EL element OLED2 emits light. do. Is applied to the organic EL device (OLED2) current is the light emitting scan line selection scan line (S _i) the data lines (D _j) when the selection signal is at a low level from before the flash signal is the low level of the (E _2i) transmitted to the Same as the data current.

Next, a driving method of the organic EL display device according to the second embodiment of the present invention will be described in detail with reference to FIG. 8 is a signal timing diagram of an organic EL display device according to a second embodiment of the present invention.

As shown in Fig. 8, in the organic EL display device according to the second embodiment of the present invention, one frame is driven by dividing into two fields 1F and 2F, similarly to the first embodiment. Timing of the light emission signals emit1 [1] to emit1 [m] and emit2 [1] to emit2 [m] applied to the light emission scan lines E _{11 to} E _1m and E _{21 to} E _2m in the fields 1F and 2F. Except for the same as in the first embodiment.

Specifically, the emission signal emit1 [i] transmitted to the emission scan line E _1i of the i-th row in the first field 1F is the selection signal select [i] of the selection scan line S _i of the i-th row. ) Has a low level pulse from the low level to the high level. The low level pulse has a width corresponding to the difference between the period corresponding to the first field 1F and the width of the low level pulse of the selection signal select [i].

Then, the selected scan lines a data current corresponding to the (S _i) two organic EL organic EL device (OLED1) of the element of each pixel region in the i-th row, when subjected to a selection signal (select [i]) of the low level (data [j]) is transferred to the data line D _j . At this time, since the light emission signals emit1 [i] and emit2 [i] of the light emission scan lines E _1i and E _{2i in the} i-th row are in a high level state, the driving transistors M1 are turned off by the transistors M31 and M32 that are turned off. ) And the organic EL elements OLED1 and OLED2 are electrically blocked. Then, the transistors M2 and M4 are turned on by the low level select signal select [i] so that the transistor M1 of each pixel region is diode-connected, and the drain current of the transistor M1 is the data current data [j]. The voltage is charged to the capacitor Cst until it is equal to]). Next, since the light emitting signal emit1 [i] is turned low and the transistor M31 is turned on, the current corresponding to the voltage charged in the capacitor Cst, that is, the data current data [j], becomes the transistor M31. The light is transmitted from the transistor M1 to the organic EL element OLED1 through the light emission.

In the same way, the first selection of the second row from the m-th scanning line selection pulse having a low level in the (S ₁ ~S _m) signal (select [1] ~select [m ]) is applied in sequence. And the selection of the selection scan line (S _i) signal (select [i]) the emission signals of the light-emitting scan lines (E _1i) of the two light-emitting scan lines (E _1i, E _2i) in the i-th row at the point that is at a low level to a high level (emit1 [i]) becomes a low level pulse.

Similarly, the second field emission signal (emit2 [i]) of i light emitting scan line (E _2i) of the second row in (2F) is the i selection signal (select [i]) for selection of the second row scanning line (S _i) low From the point at which the level goes high the low level pulses are present. The low level pulse has a width corresponding to a difference between the period corresponding to the second field 2F and the width of the low level pulse of the selection signal select [i].

Next, the selective scan driver 200 and the light emitting scan driver 300 capable of generating the driving waveform shown in FIG. 8 will be described in detail with reference to FIGS. 9 and 10. 9 is a view showing a light emitting scan driver of an organic EL display device according to a second embodiment of the present invention, and FIG. 10 is a signal timing diagram of the light emitting scan driver of FIG.

 As shown in Fig. 8, in the organic EL display device according to the second embodiment of the present invention, since the signal timing is the same as that of the first embodiment, the selective scan driver 200 in the first embodiment is the same. Since the same structure and timing can be used, only the light emitting scan driver 300 will be described below.

In the second embodiment of the present invention, unlike the first embodiment, when the select signal select [i] is at the low level, the light emission signal emit1 [i] is at the high level, so that the light emission signal emit1 [1] is low. The level pulse width is an odd multiple of half clock VCLK. However, since the output signal of the light emission scan driver 300 of FIG. 6 is always an integer multiple of the clock VCLK, the light emission scan driver 300 of FIG. 6 may not be applied to the waveform of FIG. 8. Therefore, the light emitting scan driver according to the second embodiment of the present invention provides a shift register for calculating and outputting a signal output by an integer multiple of the clock VCLK and a signal shifted by a half clock VCLK, that is, the shift register shown in FIG. Applicable to 300. Further, since the light emission signals emit1 [i] and emit2 [i] are not at a low level for one field, the light emission signals emit2 [i] are inverted as in the first embodiment by inverting the light emission signals emit1 [i]. Cannot be generated.

9, the light emitting scan driver 300 according to the second exemplary embodiment of the present invention has (m + 1) flip-flops (FF _{31 to} FF _{3 (m + 1)} ) and m NAND gates (NAND ₃₁ to N ₎ . NAND _3m ), m NOR gates (NOR _{31 to} NOR _3m ), and m inverters (INV _{31 to} INV _3m ), and operate as a shift register. The output signals of the NAND gates NAND _{31 to} NAND _3m become the emission signals emit1 [1] to emit1 [m] of the emission scan lines E _{11 to} E _1m , respectively, and the output signals of the NOR gates NOR _{31 to} NOR _3m . the output signal is a luminescence signal (emit2 [1] ~emit2 [m ]) of the inverter (INV ₃₁ ~INV _3m) signals, each light-emitting scan lines (E ₂₁ ~E _2m) inverted by. The input signal of the first flip-flop FF ₃₁ is the start signal VSP2 of FIGS. 8 and 10, and the output signal SR _3i of the i-th flip-flop FF _3i is the (i + 1) th flip-flop ( FF _{3 (i + 1)} ). The output signal of the i-th NAND gate (NAND _3i) is an output signal (SR _3i) and (i + 1) th flip-flop (FF _{3 (i + 1))} of the i-th flip-flop _{(FF 3i) (SR 3 (} i ₊₁₎ ) to NAND operation and output. In addition, the output signal of the i-th NOR gate (NOR _3i) is an output signal (SR _3i) and (i + 1) th flip-flop (FF _{3 (i + 1))} of the i-th flip-flop _{(FF 3i)} (SR ₃ ( _{i + 1)} ) is NOR operation and output to inverter (INV _3i ). Here, the NOR gate NOR _3i and the inverter INV _3i serve as OR gates.

The i-th flip-flop FF _3i of FIG. 9 has the same form as the i-th flip-flop FF _2i of FIG. 6. Therefore, when the start signal VSP2 has an inverted shape with respect to the start signal VSP2 of FIG. 3, the flip-flops FF _{31 to} FF _{3 (m + 1) are} shown in the first field 1F. ), The output signals SR _{31 to} SR _{3 (m + 1)} having the high level pulse may be sequentially output while shifting by the half clock VCLK. The NAND gate NAND _3i outputs a low level pulse while the output signals SR _3i and SR _{3 (i + 1} ) of the flip-flops FF _3i and FF _{3 (i + 1} ) are commonly at a high level. Therefore, as shown in FIG. 10, the emission signal emit1 [i] has a low level pulse for a period corresponding to the difference between the first field 1F and the half clock VCLK. Since the output signal emit1 [i + 1] of the NAND gate NAND _{3 (i + 1} ) is shifted by half the clock VCLK with respect to the emission signal emit1 [i], as shown in FIG. The light emission signal emit1 [i] may be generated.

In addition, the output signal SR _3i of the flip-flop FF _3i has a low level pulse during the second field 2F, and the NOR gate NOR _3i has two flip-flops FF _3i and FF _{3 (i + 1).} The output signals SR _3i and SR _{3 (i + 1) of} ) output a high level pulse during a period in which they are commonly low level. Therefore, the output signal of the NOR gate NOR _3i has a high level pulse for a period corresponding to the difference between the second field 2F and the half clock VCLK, and this signal is inverted by the inverter INV _3i , and FIG. 10. The light emission signal emit2 [i] is obtained. Since the output signal of the NOR gate NOR _{3 (i + 1)} is shifted by a half clock VCLK with respect to the output signal of the NOR gate NOR _3i , the light emission signal emit2 [i] as shown in FIG. 10. ) May be generated.

As described above, in the second embodiment of the present invention, two light emission signals emit1 [i] and emit2 [i] are generated by performing NAND and NOR operations on the outputs of two adjacent flip-flops, but the light emission signals emit2 [i]. Can be generated as a NAND operation. 8 and 10, the light emission signal emit2 [i] in the second field 2F has the same waveform as the light emission signal in the first field 1F, and the flip-flop FF _3i of FIG. 9. The output signal SR _3i has an inverted form in the first field 1F and the second field 2F. Accordingly, when the NAND operation is performed after inverting the output signal SR _3i of the flip-flop FF _3i , the emission signal emit2 [i] may be generated. Hereinafter, this embodiment will be described with reference to FIG. 11.

11 is a view showing a light emitting scan driver of an organic EL display device according to a third embodiment of the present invention, and FIG. 12 is a signal timing diagram of the light emitting scan driver of FIG.

Referring to FIG. 11, the light emitting scan driver 300 according to the third exemplary embodiment of the present invention is the light emitting scan driver of FIG. 9 except that the light emitting signal emit2 [i] is generated as the NAND gate NAND _4i . Have the same structure. Specifically, the light emission scan driver 300 includes (m + 1) flip-flops (FF _{31 to} FF _{3 (m + 1)} ), m NAND gates (NAND _{31 to} NAND _3m ), and m NAND gates (NAND _41). To NAND _4m ). Referring to FIG. 5B, in the flip-flop FF _3i , the input signal inv of the inverter 212 is inverted with respect to the output signal, and the input signal inv is the inverted output of the flip-flop FF _3i . Signal / SR _3i . The inverted output signals / SR _3i and / SR _{3 (i + 1) of the} two flip-flops FF _3i and FF _{3 (i + 1)} become input signals of the NAND gate NAND _4i , and the NAND gate ( The output signal of NAND _4i becomes the light emission signal emit2 [i].

And 12, the output of the second field (2F) the flip-flop output signal (/ SR _3i) is a flip-flop (FF _3i) in the first field (1F) inversion of (FF _3i) in Since it has the same shape as the signal SR _3i , the light emission signal emit2 [i] which is an output signal of the NAND gate NAND _4i may have the shape as shown in FIG. 8.

In the above, the light emitting scan driver applied to the organic EL display device of the current writing method has been described in the second and third embodiments of the present invention. However, the light emitting scan driver can also be applied to the voltage writing method. That is, even when the organic EL element blocks light emission while the selection signal is applied in the voltage writing method, the light emission scan driver of the second and third embodiments can be applied.

In the second and third embodiments, the light emission signal emit1 [i] has been described as having a low level pulse for a period corresponding to the difference between the first field and the half clock VCLK. The low level period of the light emission signal emit1 [i] may be adjusted by changing inputs of the NAND gate and / or the NOR gate at. For example, as shown in FIG. 13, the output signals of the (i-1) th and (i + 1) th flip-flops FF _{3 (i-1)} and FF _{3 (i + 1) in} FIG. 9. When (SR _{3 (i-1)} and SR _{3 (i + 1)} ) are input to the i-th NAND gate NAND _3i and the i-th NOR gate NOR _3i , the light emission signal emit1 [i] is set to zero. The light emission signal emit2 [i] has a half clock (at the beginning and the end of the second field 1F, respectively) during the period except for the half clock VCLK at the beginning and the end of the one field 1F, respectively. Have a low level pulse for the period excluding VCLK).

In addition, in the first to third embodiments, it has been described that the time when one selection signal becomes high level and the time when the next selection signal becomes low level are sequentially the same as the selection signals output sequentially. It is also possible for the next select signal to go to the low level after is at a high level and a certain period has elapsed. For example, a pulse having a low level for a period between an end point of a low level pulse of one select signal and a start point of a low level pulse of the next select signal is selected from the NAND (NAND _{11 to} NAND _1m ) of the selection scan driver of FIG. 5A. Can be entered. Although the description has been made assuming that the number of selection scan lines is even in the first to third embodiments, even when the number of selection scan lines is an odd number, the selection and emission scanning drivers described in the first to third embodiments may be modified and applied. have.

In addition, although the selection and light emission scan driver applied to the organic EL display device shown in FIG. 1 have been described in the first to third embodiments, the scan driver can also be applied to the organic EL display device of FIG. 14 is a schematic plan view of an organic EL display device according to a fourth embodiment of the present invention.

Referring to FIG. 14, the connection state of the emission scan lines E _1i and E _2i in the i th row and the emission scan lines E _{1 (i + 1)} and E _{2 (i + 1) in the} (i + 1) th row are shown. The connection status is different. Specifically, in the first row, the emission scan line E ₁₁ is connected to the left pixel 111 in the pixel region 110, and the emission scan line E ₂₁ is connected to the right pixel 112. In the second row, the emission scan line E ₁₂ is connected to the right pixel 112 in the pixel region 110, and the emission scan line E ₂₂ is connected to the left pixel 111. That is, in the odd-numbered row, the light emitting scan line E _1i is connected to the left pixel 111 and the light-emitting scanning line E _2i is connected to the right pixel 112, whereas in the even-numbered row, the light-emitting scanning line E _1i is connected to the opposite side. Then, in the first field 1F, the left pixel 111 of each pixel region 110 in the odd-numbered row and the right pixel 112 of each pixel region 110 in the even-numbered row emit light, and the second field 2F is emitted. ), The right pixel 112 of each pixel region 110 of the odd-numbered row and the left pixel 111 of each pixel region 110 of the even-numbered row emit light.

In the exemplary embodiment of the present invention, the selection signal and the emission signal output from the scan drivers 200 and 300 are directly applied to the selection and emission scan lines, but the input signal is input through a buffer formed between the scan driver and the display area. It may be. In some cases, a level shifter may be formed between the scan driver and the display area to change the level of the selection signal and the light emission signal.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

According to the present invention, two pixels share a data line with a drive element, thereby reducing the number of data lines and drive elements by half compared to the prior art. Therefore, the number of integrated circuits for driving the data lines can be reduced, and the arrangement of elements in the pixel region can be simplified.

1 is a schematic plan view of an organic EL display device according to a first embodiment of the present invention.

2 is a schematic circuit diagram of a pixel according to a first embodiment of the present invention.

3 is a driving timing diagram of the organic EL display device according to the first embodiment of the present invention.

4 is a detailed signal timing diagram of a selective scan driver of an organic EL display device according to a first embodiment of the present invention.

5A is a diagram showing a selective scan driver of an organic EL display device according to a first embodiment of the present invention.

FIG. 5B is a schematic diagram of a flip-flop used in the selective scan driver of FIG. 5A.

6 is a view showing a light emitting scan driver of an organic EL display device according to a first embodiment of the present invention.

7 is a schematic circuit diagram of a pixel according to a second embodiment of the present invention.

8 is a signal timing diagram of an organic EL display device according to a second embodiment of the present invention.

9 is a view showing a light emitting scan driver of an organic EL display device according to a second embodiment of the present invention.

10 is a signal timing diagram of the light emitting scan driver of FIG. 9.

11 is a view showing a light emitting scan driver of an organic EL display device according to a third embodiment of the present invention.

12 is a signal timing diagram of the light emission scan driver of FIG. 11.

FIG. 13 is another signal timing diagram of the light emission scan driver of FIG. 11.

14 is a schematic plan view of an organic EL display device according to a fourth embodiment of the present invention.

Claims (25)

A plurality of data lines for transmitting a data signal representing an image, a plurality of first scanning lines for transmitting a selection signal, a plurality of second and third scanning lines for transmitting a light emission signal, and the data lines and the first scanning lines, respectively; A display area including a plurality of pixel areas, A first driver sequentially transferring the first signal having the first pulse in the first field and the second field by the first period, respectively, to the plurality of first scan lines; and Sequentially transferring the second signal having the second pulse in the first field to the plurality of second scanning lines while shifting the second signal by the second period, and transmitting the third signal having the second pulse in the second field to the second signal. A second driver sequentially transferring the plurality of third scan lines while shifting by a period; The pixel area includes first and second pixels that share the data line and the first scan line, wherein the first pixel emits light by the second pulse of the second signal in the first field, and the second pixel. And the second pixel in the field emits light by the second pulse of the third signal. The method of claim 1, The data signal corresponding to the first pixel is transmitted to the data line while the first pulse is applied in the first field, and the second pixel is applied to the data line while the first pulse is applied in the second field. A display device to which a data signal corresponding to is transmitted. The method of claim 1, The first driving unit, A third driver for sequentially outputting a fourth signal having a third pulse by the first period, and And a fourth driver configured to output a pulse corresponding to the first pulse of the first signal in a period in which the fourth signal and the signal in which the fourth signal is shifted by the first period are commonly the third pulse. Display device. The method of claim 3, The third driving unit includes a plurality of first flip-flops in which an output of the first flip-flop at the front end is an input of the first flip-flop at the rear end, The first flip-flop at the rear end shifts the third pulse of the fourth signal output from the first flip-flop at the front end by the first period and outputs the third pulse to the fourth driver. The method of claim 4, wherein The first flip-flop operates at a first level of a clock to output an input signal, and operates at a second level of the clock to latch and output the input signal. Two adjacent first flip-flops are used with the clock reversed. Display device. The method of claim 1, The second period is the same as the first period. The method according to any one of claims 1 to 6, The second drive unit, The second pulse of the second signal is applied to the second scan line of the first pixel at substantially the same time as the time when the first pulse of the first signal is applied to the first scan line of the first pixel in the first field. Licensed, The second pulse of the third signal is applied to the third scan line of the second pixel at substantially the same time as the time when the first pulse of the first signal is applied to the first scan line of the second pixel in the second field. Approved display device. The method of claim 7, wherein The second driver generates the third signal by inverting the second signal. The method of claim 8, The second driving unit includes a plurality of second flip-flops in which an output of the second flip-flop at the front end is an input of a second flip-flop at the rear end, The second flip-flop at the rear end shifts and outputs a pulse corresponding to the second pulse of the second signal output from the second flip-flop at the front end by the second period. The method according to any one of claims 1 to 6, The second drive unit, Applying a second pulse of the second signal to the second scan line of the first pixel after an end of the first pulse of the first signal applied to the first scan line of the first pixel in the first field , Applying a second pulse of the third signal to the third scan line of the second pixel after an end of the first pulse of the first signal applied to the first scan line of the second pixel in the second field Display device. The method of claim 10, The second drive unit, A fifth driver sequentially outputting a fifth signal having a fourth pulse by a fourth period, and A sixth driver configured to output a pulse corresponding to the second pulse of the second signal in a period in which the signal shifted by the fifth signal and the fifth signal by an integer multiple of the fourth period is the fourth pulse in common; Display device comprising a. The method of claim 11, The fifth signal has a fifth pulse of an inverted level with respect to the fourth pulse for a period other than the fourth pulse, The second driver may include a pulse corresponding to the second pulse of the third signal in a period in which the fifth signal and the signal in which the fifth signal is shifted by an integer multiple of the fourth period are the fifth pulse in common. The display device further comprises a seventh driver for outputting the. The method of claim 11, The second driver may include a sixth signal in which the fifth signal is inverted and a sixth signal in which the sixth signal is shifted by an integer multiple of the fourth period, and has a fifth pulse having the same level as the fourth pulse. And a seventh driver configured to output a pulse corresponding to the second pulse of the third signal. The method of claim 11, The fifth driver includes a plurality of third flip flops in which an output of the third flip flop at the front end is an input of a third flip flop at the rear end, And the third flip-flop at the rear end shifts the fourth pulse of the fifth signal output from the third flip-flop at the front end by the fourth period and outputs the fourth pulse to the fifth driver. A display device comprising: a plurality of first scan lines for transmitting a first signal, a plurality of second scan lines for transmitting a second signal, and a plurality of third scan lines for transmitting a third signal, The first signal has a first pulse during a first period in the first field and the second field respectively, the second signal has a second pulse during the second period in the first field, and the third signal is the Having the second pulse during the second period in a second field, The display device, A first driver which sequentially outputs the first signal to the plurality of first scan lines while shifting the first signal by a third period, and A second driver that sequentially outputs the second signal to the plurality of second scan lines while shifting the second signal, and sequentially outputs the third signal to the plurality of third scan lines while shifting the third signal by the third period Display device comprising a. The method of claim 15, The first driving unit, Sequentially outputting a fourth signal having the third pulse by the third period in a fourth period longer than the third period in the first field and the second field, respectively, And a pulse corresponding to the first pulse during a period in which the fourth signal and the fourth signal shifted by the fourth signal by the third period are the third pulse in common. The method of claim 15, The starting point of the first pulse of the first signal in the first field is substantially the same as the starting point of the second pulse of the second signal, The starting point of the first pulse of the first signal in the second field is substantially the same as the starting point of the second pulse of the third signal, The second driver generates the third signal by inverting the second signal. The method of claim 15, The second drive unit, Outputting a fourth signal sequentially having a fourth pulse and a fifth pulse whose level is inverted with respect to the fourth pulse while shifting by the third period, Output a pulse corresponding to the second pulse of the second signal during a period in which the fourth signal and the fourth signal in which the fourth signal is shifted by an integer multiple of the third period are commonly the fourth pulse, An indication that outputs a pulse corresponding to the second pulse of the third signal during a period in which the fourth signal and the fourth signal shifted by an integer multiple of the third period are the fifth pulse in common; Device. The method of claim 15, The second drive unit, Outputting a fourth signal sequentially having a fourth pulse and a fifth pulse whose level is inverted with respect to the fourth pulse while shifting by the third period, Output a pulse corresponding to the second pulse of the second signal during a period in which the fourth signal and the signal in which the fourth signal is shifted by an integer multiple of the third period are commonly the fourth pulse, The second pulse of the third signal during the period when the fifth signal in which the fourth signal is inverted and the fifth signal in which the fifth signal is shifted by an integer multiple of the third period are the fifth pulses which are commonly inverted. A display device for outputting a pulse corresponding to the. The method of claim 18 or 19, The second pulse of the second signal is started after the first pulse of the first signal in the first field and the third after the first pulse of the first signal in the second field And the second pulse of the signal is started. The method according to any one of claims 15 to 19, A plurality of data lines for transmitting a data signal representing an image, and A plurality of pixel areas defined by the data line and the first scan line, respectively; The pixel area is, A drive element for writing a data signal from said data line in response to said first pulse of said first signal; A first light emitting device that emits light in accordance with the data signal written to the driving element in response to the second pulse of the second signal, and And a second light emitting device that emits light according to the data signal written to the driving device in response to the second pulse of the third signal. A method of driving a display device including a pixel region formed by a first scan line, a second scan line, a third scan line, and a data line for transmitting a data signal representing an image, the method comprising: Outputting a first signal having a first pulse for a first period in each of the first field and the second field; Outputting a second signal having a second pulse during a period in which the first signal and the signal shifted from the first signal by a second period shorter than the first period are commonly the first pulse, Outputting a third signal having a third pulse for a third period in the first field, and Outputting a fourth signal having the third pulse during the third period in the second field, In a pixel region in which a data signal from the data line is written when a pulse corresponding to the second pulse is applied to the first scan line, the first pixel is applied to the third pulse of the third signal on the second scan line. And a second pixel emits light when a pulse corresponding to the third pulse of the fourth signal is applied. The method of claim 22, And the third signal has a fourth pulse having a level inverted with respect to the third pulse in the second field, and the fourth signal is generated by inverting the third signal. The method of claim 22, The outputting of the third signal and the fourth signal may include: Outputting a fifth signal alternately having a fourth pulse and a fifth pulse having an inverted level with respect to the fourth pulse; Shifting the fifth signal by an integer multiple of a fourth period to output a sixth signal, Outputting a third pulse of the third signal while the fifth signal and the sixth signal are the fourth pulse in common; and And outputting a third pulse of the fourth signal while the fifth signal and the sixth signal are the fifth pulse in common. The method of claim 22, The outputting of the third signal and the fourth signal may include: Outputting a fifth signal having a fourth pulse and a fifth pulse having an inverted level with respect to the fourth pulse, and a sixth signal in which the fifth signal is inverted; Outputting a seventh signal and an eighth signal by shifting the fifth signal and the sixth signal by an integer multiple of a fourth period, respectively, Output a third pulse of the third signal during a period in which the fifth signal and the seventh signal are the fourth pulse, and And outputting a third pulse of the fourth signal during the period of the fifth pulse in which the sixth signal and the eighth signal are inverted in common.