KR20050086675A - Memory based device and method for channel estimation in a digital communication receiver - Google Patents

Abstract

The present invention provides an input memory buffer 16 for storing samples of the input signal y (k), a code generator circuit 30 for generating a regenerated user code, and an input signal y (k) for each received signal. Select the device 24 for evaluating channel delay profile energy to calculate the time delays and amplitudes of the multipath elements, the plurality of fingers 18 and the most powerful multipath elements of the input signal y (k). And a finger assignment unit (26) for processing channel delay profile energy for allocating the multipath elements to the fingers (18).

The apparatus 24 for evaluating the channel delay profile energy also includes a first input 41 for continuously reading a plurality of samples of the input signal y (k) from a memory location of the input memory buffer 16. A channel delay by means of a correlation operation between the second input 43 and the plurality of samples of the input signal and the regenerated user code, for receiving a regenerated user code from the code generator circuit 30; A basic correlator 32 comprising an output for generating a value of the profile energy DP (l), and a new value of the basic correlator 32 to calculate a new value of the channel delay profile energy DP (l). Addressing the input memory buffer 16 such that each addressing operation corresponding to a correlation operation is continuously input by the first input portion 41 of the basic correlator 32 to the memory location contents of the memory buffer 16. memory controller circuitry 36 for addressing.

Description

Memory Based Device and Method for Channel Estimation in a Digital Communication Receiver

The present invention relates to a telecommunication system, and more particularly to a digital receiver for use in a code division multiple access (CDMA) system. The invention also relates to an apparatus and method for evaluating a channel delay profile in a digital communication receiver.

It is now found that CDMA access technology is widely used in third generation mobile communication systems (e.g., UMTS, CDMA2000) due to greater spectral efficiency than other technologies.

Data sequences in CDMA systems are spread by pseudo noise codes (hereinafter referred to as " PN codes ") having wider spectral widths. The efficiency of such a system depends primarily on the receiver's ability to continuously maintain accurate phase synchronization between the received PN code and the locally generated PN code.

In fact, without accurate phase synchronization between the received PN code and the locally generated PN code, the performance loss of the receiver is a few dB even for a mismatch of half the chip period.

Phase synchronization processing is usually performed in two stages: code acquisition and code tracking. The code acquisition is an initial search process that brings the phase of the locally generated code into the chip period (Tc = 1 / Fc) of the code. Code tracking is a process of achieving and maintaining fine alignment of chip boundaries between input code and locally generated codes.

In particular, the present invention relates to a code acquisition process.

One CDMA receiver is usually implemented in the form of a RAKE receiver which collects signal energy from other multipath elements and closely combines each contribution. Basically, the rake receiver consists of a number of independent receiving units called fingers that each tune the transmitted signal to a different replica. In addition, the rake receiver operates properly only if the time delay and amplitude of the other multipath components are accurately evaluated.

Thus, it is necessary to consider a special module that evaluates the time delay and amplitude of other multipath components of the signal received within the functional modules of the rake receiver. The detection of multipath elements, that is, path detection, affects the capacity of a CDMA system because false or missed detection must increase the transmission power required to achieve the desired quality of service (QoS).

In the following we describe some known methods used for channel delay profile estimation in CDMA receivers. These methods can be divided into two different groups depending on the individual structures used. As the two methods, a method based on a code delayed architecture (CDA) and a method based on a data delayed architecture (DDA) may be considered.

 In the CDA delay profile estimator, one copy of the PN sequence is correlated with data generated at the receiver or directly received. During the subsequent correlation operation, the phase of the PN sequence is changed periodically to scan for other locations (eg, delays) of the receiving search window.

 The phase of the data received at the DDA delay profile estimator changes periodically, while the phase in the PN sequence remains fixed. The displacement of the received data is generally obtained by storing the received signal samples in the delay line and taking samples periodically during the correlation operation from other locations in the delay line.

In the description of known methods, various signals are represented by a complex envelope of each signal represented by two components, in-phase (I) and in-quadrature (Q). The information sequence generated by the receiver is denoted by u (n), where n is the information symbol period Discrete time index related to.

u (n) = u (n * ) n = 0, 1, 2, ...

The PN code sequence S (k) is expressed as follows.

S (k) = S (k * ) = (k) + j * (k) k = 0, 1, 2, ...

Where k is the chip cycle Discrete time index related to. PN sequences are periodic in the period of Spreading Factor (SF) chips and are assigned to each user to minimize cross-interference between users whose different sequences share the same channel.

S (k) = S (k + SF) ∀k ≥ 0

The information sequence u (n) is spread by multiplying each information symbol by the PN code sequence S (k) produced by the chips following SF as follows.

x (k) = (k) + j * (k) = u (k div SF) * S (k)

As a result, the chip period Symbol period after the spreading operation It is SF times smaller and is increased by the signal bandwidth factor SF of the information sequence after the spreading operation. The discrete time index n of the information sequence is expressed as a function of the discrete time index k of the chip sequence in the following manner.

n = k div SF

The k div SF is an integer part of the quotient between k and SF.

The signal x (k) is then filtered, filtered and transmitted over a propagation channel. In the special case where the propagation path has only one direct path between the transmitter and the receiver, the baseband signal reaching the input of the rake receiver from the front end of the receiver is denoted by y (k) and y (k) As follows.

y (k) = x (k) * c (k) + n (k) = u (k div SF) * S (k) * c (k) + n (k)

Where c (k) = (k) + j * (k) represents the distortion introduced by the propagation channel because of the fast padding and Doppler effect, where n (k) = (k) + j * (k) shows the result of the interference combined with the thermal noise.

The channel delay profile is h (ㅣ) = (l) + j * It is represented by (l), where l is a variable according to channel delay spread. In the present invention, it is assumed that the time spread of the channel is limited to T chips after signal replication to H chips before the most strongly received signal replication. As a result, the variable l is in the following range.

-H ≤ l ≤ T

Here, the value of = 0 = corresponds to the time position of the strongest signal replication and, therefore, is generally adopted as a reference for synchronization of the receiver. The receive search window, in which the rake receiver can capture the energy of the multipath elements, has an H + T + 1 chip length.

Finally, in the present invention, channel delay profile energy is defined as DP (l) as follows.

DP (l) = (l) + (l)

In addition, the following methods are described for channel profile estimation.

Serial correlator (CDA)

Bank of correlators (CDA)

Serial correlator (DDA)

Matched filtor (DDA)

A first method for channel profile evaluation is a sequential correlator based on CDA, the sequential correlator structure being shown in FIG.

The received signal y (k) is a PN sequence multiplied by the conjugate complex number of (k-1), and the result is accumulated through an integration window of NC subsequent chips (e.g., NC may be equal to SF). After integration, the channel profile energy is calculated by multiplying the two signal elements. Therefore, the channel profile is calculated by the following equation.

h (l) = y (i) * (i-1)

The profile energy is given by

DP (l) = +

Each value of l (−H ≦ l ≦ T) corresponds to one particular delay in the code sequence and one point in the channel profile. The calculation at one point of the delay profile requires a time interval of NC chips, and in general, for the delay profile at H + T + 1 points, the time required for this profile calculation is as follows.

= (H + T + 1) * NC [chips]

In order to reduce the time required for the profile calculation, it is possible to use a bank of sequential correlators in which each correlator is fed to another copy of the PN code sequence. For example, by using H + T + 1 correlators, when all points of the profile are calculated in parallel, the time required for profile calculation is reduced to the NC chip.

= NC [chips]

A block diagram for a bank of sequential correlators based on the CDA solution is shown in FIG. Other copies of the PN code sequence, (k + H), (k + H-1) ... (kT) are obtained by using a single code generator that records code values in a memory buffer. At the same time, other copies of the PN code can also be read from other locations in the memory buffer 2 as shown in FIG.

The sequential correlator (DDA) represents a dual solution with respect to the sequential correlator (CDA). In the DDA solution, the phase of the PN code remains fixed while the phase of the received data changes. This is obtained by storing the samples received at the delay line 4 and taking samples periodically during the correlation operation from another location on the delay line. A block diagram of the sequential correlator (DDA) is shown in FIG.

The channel profile is calculated by the following equation.

h (l) = y (i + 1) * (i)

At this time, the given profile energy is as follows.

DP (l) = +

The time required to calculate a profile is the same as the CDA solution and also the NC chips. As a result, the time required to calculate the complete profile for H + T + 1 points is as follows.

= (H + T + 1) * NC [chips]

By using a matched filter, it is possible to reduce the time required for the DDA solution for channel delay profile calculation. A matched filter is a filter whose frequency characteristic is designed to precisely match the frequency spectrum of the input signal. In a CDMA system the matched filter is tuned to match the code sequence that is expected to appear in the digital samples input to the receiver. For example, in the case of a UMTS system, a channel suitable for uplink channel delay profile estimation is a dedicated physical control channel (DPCCH).

The matched filter is a dual solution with respect to the bank of sequential correlators for CDA. The filter is matched to a PN sequence, thus filter coefficients (j) is obtained by the following formula.

(j) = (NC-j) 1 ≤ j ≤ NC

A block diagram of the matched filter is shown in FIG.

The matched filter detects the presence of a PN code sequence in the input data stream. The output of the matched filter can be seen as a score value that indicates a match in the code sequence. High score values indicate a good correlation between the PN code sequence and the input data.

The output of the matched filter is calculated according to the following equation.

h (l) = y (i + 1) * (ik)

Here, the profile energy is as follows.

DP (l) = +

The time required for the matched filter to calculate the channel delay profile is the search window length, i.e. (NC-1) required to fill the filter delay line with samples input to the H + T + 1 chips. It's like adding chips.

= H + T + 1 + (NC-1) [chips]

The matched filter (DDA) and the bank of correlators (CDA) provide faster path detection than other solutions, but are very complex and power consuming.

The theory supporting the operations performed by a bank or matched filter (DDA) of the correlators (CDA) for calculating a channel delay profile in a spread spectrum receiver is described in IEEE Transactions and Communications, Vol. , Theory of Spread Spectrum Communications-A Tutorial by RL Pickholtz, DL Shilling, LB Milstein et al., No. 5, May 1982.

The problem of reducing the complexity of the matched filter structure is addressed in US Pat. No. 5,715,276. The US 5,715,276 patent relates to a matched filter (DDA) for use as part of a spread spectrum receiver, wherein the matched filter (DDA) has the same filter length divided by half the length of N / 2. N corresponds to the number of taps of the matched filter.

The matched filter described in the US Pat. No. 5,715,276 patent requires less logic gates for the classic matched filter, but has a problem with the overall hardware implementation of the filter.

The structure of a rake receiver, as is well known, incorporates a memory buffer for temporarily storing an input data stream (DDA) or locally generated PN code (CDA).

The structure disclosed in the WO 00/25437 patent is an example of a rake receiver structure in which an input memory buffer is installed and executed with dual-port RAM. The I / Q sample pair at the rake receiver input is stored in RAM memory (RAM) via a first port, while the second port is used to connect the same memory in read mode.

Another Rake receiver architecture (DDA), which incorporates a conventional input memory buffer, was developed at the Third IEEE Signal Processing Workshop on Signal Processing Advances in Wireless Communications, held in Taoyuan, Taiwan, March 20-23, 2001. A Flexible Rake receiver Architecture for WCDMA Mobile Terminals, published by H. Lasse, N. Jari.

Such a rake receiver structure incorporates an input memory buffer, which is used to store an I / Q sample pair at the rake receiver input, and writes data to three portions, the buffer. A time-sliding window divided into a write window for writing and a pre-window and a post-window for reading access without overlapping with the write window. This is realized with an input stream buffer such as a time-sliding window Read and write connections are alternately performed to avoid connecting memory at the same time. The correlator reads the multipath samples from the stream buffer and sequentially despreads the multipath elements.

And another Rake receiver architecture (CDA), in which the input memory buffers for the different phases of the previous PN code sequence are embedded, is described in June 1990, IEEE Journal on Selected Area in Communications, Vol. Grob, AL It is disclosed in "Microcellular Direct-Sequence Spread-Spectrum Radio System Using N-Path RAKE Receiver" published by Welti, E. Zollinger, R Kung and H. Kauffman.

Applicant has studied the problem of further reducing the complexity and silicon requirements in the channel delay profile evaluation device of the rake receiver.

In addition, Applicants have found that a RAN buffer is always needed regardless of the choice of receiver structure in the rake receiver. The RAM buffer is used to store data coming from the receiver front-end in the case of the DDA structure and to store data arriving from the code generator circuit in the case of the CDA structure.

Applicants have found in the prior art using a matched filter (DDA) that the delay files of the matched filter partially replicate the functionality of the RAM buffer to store data coming from the front end of the receiver. In fact, both the delay line and the RAM buffer store the same data.

Similarly, in the prior art using Applicants' banks of correlators (CDAs), the delay line partially copies the function of the Rake receiver RAM buffer to store other PN code copies for the delay line required for the generation of other phases of the PN sequence. Figured out. In fact, both the delay line and the RAM buffer store the same data.

It is therefore an object of the present invention to provide a method and apparatus for evaluating channel delay profile in a digital communication receiver, which reduces the hardware complexity of the rake receiver and consequently reduces the silicon area of the chip into which the system is integrated. .

1 is a block diagram illustrating a conventional sequential correlator (CDA)

2 is a block diagram illustrating a bank of conventional sequential correlators (CDA)

3 illustrates a single PN code generator for writing PN code samples to a conventional memory buffer.

4 is a block diagram illustrating a conventional sequential correlator (DDA).

5 is a block diagram illustrating a conventional matched filter correlator (DDA).

6 is a block diagram illustrating a DDA structure rake receiver implemented in accordance with the first aspect of the invention.

7 illustrates a delay profile evaluation unit used in the rake receiver shown in FIG. 6 in accordance with the present invention.

8 illustrates a detailed structure of a basic correlator used in a rake receiver implemented according to the present invention.

9 is a block diagram illustrating a rake receiver implemented in accordance with a second aspect of the present invention.

10 shows a delay profile evaluation unit used in the rake receiver shown in FIG.

Applicants note that in a rake receiver with a DDA structure, an input memory buffer used to store data coming from the front end of the receiver can be used in the channel delay profile estimation unit as an input delay line. Paid. According to a first aspect of the invention, the basic correlator sequentially reads data from the input memory buffer of the rake receiver, correlates the regenerated user code with the data read from the input memory buffer, and stores the result in cumulative memory.

A second aspect of the invention relates to a channel delay profile estimation unit for a rake receiver having a CDA structure. The CDA structure uses a memory buffer to store PN code values coming from the code generator circuit. The basic correlator sequentially reads the code elements regenerated from the memory buffer, correlates the read code elements with the received data, and stores the result in accumulated memory.

Accordingly, the Applicant has found that compared to the conventional receiver architecture, the hardware complexity of the Rake receiver is significantly reduced, and the computation time is slightly increased due to the offset of the significantly reduced complexity.

6 is a block diagram illustrating a digital communication receiver implemented in accordance with the first aspect of the invention (DDA structure).

Referring to FIG. 6, the rake receiver 10 is not shown in the figure but the chip frequency from the receiver front-end. Receive an input signal y (k) sampled N times. The input signal y (k) is a random access memory (RAM) 16 having a size equal to a channel delay spread of an H + T + 1 chip and a delay profile estimation unit. Supplied to 24.

The delay profile estimation unit 24 calculates time delays and amplitudes of each received multipath elements, and outputs a channel profile energy DP (l). Where l is a variable for channel delay spread.

The rake receiver 10 is, from a functional standpoint, a modular device consisting of a plurality of independent receivers, i.e., fingers 18, each tuned to a different replica of the transmitted signal. Each finger F1..Fn performs descrambling, despreading and integration of chips of the input signal. In addition, the delay profile evaluation unit 24 regularly calculates a channel delay profile in order to allocate the required number of fingers. The main peaks of the delay profile are assigned to the fingers 18 of the rake receiver. Since the measured delay profile is affected by noise, interference, fading, etc., a suitable module 26, commonly referred to as a finger allocation unit, is described above. Compensate for these damages mentioned and select the optimal positions of the assigned fingers and the number of assigned fingers.

The outputs of the fingers 18 are coupled by a combiner 22, the output 14 of the combiner 22 being deinterleavers, channel decoders, although not shown in FIG. 6. It can be connected to the following modules, such as decorders.

A delay profile estimation unit 24 implemented by the first aspect of the invention as a sequential correlator (DDA) is shown in detail in FIG. 7. A basic correlator 32 whose structure is described with reference to FIG. 8 reads data from RAM 16, which is the input memory buffer of the rake receiver, and data read from RAM 16. Correlate with the regenerated user code provided by the code generator unit 30.

The channel profile energy DP (l), which is the result of the correlation operation, is stored in a memory such as, for example, a RAM memory, which is called a profile accumulation memory (PAM) 34.

The input memory buffer (RAM) 16 and the profile accumulation memory (PAM) 34 are both addressed by a memory controller 36. That is, the read and write operations of the basic correlator 32 in the memories 16 and 34 are handled by the memory controller 36.

For example, samples of the input channel y (k) may be written or read by the memory buffer 16 as in a circular buffer. In particular, write and read operations can be performed through respective points of the increased module with buffer size H + T + 1.

At all NC chips whose integration window size is NC, the memory controller 36 updates the reading pointer of the memory buffer 16 to calculate the next point of the channel delay profile energy. .

When the basic correlator 32 processes the first NC chips, the first point of the channel profile energy DP (k) is obtained and stored in the PAM memory 34. Then, the basic correlator 32 changes the read and write positions of each of the memories 16 and 34 and processes the next NC chip, so that the basic correlator 32 has a second point DP (k +) of the channel profile energy. Calculate 1).

A direct way to improve the reliability of delay profile evaluation is to implement non-coherent accumulation of several delay profiles. Non-coherent detection eliminates phase rotation introduced by the channel and allows energy sums of various delay profiles to be obtained at different times. The non-coherent accumulation can be expressed as follows.

(ㅣ) = (ㅣ) ∀ ㅣ

Where Is the number of accumulations, Is the non-coherent cumulative profile, Is Channel profile energy.

When there is no accumulation, the delay profile evaluation unit 24 calculates a delay profile of H + T + 1 points at the same time as the NC * (H + T + 1) chip. For example, taking into account the delay profile at 128 points and the integral window of 256 NCs, the time required for the sequential correlator to calculate this corresponds to 13 slots in FDD mode in a UMTS system, for example. Same as the 32768 chip. In order to further improve the reliability of the estimated delay profile, It is larger than times. Moreover, if the channel delay profile is oversampled with n samples per chip, the calculation time is n times larger because the number of points to be calculated is n * (H + T + 1) for each profile.

Multiple chip frequencies to reduce the computation time needed for evaluation of delay profiles It is possible to time multiplex the basic correlator 32 in. For example, L times the chip frequency In the multiplexed base correlator, we oversample at n samples per chip The delay profile of the H + T + 1 chip accumulated twice can be calculated at the following time.

= * n * [chips]

On the other hand, time multiplexing of the basic correlator increases the access frequency of the memory buffer 16.

The structure of the basic correlator 32 is shown in detail in the block diagram of FIG. 8. The basic correlator 32 is provided by the first input unit Data for receiving the complex sequence (I, Q elements) of the NC chip corresponding to the received signal y (k) and the code generator unit 30 of FIG. It has a 2nd input part (Code) which receives the complex PN code sequence of the generated NC chip.

In a special case, such as a UMTS receiver operating in FDD mode, the basic correlator 32 is a descrambling and despreading unit for multiplying the complex conjugate of the input data and the regenerated user code. (40) and two integral and dump units (42) which perform the sum of the NC partial products at the output of the descrambling and despreading unit (40). And two square units 44 for calculating the energy of received symbols output from the two integral and dump units 42. do. The energies of the two signal components are then combined by an adder 46.

The apparatus for evaluating the channel delay profile described above operates according to a method having the following steps.

a) sequentially reading a first plurality of samples of the input signal y (k) from the memory buffer 16,

b) correlating the plurality of samples of the input signal with the regenerated user code to generate a first value of channel delay profile energy DP (k);

c) updating the read position of the input memory buffer 16 to read the next plurality of samples of the input signal y (k),

d) correlating the next plurality of samples of the input signal with the regenerated user code to generate a next value of the channel delay profile energy DP (k + 1) stored in the profile accumulation memory 34;

e) repeating steps c) to d) to calculate a channel delay profile at all points.

With reference to FIG. 9, a digital communication receiver implemented in accordance with the second aspect of the present invention will be described. The block diagram of FIG. 9 shows a rake receiver based on a Code Delayed Architecture (CDA) employing a delay profile evaluation unit or a sequential correlator (CDA) detailed in FIG. 10. Since the measurement delay profile is affected by noise, interference, fading, etc., a suitable module 76, commonly referred to as a finger allocation unit, is responsible for such effects as noise, interference, fading, and the like. To compensate, select the optimal positions and the number of assigned fingers.

The rake receiver implemented using the CDA is a complex conjugate of the PN code sequence generated by the code generator unit 52 for the same time as the full channel delay spread of the H + T + 1 chip. RAM memory buffer (RAM) 50 is used. The received signal y (k) is multiplied directly at every fingers 78 with one code replica obtained via connection to other locations in the RAM memory, as shown in FIG. The output of the fingers 78 is coupled by a combiner 72, which may be coupled to subsequent modules such as interleavers and channel decoders, although not shown in FIG. As with the DDA structure, read and write operations in the memory buffer 50 can be configured, for example, as circular buffers.

In the delay profile evaluation unit shown in FIG. 10, the re-generated user code sequence generated in the code generator unit 52 is stored in the RAM memory buffer 50 of the receiver while the received data y (k) is stored in the basic correlator 54. Supplied directly.

The basic correlator 54 reads a number of consecutive PN code elements, such as NC, from the RAM memory buffer 50, correlates them with the received data y (k) and generates one point of the delay profile. The delay profile energy values above are stored in PAM 56, which is a profile cumulative memory as previously mentioned in the DDA solution.

Then, in every NC chip, the basic correlator 54 updates the reading position of the NC chip in the RAM memory buffer 50 and repeatedly performs the correlation operation to calculate the next point of the channel delay profile.

Addressing operations of the RAM 50 and the PAM 56 are controlled by a memory controller 58.

As described with reference to the DDA structure, time multiplexing of the base correlator 54 reduces the computation time of the delay profile.

The apparatus for evaluation of the channel delay profile described previously with reference to the CDA structure operates according to a method having the following steps.

a) sequentially reading the first plurality of samples of the user code regenerated from the memory buffer 50,

b) correlating the input signal y (k) with a plurality of samples of the regenerated user code to generate a first value of the channel delay profile energy DP (k),

c) updating the read position of the input memory buffer 50 to read the next plurality of samples of the regenerated user code;

d) correlation of the input signal y (k) with the next plurality of samples of the regenerated user code to generate the next value of the channel delay profile energy DP (k + 1) stored in the profile accumulation memory 56; Making a step,

e) repeating steps c) to d) to calculate a channel delay profile at all points.

The delay profile evaluation unit according to the invention, which is implemented by either a rake receiver of the DDA or CDA structure, offers several advantages over the matched filter, in particular of the conventional invention.

The delay line of the matched filter is implemented by having a cascaded series of flip-flops, while the sequential correlator uses a RAM memory buffer already present in the rake receiver structure as the delay profile evaluation unit. Moreover, unlike matched filters, the sequential correlator maintains receiver modularity. In fact, the sequential correlator can be seen as a sub-system internal to the rake receiver since it is concentrated to a single user. Because of the need to split the filter among several users, the burden of any communication, for example updating the matched filter constants, is avoided.

Claims (18)

An input memory buffer 16 for storing samples of the input signal y (k); Code generator circuit 30 for generating a regenerated user code; An apparatus 24 for evaluating channel delay profile energy for the input signal y (k) to calculate the time delays and amplitudes of each received multipath element; A plurality of fingers 18; Spread spectrum digital communication comprising a finger assignment unit 26 for selecting the most powerful multipath elements of the input signal y (k) and processing channel delay profile energy for assigning the multipath elements to fingers 18. In the receiver, The apparatus 24 for evaluating the channel delay profile energy comprises a first input 41 for continuously reading a plurality of samples of the input signal y (k) from a memory location of the input memory buffer 16, and A channel delay profile energy by means of a correlation operation between the second input 43 and the plurality of samples of the input signal and the regenerated user code, for receiving the generated user code from the code generator circuit 30; A basic correlator 32 comprising an output unit for generating a value of DP (l), In order to calculate a new value of the channel delay profile energy DP (l), each addressing operation corresponding to the new correlation operation of the basic correlator 32 is converted into a basic correlator (i.e., a memory location of the memory buffer 16). And a memory controller circuit (36) for addressing said input memory buffer (16) such that said first input (41) of said 32 is continuously input. The method of claim 1, A spread spectrum digital communication receiver, characterized in that the values of the channel delay profile energy (DP (l)) are gradually stored in the profile accumulation memory (34). The method of claim 2, The memory controller circuit 36 addresses the profile accumulator memory 34 such that the basic correlator 32 performs a read operation from the memory buffer 16 and write operation to the profile accumulator memory 34. Spread spectrum digital communication receiver. The method of claim 3, wherein The memory controller circuit 36 updates the addressing of the input memory buffer 16 and the profile accumulation memory 34 every NC (NC is an integral window size) chip to change the read and write positions of the basic correlator 32. A spread spectrum digital communication receiver, characterized in that. The method of claim 3, wherein Spread-spectrum digital, characterized in that addressing resumes periodically at the first position of the two memories 16, 34 when the final memory positions of the input memory buffer 16 and profile accumulation memory 34 are reached. Communication receiver. The method of claim 3, wherein The base correlator (32) is time multiplexed at a plurality of chip frequencies (Fc) between an input memory buffer (16) and a plurality of memory locations of a profile accumulation memory (34). The method of claim 2, A spread spectrum digital communication receiver, characterized in that the delay profile energy DPacc (l) is obtained by accumulating the energies of some delay profiles DPi (l). Evaluation of channel delay profile energy of a spread spectrum digital communication receiver comprising an input memory buffer 16 storing samples of the input signal y (k) and a code generator circuit 30 for generating a regenerated user code In the method, a) sequentially reading the first plurality of samples of the input signal y (k) from the memory buffer (16); b) correlating the plurality of samples of the input signal with the regenerated user code to generate a first value of a channel delay profile energy DP (k); c) updating the read position of the input memory buffer 16 to read another plurality of samples of the input signal y (k); d) another plurality of samples of the input signal and the regenerated user code to generate another value of the channel delay profile energy DP (k + 1) stored in the profile accumulation memory 34; Correlating; e) repeating steps c) to d) to calculate all of the values of the channel delay profile. The method of claim 8, And storing each generated value of said channel delay profile energy (DP (l)) in a profile accumulation memory (34). Code generator circuit 52 for generating a regenerated user code; A memory buffer (50) for storing samples of the regenerated user code; An apparatus 64 for evaluating channel delay profile energy for calculating the time delays and amplitudes of each received multipath component of the input signal y (k) received at the receiver; A plurality of fingers 78; Spread spectrum comprising a finger assignment unit 76 for channel delay profile energy processing to select the strongest multipath elements in the input signal y (k) and to assign the selected elements to fingers 78 In a digital communication receiver, The apparatus 64 for evaluating the channel delay profile energy may include a first input 41 receiving the input signal y (k) and a plurality of samples of the regenerated user code in the memory buffer 50. The channel delay profile energy DP (l) by means of a correlating operation between the second input 43 and the plurality of samples of the regenerated user code and the second input 43 for sequentially reading at a memory location of A basic correlator 54 having an output for generating a value of In order to calculate a new value of the channel delay profile energy DP (l), the second correlator 43 of the basic correlator 54 is configured for each addressing operation corresponding to the new correlating operation. And a memory controller circuit (58) for addressing the memory buffer (50) to sequentially receive the memory location contents of the memory buffer (50). The method of claim 10, A spread spectrum digital communication receiver, characterized in that the values of the channel delay profile energy (DP (l)) are stored progressively in the profile accumulation memory (56). The method of claim 11, The memory controller circuit 58 addresses the profile accumulation memory 56 to perform a read operation of the basic correlator 54 from the memory buffer 50 and to perform a write operation to the profile accumulation memory 56. A spread spectrum digital communication receiver, characterized in that. The method of claim 12, The memory controller circuit 58 updates the addressing of the input memory buffer 50 and the profile accumulating memory 56 every NC (NC is an integral window size) chip to change the read and write positions of the basic correlator 54. A spread spectrum digital communication receiver, characterized in that. The method of claim 12, Spread spectrum digital communication, wherein addressing resumes periodically at the first location of the two memories 50, 56 when the final memory locations of the memory buffer 50 and the profile accumulation memory 56 arrive receiving set. The method of claim 12, And the basic correlator (54) is time multiplexed at a plurality of chip frequencies (Fc) between the memory buffer (50) and the plurality of memory locations of the profile accumulation memory (56). The method of claim 12, Wherein said delay profile energy DPacc (l) is obtained by accumulating the energies of several delay profiles DPi (l). Evaluation of channel delay profile energy of a spread spectrum digital communication receiver of a type comprising a memory buffer 50 storing samples of regenerated user code and a code generator circuit 52 for generating regenerated user code In the method, a) sequentially reading a first plurality of samples of the user code regenerated from the memory buffer 50; b) correlating the plurality of samples of the regenerated user code with the input signal y (k) to generate a first value of the channel delay profile energy DP (k); c) updating the read position of the input memory buffer 50 to read another plurality of samples of the regenerated user code; d) of the next plurality of samples of the regenerated user code and the input signal y (k) to generate another value of the channel delay profile energy DP (k + 1) stored in the profile accumulation memory 56; Correlating; e) repeating steps c) to d) to calculate a channel delay profile at all points. The method of claim 17, And storing each generated value of the channel delay profile energy (DP (l)) generated in the profile accumulation memory (56), respectively.