KR20050067571A - Fabricating method for capacitor in semiconductor device - Google Patents
Fabricating method for capacitor in semiconductor device Download PDFInfo
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- KR20050067571A KR20050067571A KR1020030098558A KR20030098558A KR20050067571A KR 20050067571 A KR20050067571 A KR 20050067571A KR 1020030098558 A KR1020030098558 A KR 1020030098558A KR 20030098558 A KR20030098558 A KR 20030098558A KR 20050067571 A KR20050067571 A KR 20050067571A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims abstract description 38
- 229910021193 La 2 O 3 Inorganic materials 0.000 claims abstract description 33
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 238000010030 laminating Methods 0.000 claims abstract description 3
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052741 iridium Inorganic materials 0.000 claims description 3
- 238000005121 nitriding Methods 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims 2
- HTXDPTMKBJXEOW-UHFFFAOYSA-N iridium(IV) oxide Inorganic materials O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 44
- 239000010409 thin film Substances 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000012495 reaction gas Substances 0.000 description 3
- 229910019899 RuO Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 반도체 소자의 캐패시터 형성방법에 관한 것으로, 원자층 증착법을 이용하여 누설전류 특성이 우수한 Al2O3 막과 유전율이 상대적으로 높은 La 2O3 막을 박막(laminate) 형태로 증착하여 신뢰성 높은 소자구현이 가능한 발명이다. 이를 위한 본 발명은, 기판 상에 하부전극을 형성하는 단계; 원자층 증착법을 이용하여 상기 하부전극 상에 일정두께의 Al2O3 막을 형성하는 단계와 일정두께의 La 2O3 막을 형성하는 단계를 번갈아 가며 수행하여, 라미네이트 Al2O3 - La2O 3 유전막을 형성하는 단계; 상기 라미네이트 Al2O3 - La2O3 유전막에 대한 열처리를 수행하는 단계; 및 상기 라미네이트 Al2O3 - La2O3 유전막 상에 상부전극을 형성하는 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor device, wherein an Al 2 O 3 film having excellent leakage current characteristics and a La 2 O 3 film having a relatively high dielectric constant are deposited in the form of a thin film by using atomic layer deposition. It is an invention capable of device implementation. The present invention for this purpose, forming a lower electrode on the substrate; Laminating Al 2 O 3 -La 2 O 3 by alternately forming a predetermined thickness of Al 2 O 3 film on the lower electrode by using an atomic layer deposition method and forming a La 2 O 3 film of a predetermined thickness Forming a dielectric film; Performing a heat treatment on the laminate Al 2 O 3 -La 2 O 3 dielectric film; And forming an upper electrode on the laminate Al 2 O 3 -La 2 O 3 dielectric layer.
Description
본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, ALD 법을 이용하여 누설전류 특성이 우수한 Al2O3 막과 유전율이 상대적으로 높은 La2 O3 막을 라미네이트(laminate) 형태로 형성하여 우수한 누설전류 특성을 얻음과 동시에 신뢰성 있는 소자제작이 가능한 발명이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, wherein an Al 2 O 3 film having excellent leakage current characteristics and a La 2 O 3 film having a relatively high dielectric constant are formed in a laminate form using an ALD method to provide excellent leakage current. It is an invention that can obtain a characteristic and manufacture a reliable device.
반도체 기억 소자들 중 DRAM(Dynamic Random Access Memory)의 집적도가 증가함에 따라 기억정보의 기본 단위인 1비트를 기억시키는 메모리 셀의 면적이 점차 작아지고 있다. 그런데 셀의 축소에 비례하여 캐패시터의 면적을 감소시킬 수는 없는 바, 이는 소프트 에러(Soft Error)를 방지하고 안정된 동작을 유지하기 위해서 단위 셀당 일정 이상의 충전용량이 필요하기 때문이다.As the degree of integration of DRAM (Dynamic Random Access Memory) among semiconductor memory devices increases, the area of a memory cell storing one bit, which is a basic unit of memory information, is gradually decreasing. However, it is not possible to reduce the area of the capacitor in proportion to the shrinking of the cell, because a certain charging capacity per unit cell is required to prevent soft errors and maintain stable operation.
따라서, 제한된 셀 면적내에 메모리 캐패시터의 용량을 적정값 이상으로 유지시키기 위한 연구가 요구되고 있으며, 이는 대개 3가지 방법으로 나뉘어 진행되어 왔다. 즉, 유전막의 두께 감소, 캐패시터의 유효면적의 증가, 비유전율이 높은 재료의 사용 등이 고려되어 왔다.Therefore, research is required to maintain the capacity of the memory capacitor in a limited cell area above an appropriate value, which has been generally divided into three methods. That is, reduction in the thickness of the dielectric film, increase in the effective area of the capacitor, use of a material having a high dielectric constant, and the like have been considered.
이중에서 세번째의 경우에 대하여 구체적으로 살펴보면 다음과 같다. 종래 캐패시터에 이용되는 유전막은 SiO2 로 부터, 유전률이 SiO2 의 거의 2배인 Si 3N4를 사용한 NO(Nitride-Oxide) 또는 ONO(Oxide-Nitride-Oxide) 박막이 주류였다.The third case in detail is as follows. Dielectric layer used in the conventional capacitor is SiO 2 with from, dielectric constant of NO with almost double the Si 3 N 4 on SiO 2 (Nitride-Oxide), or ONO (Oxide-Nitride-Oxide) thin film was the mainstream.
하지만 SiO2, NO(Nitride-Oxide), ONO(Oxide-Nitride-Oxide) 박막 등은 물질자체의 유전률이 작으므로 유전막의 두께를 줄이거나 표면적을 넓힌다고 해도 높은 정전용량을 구현할 만한 여지가 없게 되어 새로운 물질을 도입할 수 밖에 없는 상황에 이르렀다. 결국 고집적 DRAM에서는 기존 유전막을 대신할 물질로서 HfO2, SiON, Al2O3, SrTiO3 등의 유전막을 도입하였다.However, since SiO 2 , NO (Nitride-Oxide), and ONO (Oxide-Nitride-Oxide) thin films have small dielectric constants, there is no room for high capacitance even if the thickness of the dielectric film is reduced or the surface area is increased. There is no choice but to introduce new materials. As a result, dielectric films such as HfO 2 , SiON, Al 2 O 3 , and SrTiO 3 have been introduced in the highly integrated DRAM as a material to replace the existing dielectric film.
현재 캐패시터의 유전막으로 사용되고 있는 Al2O3 및 HfO2 계 유전막에서, Al2O3 막은 그 유전율이 낮기 때문에 디바이스에 계속해서 적용되기에는 한계에 도달하였다.In Al 2 O 3 and HfO 2 based dielectric films that are currently used as dielectric films for capacitors, Al 2 O 3 films have reached a limit to continue to be applied to devices because of their low permittivity.
또한, HfO2 유전막의 경우, 단독으로 사용될 경우에는 낮은 온도에서 결정화가 일어나는 관계로 누설전류 특성이 매우 취약한 단점을 가지고 있다. HfO2 유전막의 경우, 이와같은 점을 보완하기 위하여 Al2O3 와 라미네이트 형태로 유전막을 형성하여 사용하고 있다.In addition, the HfO 2 dielectric film has a disadvantage in that leakage current characteristics are very weak because crystallization occurs at a low temperature when used alone. In the case of the HfO 2 dielectric film, a dielectric film is formed in a laminate form with Al 2 O 3 to compensate for this.
그러나, 원하는 누설전류 특성을 확보하기 위해서는 Al2O3 와 HfO2 의 라미네이트 형태에서, Al2O3 가 차지하는 비율이 높아야 하며, 이로 인해 전체적인 유전율이 낮아져서 이 방법 또한 한계에 도달하고 있다.However, in order to secure desired leakage current characteristics, Al 2 O 3 in the form of a laminate of Al 2 O 3 and HfO 2 must be high, which lowers the overall dielectric constant and this method has also reached its limit.
본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, Al2O3 와 La2 O3 유전막을 라미네이트 형태로 사용하여 누설전류 특성과 유전특성을 동시에 향상시킨 반도체 소자의 캐패시터 제조방법을 제공함을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and provides a method for manufacturing a capacitor of a semiconductor device which improves leakage current characteristics and dielectric characteristics simultaneously by using an Al 2 O 3 and La 2 O 3 dielectric film in a laminate form. The purpose.
상기한 목적을 달성하기 위한 본 발명은, 기판 상에 하부전극을 형성하는 단계; 원자층 증착법을 이용하여 상기 하부전극 상에 일정두께의 Al2O3 막을 형성하는 단계와 일정두께의 La2O3 막을 형성하는 단계를 번갈아 가며 수행하여, 라미네이트 Al2O3 - La2O3 유전막을 형성하는 단계; 상기 라미네이트 Al 2O3 - La2O3 유전막에 대한 열처리를 수행하는 단계; 및 상기 라미네이트 Al2O3 - La2O3 유전막 상에 상부전극을 형성하는 단계를 포함하여 이루어진다.The present invention for achieving the above object, forming a lower electrode on the substrate; Laminating Al 2 O 3 -La 2 O 3 by alternately forming a predetermined thickness of Al 2 O 3 film on the lower electrode by using an atomic layer deposition method and forming a La 2 O 3 film of a predetermined thickness Forming a dielectric film; Performing a heat treatment on the laminate Al 2 O 3 -La 2 O 3 dielectric film; And forming an upper electrode on the laminate Al 2 O 3 -La 2 O 3 dielectric layer.
La2O3 는 유전율이 HfO2 와 비슷하면서도, 실리콘과 접촉시 우수한 계면특성을 보이는 장점을 가지고 있으며 또한, 실리콘 밴드갭 에너지로 부터 높은 오프셋을 나타내기 때문에 HfO2 에 비해 누설전류 측면에서 월등히 우수한 장점을 가지고 있다.La 2 O 3 has the advantage of showing excellent interfacial properties when it is in contact with silicon while having a dielectric constant similar to that of HfO 2 , and also excellent in leakage current compared to HfO 2 due to its high offset from silicon bandgap energy. It has advantages
따라서, 본 발명에서는 원자층 증착법(Atomic Layer Deposition : ALD)을 이용하여 Al2O3 와 La2O3를 라미네이트 형태로 형성함으로써, 더욱 얇은 두께에서도 누설전류 특성이 확보될 수 있을 것으로 판단되며, 이는 곧 낮은 TOX 값을 얻을 수 있게 됨을 의미한다.Therefore, in the present invention, by forming Al 2 O 3 and La 2 O 3 in a laminate form using atomic layer deposition (ALD), it is determined that leakage current characteristics can be secured even at a thinner thickness. This means that a lower T OX value can be obtained.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.
도1a 내지 도1d는 본 발명의 일실시예에 따른 캐패시터 제조공정을 도시한 공정단면로서 이를 참조하여 본 발명을 설명하면 다음과 같다.1A to 1D are cross-sectional views illustrating a capacitor manufacturing process according to an embodiment of the present invention.
먼저, 반도체 기판(10) 상에 폴리실리콘 하부전극(11)을 형성한다. 일단, 본 발명은 SIS(Silicon Insulator Silicon) 구조, MIS (Metal Insulator Silicon) 구조, MIM(Metal Insulator Metal) 구조의 캐패시터에 모두 적용될 수 있으므로, 하부전극(11)으로는 도핑된 폴리실리콘 이외에도 Pt, Ru, Ir, RuO2, IrO2, TiN 또는 WN 등이 사용될 수 있다.First, the polysilicon lower electrode 11 is formed on the semiconductor substrate 10. First, since the present invention can be applied to all capacitors of a silicon insulator silicon (SIS) structure, a metal insulator silicon (MIS) structure, and a metal insulator metal (MIM) structure, the lower electrode 11 is formed of Pt, Ru, Ir, RuO 2, IrO 2, TiN, or WN may be used.
이와같이 폴리실리콘 하부전극(11)을 형성한 이후에, 도1b에 도시된 바와같이 후속 유전막 증착시 폴리실리콘 하부전극(11)의 계면이 산화되는 것을 방지하기 위하여, 폴리실리콘 하부전극(11)의 표면을 질화처리한다.After the polysilicon lower electrode 11 is formed as described above, in order to prevent the interface of the polysilicon lower electrode 11 from being oxidized during subsequent deposition of the dielectric film as shown in FIG. 1B, the polysilicon lower electrode 11 may be formed. Nitriding the surface.
상기 질화처리는 NH3 를 사용하며, 800 ∼ 1200℃ 에서 10 ∼ 120 초 동안 실시되어, 폴리실리콘 하부전극(11)의 표면에 얇은 두께의 SiN 막(12)을 형성한다.The nitriding treatment uses NH 3 , and is performed at 800 to 1200 ° C. for 10 to 120 seconds to form a thin SiN film 12 on the surface of the polysilicon lower electrode 11.
다음으로 유전막을 증착하는 공정이 수행되며, 이를 도1c를 참조하여 설명한다. Next, a process of depositing a dielectric film is performed, which will be described with reference to FIG. 1C.
본 발명에서는 상대적으로 저유전율을 갖지만 누설전류 특성이 우수한 Al2O3 막(13)과 고유전율을 갖고 있으며, HfO2에 비해 누설전류 특성이 우수한 La2O 3 막(14)을, 원자층 증착법을 이용하여 일정두께로 번갈아 가며 증착하여 라미네이트 형태의 유전막(15)을 형성한다.In the present invention, an Al 2 O 3 film 13 having a relatively low dielectric constant but excellent leakage current characteristics and a La 2 O 3 film 14 having a high dielectric constant and superior leakage current characteristics as compared to HfO 2 are obtained. By depositing alternately by a predetermined thickness using a deposition method to form a dielectric film 15 of the laminate form.
이때, Al2O3 막(13) 및 La2O3 막(14)이 증착되는 순서는 뒤바뀌어도 상관이 없으며, 각각의 레이어들은 5 ∼ 20Å 정도의 두께를 갖게 형성된다.At this time, the order in which the Al 2 O 3 film 13 and the La 2 O 3 film 14 are deposited may be reversed, and each layer is formed to have a thickness of about 5 to about 20 microseconds.
원자층 증착법을 이용하여 Al2O3 막(13)을 5 ∼ 20Å 정도 형성하는 경우, 알루미늄 소스로는 TMA(Tri Methyl Aluminum)를 사용하며, 반응가스로는 O3 또는 H2O 증기를 이용한다. 또한, 기판온도는 250 ∼ 450 ℃ 로 한다.In the case of forming the Al 2 O 3 film 13 by 5 to 20 kPa by atomic layer deposition, TMA (Tri Methyl Aluminum) is used as the aluminum source, and O 3 or H 2 O vapor is used as the reaction gas. In addition, board | substrate temperature shall be 250-450 degreeC.
그리고, 원자층 증착법을 이용하여 La2O3 막(14)을 5 ∼ 20Å 정도 형성하는 경우, 란탄 소스로는 La(iPrAMD)3 또는 La(THD)3 를 사용하며, 반응가스로는 반응가스로는 O3 또는 H2O 증기를 이용한다. 또한, 기판온도는 250 ∼ 450 ℃ 로 한다.In the case of forming the La 2 O 3 film 14 by about 5 to 20 kPa by atomic layer deposition, La (iPrAMD) 3 or La (THD) 3 is used as the lanthanum source, and the reaction gas is used as the reaction gas. Use O 3 or H 2 O steam. In addition, board | substrate temperature shall be 250-450 degreeC.
그리고 도1c에 도시된, Al2O3 막(13)과 La2O3 막(14)이 일정두께로 번갈아 가며 증착하여 라미네이트 형태의 유전막(15)의 총 두께는 25 ∼ 200Å 정도로 한다.In addition, the Al 2 O 3 film 13 and the La 2 O 3 film 14 shown in FIG. 1C are alternately deposited at a predetermined thickness so that the total thickness of the laminated dielectric film 15 is about 25 to 200 micrometers.
이하에서는 Al2O3 막(13)과 La2O3 막(14)이 일정두께로 번갈아 가며 증착하여 라미네이트 형태의 유전막(15)을 라미네이트 Al2O3 - La2O3 유전막이라 칭하기로 한다.Hereinafter, the Al 2 O 3 film 13 and the La 2 O 3 film 14 are alternately deposited to have a predetermined thickness, and the laminate dielectric film 15 will be referred to as a laminate Al 2 O 3 -La 2 O 3 dielectric film. .
이와같이 라미네이트 Al2O3 - La2O3 유전막(15)을 형성한 다음, 라미네이트 Al2O3 - La2O3 유전막의 치밀화를 위하여 어닐공정을 실시한다. 이러한 어닐공정은 N2 분위기에서 급속열처리(RTP) 공정을 이용하여 진행되며, 500 ∼ 800℃ 의 온도에서 30 ∼ 120 초 동안 진행된다.Thus, after forming the laminated Al 2 O 3 -La 2 O 3 dielectric film 15, the annealing process is performed to densify the laminated Al 2 O 3 -La 2 O 3 dielectric film. This annealing process is carried out using a rapid heat treatment (RTP) process in an N 2 atmosphere, and proceeds for 30 to 120 seconds at a temperature of 500 ~ 800 ℃.
다음으로 도1d에 도시된 바와같이 상기 하부전극 상에 상부전극(16)을 형성한다. 상부전극(16)으로는 n형으로 도핑된 폴리실리콘 또는 Pt, Ru, Ir, RuO2, IrO2, TiN 또는 WN 등이 사용될 수 있다. Next, as shown in FIG. 1D, an upper electrode 16 is formed on the lower electrode. As the upper electrode 16, n-type doped polysilicon or Pt, Ru, Ir, RuO 2, IrO 2, TiN, or WN may be used.
이상과 같은 본 발명은 0.1㎛ 급 이하의 디바이스에서 실린더 구조 또는 콘캐이브 구조와 같이 3차원 구조를 갖는 캐패시터에 적용가능하며, 전술한 바와같이 SIS, MIS, MIM 구조의 캐패시터에 모두 적용가능하다. The present invention as described above is applicable to a capacitor having a three-dimensional structure, such as a cylinder structure or a concave structure in a device of class 0.1㎛ or less, as described above can be applied to all capacitors of SIS, MIS, MIM structure.
본 발명을 적용하게 되면, 상대적으로 얇은 두께에서 우수한 누설전류 특성을 확보할 수 있으며, 또한 높은 캐패시턴스를 얻을 수 있어 100nm 이하의 디바이스에서 활용도가 높은 장점이 있다. When the present invention is applied, excellent leakage current characteristics can be secured at a relatively thin thickness, and high capacitance can be obtained, so that there is an advantage of high utilization in devices of 100 nm or less.
이상에서 설명한 바와 같이 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명이 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다. As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in Esau.
본 발명을 적용하게 되면, 상대적으로 얇은 두께에서 우수한 누설전류 특성을 확보할 수 있으며, 또한 높은 캐패시턴스를 얻을 수 있어 100nm 이하의 디바이스에서 활용도가 높은 장점이 있다. When the present invention is applied, excellent leakage current characteristics can be secured at a relatively thin thickness, and high capacitance can be obtained, so that there is an advantage of high utilization in devices of 100 nm or less.
도1a 내지 도1d는 본 발명의 일실시예에 따른 캐패시터 제조공정을 도시한 도면. 1A to 1D are diagrams illustrating a capacitor manufacturing process according to an embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10 : 기판10: substrate
11 : 하부전극11: lower electrode
12 ; 실리콘질화막12; Silicon nitride film
13 : Al2O3 13: Al 2 O 3
14 : La2O3 14: La 2 O 3
15 : 라미네이트 유전막15: laminate dielectric film
16 : 상부전극 16: upper electrode
Claims (9)
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| KR1020030098558A KR20050067571A (en) | 2003-12-29 | 2003-12-29 | Fabricating method for capacitor in semiconductor device |
| US10/880,372 US7102875B2 (en) | 2003-12-29 | 2004-06-30 | Capacitor with aluminum oxide and lanthanum oxide containing dielectric structure and fabrication method thereof |
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