KR20050055432A - Method for informing gate of semiconductor device - Google Patents
Method for informing gate of semiconductor device Download PDFInfo
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- KR20050055432A KR20050055432A KR1020030088641A KR20030088641A KR20050055432A KR 20050055432 A KR20050055432 A KR 20050055432A KR 1020030088641 A KR1020030088641 A KR 1020030088641A KR 20030088641 A KR20030088641 A KR 20030088641A KR 20050055432 A KR20050055432 A KR 20050055432A
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 229920005591 polysilicon Polymers 0.000 claims abstract description 24
- 229920000642 polymer Polymers 0.000 claims abstract description 23
- 238000009616 inductively coupled plasma Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
- H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0135—Manufacturing their gate conductors
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Abstract
본 발명은 반도체 소자의 게이트 형성방법을 개시한다. 개시된 본 발명은, 게이트 산화막과 게이트도전막용 폴리실리콘막이 차례로 형성된 실리콘 기판을 제공하는 단계와, 상기 폴리실리콘막 상에 게이트 형성 영역을 한정하는 레지스트 패턴을 형성하는 단계와, 상기 레지스트 패턴을 이용해서 상기 폴리실리콘막을 식각하는 단계를 포함하는 반도체 소자의 게이트 형성방법에 있어서, 상기 폴리실리콘막을 식각하는 단계는 식각된 폴리실리콘막 측벽에의 폴리머 발생량이 극소회도록 Cl2와 SF6 및 N2의 혼합 가스를 이용한 TCP(Transformer Coupled Plasma) 방식으로 수행하는 것을 특징으로 한다. 본 발명에 따르면, 게이트 식각시 Cl2와 SF6 및 N2의 혼합 가스를 사용함으로써 폴리머의 양을 줄일 수 있으며, 버티컬한 프로파일을 갖는 게이트 전극을 형성하여 후속 공정의 단순화를 얻을 수 있다. 또한, 게이트 전극이 버티컬한 프로파일을 갖게 됨으로 인해 콘택 형성시 공정 상의 마진을 확보할 수 있다.The present invention discloses a method for forming a gate of a semiconductor device. According to an aspect of the present invention, there is provided a silicon substrate in which a gate oxide film and a polysilicon film for a gate conductive film are sequentially formed, forming a resist pattern defining a gate formation region on the polysilicon film, and using the resist pattern. In the method of forming a gate of a semiconductor device comprising etching the polysilicon film, the etching of the polysilicon film is a mixed gas of Cl2, SF6 and N2 to minimize the amount of polymer generated on the sidewall of the etched polysilicon film Characterized in that performed by the TCP (Transformer Coupled Plasma) method. According to the present invention, the amount of polymer can be reduced by using a mixed gas of Cl2, SF6, and N2 in the gate etching, and a simplification of the subsequent process can be obtained by forming a gate electrode having a vertical profile. In addition, since the gate electrode has a vertical profile, a process margin may be secured during contact formation.
Description
본 발명은 반도체 소자의 게이트 형성방법에 관한 것으로, 보다 상세하게는, 게이트 식각시 발생하는 폴리머(Polymer)를 제거하여 소자의 특성을 개선할 수 있는 반도체 소자의 게이트 형성방법에 관한 것이다.The present invention relates to a method of forming a gate of a semiconductor device, and more particularly, to a method of forming a gate of a semiconductor device that can improve the characteristics of the device by removing the polymer (Polymer) generated during the gate etching.
최근, 고전압 로직(High Voltage Logic) 제품에 있어서 고전압 영역의 게이트 패턴은 밀도가 극도로 작다. 이렇게 패턴의 밀도가 작은 게이트 식각시 TCP(Transformer Coupled Plasma) 장비를 사용하게 되며, 이때에 Cl2 가스를 단독으로 사용하거나 상황에 따라 산화막의 식각 선택비를 향상시키기 위해 O2 가스를 추가하거나 또는 질산화막의 형성을 위해 소량의 N2 가스를 첨가하여 사용하고 있다.Recently, in high voltage logic products, the gate pattern of the high voltage region has an extremely low density. In this case, TCP (Transformer Coupled Plasma) equipment is used for the gate pattern with small density of pattern.In this case, O2 gas is added or Nitric oxide layer is added to improve the etching selectivity of the oxide layer by using Cl2 gas alone. In order to form a small amount of N2 gas is added and used.
한편, 게이트 패턴의 밀도가 극도로 작아짐으로 인해 게이트 식각시 실리콘(Si)량도 다량으로 식각되어 포토 레지스트(5)와 실리콘의 결합으로 인해 도 1a에 도시된 바와 같이, 폴리실리콘막(3)의 양측벽에 다량의 폴리머(Polymer : A)가 발생하게 된다. 이로 인해 게이트의 프로파일(Profile)이 극도로 완만해지며, 게이트 패턴의 임계치수(Critical Dimension)를 매우 작게 해야함은 물론 스페이서 산화막이 제대로 형성되지 않는다.On the other hand, due to the extremely small density of the gate pattern, the amount of silicon (Si) is also etched in a large amount during the gate etching, and as shown in FIG. 1A due to the combination of the photoresist 5 and silicon, the polysilicon film 3 A large amount of polymer (Polymer: A) is generated on both side walls of the. As a result, the profile of the gate is extremely smooth, the critical dimension of the gate pattern must be made very small, and the spacer oxide layer is not properly formed.
상기와 같이, 스페이서 산화막이 제대로 형성되지 않게 되면, 게이트 식각시 게이트 양측벽이 식각되어 게이트의 표면 및 소오스 및 드레인 영역의 표면에 금속 실리사이드막을 형성하는 후속 공정에서 게이트 측벽에 금속 실리사이드막이 형성되어 도 1b에 도시된 바와 같이, 기판(1)의 실리사이드막(7a)과 게이트 상의 실리사이드막(7b)이 브리지(Bridge : B) 되어 쇼트(Short)가 발생된다.As described above, when the spacer oxide layer is not formed properly, the metal silicide layer may be formed on the sidewalls of the gate in a subsequent process of forming the metal silicide layer on the surface of the gate and the surface of the source and drain regions by etching both sidewalls of the gate during the gate etching process. As shown in 1b, the silicide film 7a of the substrate 1 and the silicide film 7b on the gate are bridged to generate a short.
따라서, 게이트 패턴의 밀도가 작아짐으로 인해 게이트 식각시 폴리머가 다량으로 발생하게 되어 후속의 폴리머 제거 과정이 복잡해질 뿐만 아니라 기판의 실리사이드막과 게이트 상의 금속 실리사이드막이 쇼트되어 소자에 치명적인 영향을 주게 된다.Therefore, the density of the gate pattern is reduced, so that a large amount of polymer is generated during the gate etching, thereby complicating the subsequent polymer removal process and shortening the silicide layer of the substrate and the metal silicide layer on the gate, which has a fatal effect on the device.
또한, 종래의 식각 가스로는 폴리머를 제거하는데 한계가 있으므로, SiClx, SixCy와 같은 실리콘 계열의 폴리머를 제거할 수 있는 가스를 적용해야 한다.In addition, since the conventional etching gas has a limitation in removing the polymer, a gas capable of removing a silicon-based polymer such as SiClx and SixCy should be applied.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 게이트 식각시 발생하는 폴리머를 제거하여 소자의 특성을 개선할 수 있는 반도체 소자의 게이트 형성방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a gate of a semiconductor device capable of improving the characteristics of a device by removing a polymer generated during gate etching as a solution to the above problems.
상기 목적을 달성하기 위한 본 발명은, 게이트 산화막과 게이트도전막용 폴리실리콘막이 차례로 형성된 실리콘 기판을 제공하는 단계와, 상기 폴리실리콘막 상에 게이트 형성 영역을 한정하는 레지스트 패턴을 형성하는 단계와, 상기 레지스트 패턴을 이용해서 상기 폴리실리콘막을 식각하는 단계를 포함하는 반도체 소자의 게이트 형성방법에 있어서, 상기 폴리실리콘막을 식각하는 단계는 식각된 폴리실리콘막 측벽에의 폴리머 발생량이 극소회도록 Cl2와 SF6 및 N2의 혼합 가스를 이용한 TCP(Transformer Coupled Plasma) 방식으로 수행하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a silicon substrate in which a gate oxide film and a polysilicon film for a gate conductive film are sequentially formed, forming a resist pattern defining a gate formation region on the polysilicon film; In the method of forming a gate of a semiconductor device comprising etching the polysilicon film using a resist pattern, the etching of the polysilicon film is Cl2, SF6 and so that the amount of polymer generated on the sidewall of the etched polysilicon film is minimized Characterized in that performed by the TCP (Transformer Coupled Plasma) method using a mixed gas of N2.
여기에서, 상기 폴리실리콘막을 식각하는 단계는 구동전압을 550∼650W이고, 바이어스 전압은 45∼55W, 압력을 10∼205mTorr, 온도를 15∼25℃로 하면서 Cl2 가스량을 35∼45sccm, SF6 가스량을 3∼7sccm, N2 가스량을 3∼7sccm으로 하는 조건 하에서 30∼40초 동안 수행하는 것을 특징으로 한다. In the etching of the polysilicon film, the driving voltage is 550 to 650 W, the bias voltage is 45 to 55 W, the pressure is 10 to 205 mTorr, the temperature is 15 to 25 ° C, and the Cl2 gas amount is 35 to 45 sccm and the SF6 gas amount is used. It is characterized by performing for 30 to 40 seconds under the conditions of 3 to 7 sccm, the amount of N2 gas 3-7 sccm.
(실시예)(Example)
이하, 본 발명의 바람직한 실시예에 대해 첨부된 도면을 참조하여 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 설명하기 위한 공정별 단면도이다.2A through 2D are cross-sectional views illustrating processes of forming a gate of a semiconductor device in accordance with an embodiment of the present invention.
도 2a에 도시된 바와 같이, 액티브 영역을 한정하는 소자분리막들(미도시)이 구비된 실리콘 기판(21) 상에 게이트를 형성하기 위해 게이트 산화막(23)과 게이트 도전막용 폴리실리콘막(25)을 차례로 형성한 후에 폴리실리콘막(25) 상에 게이트 형성 영역을 한정하는 레지스트 패턴(27)을 형성한다.As shown in FIG. 2A, the gate oxide layer 23 and the polysilicon layer 25 for the gate conductive layer are formed to form a gate on the silicon substrate 21 having device isolation layers (not shown) defining an active region. After sequentially forming the resist pattern, a resist pattern 27 defining a gate formation region is formed on the polysilicon film 25.
그 다음, 도 2b에 도시된 바와 같이, 상기 레지스트 패턴(27)을 이용해서 폴리실리콘막(25)을 식각하여 게이트 전극(29)을 형성한다. 여기에서, 식각된 폴리실리콘막(25) 측벽에의 폴리머 발생량이 극소화되도록 CL2와 SF6 및 N2의 혼합 가스를 이용한 TCP(Transformer Coupled plasma) 방식으로 식각을 진행한다. 이때, TCP 방식의 공정 조건은 구동전압을 550∼650W이고, 바이어스 전압은 45∼55W, 압력을 10∼205mTorr, 온도를 15∼25℃로 하면서 Cl2 가스량을 35∼45sccm, SF6 가스량을 3∼7sccm, N2 가스량을 3∼7sccm으로 하는 조건 하에서 30∼40초 동안 수행한다.Next, as illustrated in FIG. 2B, the polysilicon layer 25 is etched using the resist pattern 27 to form the gate electrode 29. Here, etching is performed in a TCP (Transformer Coupled plasma) method using a mixed gas of CL2, SF6, and N2 so as to minimize the amount of polymer generated on the etched polysilicon film 25 sidewalls. At this time, the process conditions of the TCP method are the driving voltage of 550 to 650 W, the bias voltage of 45 to 55 W, the pressure of 10 to 205 mTorr, the temperature of 15 to 25 ° C, the Cl2 gas amount of 35 to 45 sccm, and the SF6 gas amount of 3 to 7 sccm. , N2 gas is carried out for 30 to 40 seconds under the condition of 3 to 7 sccm.
그리고, 폴리실리콘막(25)의 측벽에 폴리머가 발생하면서 동시에 SF6 가스의 화학적 반작용(Chemical Reation)에 의해 폴리머가 제거됨으로써 폴리머의 양이 작게 형성되고, 이로 인해 폴리머의 프로파일도 개선된다.As the polymer is generated on the sidewall of the polysilicon film 25 and the polymer is removed by chemical reaction of SF6 gas, the amount of the polymer is formed to be small, thereby improving the profile of the polymer.
이어서, 도 2c에 도시된 바와 같이, 포토 레지스트 스트립(Strip)을 통해 레지스트 패턴(27)을 제거한 후에 세정 공정을 실시한다. 계속해서, 상기 게이트 전극(29) 양측의 기판 표면에 이온을 주입하여 LDD 영역(31a, 31b)을 형성한다. Subsequently, as shown in FIG. 2C, a cleaning process is performed after removing the resist pattern 27 through the photo resist strip. Subsequently, ions are implanted into the surface of the substrate on both sides of the gate electrode 29 to form LDD regions 31a and 31b.
그 다음, 도 2d에 도시된 바와 같이, 상기 게이트 전극(29) 양측벽 및 기판(21) 상에 산화막(33)과 질화막(35)을 형성한 후에 식각을 진행하여 상기 게이트 전극(29) 양측벽에 스페이서(37)를 형성한다. Next, as shown in FIG. 2D, after the oxide film 33 and the nitride film 35 are formed on both sidewalls of the gate electrode 29 and the substrate 21, etching is performed to both sides of the gate electrode 29. The spacer 37 is formed in the wall.
상기와 같이, 본 발명은 폴리머를 발생시키는 종래의 게이트 식각 공정과 달리, 식각선택비가 높은 Cl2와 SF6 및 N2의 혼합 가스를 사용함으로써 게이트 식각시 발생하는 폴리머의 양을 줄일 수 있으며, 버티컬(Vertical)한 프로파일을 갖는 게이트 전극을 형성할 수 있다.As described above, the present invention, unlike the conventional gate etching process for generating a polymer, it is possible to reduce the amount of polymer generated during gate etching by using a mixed gas of Cl2, SF6 and N2 with a high etching selectivity, Vertical (Vertical A gate electrode having a profile can be formed.
또한, 게이트 식각시 발생하는 폴리머의 양을 줄임으로써 폴리머를 제거하는 후속 공정의 단순화를 얻을 수 있으며, 게이트 전극이 버티컬한 프로파일을 갖게 됨으로 인해 콘택 형성시 공정 상의 마진(Margine)을 확보할 수 있다.In addition, the subsequent process of removing the polymer can be simplified by reducing the amount of polymer generated during gate etching, and the margin of the process can be secured during contact formation because the gate electrode has a vertical profile. .
이상, 본 발명을 몇 가지 예를 들어 설명하였으나, 본 발명은 이에 한정되는 것은 아니며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 본 발명의 사상에서 벗어나지 않으면서 많은 수정과 변형을 가할 수 있음을 이해할 것이다.In the above, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and a person of ordinary skill in the art may make many modifications and variations without departing from the spirit of the present invention. I will understand.
이상에서와 같이, 본 발명은 게이트 식각시 SF 및 Cl2 가스를 혼합하여 사용함으로써 폴리머의 양을 줄일 수 있으며, 버티컬한 프로파일을 갖는 게이트 전극을 형성하여 후속 공정의 단순화를 얻을 수 있다. As described above, the present invention can reduce the amount of polymer by using a mixture of SF and Cl2 gas during the gate etching, and can simplify the subsequent process by forming a gate electrode having a vertical profile.
또한, 게이트 전극이 버티컬한 프로파일을 갖게 됨으로 인해 콘택 형성시 공정 상의 마진을 확보할 수 있다.In addition, since the gate electrode has a vertical profile, a process margin may be secured during contact formation.
도 1a 내지 도 1b는 종래 반도체 소자의 게이트 형성방법의 문제점을 설명하기 위한 공정 단면도.1A to 1B are cross-sectional views illustrating a problem of a method for forming a gate of a conventional semiconductor device.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 설명하기 위한 공정별 단면도.2A through 2D are cross-sectional views illustrating processes for forming a gate of a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
21 : 실리콘 기판 23 : 게이트 산화막21 silicon substrate 23 gate oxide film
25 : 폴리실리콘막 27 : 레지스트 패턴25 polysilicon film 27 resist pattern
29 : 게이트 전극 31a, 31b : LDD 영역29: gate electrode 31a, 31b: LDD region
33 : 산화막 35 : 질화막33: oxide film 35: nitride film
37 : 스페이서37: spacer
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