KR20050055217A - Method of manufacturing a nand flash device - Google Patents

Abstract

The present invention relates to a method for manufacturing a NAND flash device, and the present invention is to simultaneously form a source line plug and a drain contact plug, and then to drain the source metal contact and the bit line for contact with the metal landing pad on each top. The present invention provides a method of manufacturing a NAND flash device capable of reducing unnecessary process steps by forming a metal contact, and reducing defects caused by an overlay error occurring at the time of forming a contact because the contact is integrated.

Description

Method of manufacturing a NAND flash device

The present invention relates to a method for manufacturing a NAND flash device, and more particularly, to a method of forming a drain contact and a source contact of a NAND flash device.

Unlike general flash devices, a cell array of a NAND flash device operates by connecting a cell array with a string. Due to this characteristic, there are drain contacts and source line contacts for global ground connected to bit lines at both ends of the string, and these contacts are used for string control. It is connected to the junction of the select transistor.

1 is an array diagram of a conventional NAND flash device.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

1 and 2, the drain select transistor 30 and the source terminal of the cell string 20 are selected to select the cell string 20 and the drain terminal of the cell string 20 for storing electrical information. A first interlayer insulating film 12 is formed on the semiconductor substrate 10 on which the source select transistor 40 is formed.

After the photoresist is formed on the entire structure, a photolithography process using a mask is performed to form a photoresist pattern (not shown) that opens the source line region. An etching process using the photoresist pattern as an etching mask is performed to remove the first interlayer insulating layer 12 on the source region of the source select transistor 40 to form a source line contact hole. The photoresist pattern is formed through a strip process. After depositing a polysilicon film on the entire structure, the source line plug 14 is formed by filling the source line contact with polysilicon by chemical mechanical polishing using the first interlayer insulating film 12 as a stop film.

The second interlayer insulating film 16 is formed over the entire structure. A photosensitive film pattern (not shown) is formed on the entire structure to open the drain contact region. An etching process using the photoresist pattern as an etching mask is performed to remove the second and first interlayer insulating layers 12 and 16 on the drain region of the drain select transistor 30 to form a drain contact hole. After removing the photoresist pattern, a polysilicon film is deposited on the entire structure. The drain contact plug 18 is formed by filling the drain contact hole with polysilicon by performing chemical mechanical polishing using the second interlayer insulating film 18 as a stop film.

Subsequently, a predetermined region of the second interlayer insulating layer 18 on the source line plug is etched through the metal line forming process to form the source metal plug 52 and the metal landing pad 60 is formed thereon. In addition, the bit line 50 is connected to the drain contact plug 18 and formed to be orthogonal to the cell string 20 and the source line plug 14.

As described above, since the drain contact plug 18 and the source line plug 14 are formed by using independent processes, there is a problem that the overall number of masks and the number of process steps are increased, thereby lowering productivity. do. In addition, independent mask alignment of the contact plugs and the metal wirings is required, which causes difficulties in overlay control.

Therefore, in order to solve the above problems, the present invention simultaneously forms a source line contact and a drain contact and electrically connects each of them to the upper metal film through a metal wiring process, thereby preventing a decrease in yield due to simplification and misalignment. It provides a method for manufacturing a NAND flash device.

Providing a semiconductor substrate having a NAND flash cell and a drain select transistor for selecting a drain terminal of the cell and a source select transistor for selecting a source terminal for selecting a source terminal of the cell according to the present invention; Forming a first interlayer insulating film on the semiconductor substrate, patterning the first interlayer insulating film, and then filling the first interlayer insulating film with a conductive film to form a drain contact plug on the drain region of the drain selection transistor, Forming a source line plug on a source region, forming a second interlayer insulating film on the first interlayer insulating film, patterning the second interlayer insulating film, and then filling the metal layer with a metal film to planarize the drain contact A drain metal contact on the plug and a source on the source line plug Forming a bit line on the drain metal contact and forming a metal landing pad on the source metal contact by forming a metal contact and performing a metallization process.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

3 is an array diagram of a NAND flash device according to the present invention.

4A to 4C are cross-sectional views taken along line III-III 'of FIG. 3 for explaining a method of manufacturing a NAND flash device according to the present invention.

3 and 4A, a drain select transistor 130 for selecting a NAND flash cell 120 and a drain terminal of the cell 120, and a source selector for selecting a source terminal for selecting a source terminal of the cell The first interlayer insulating layer 116 is formed on the semiconductor substrate 110 on which the transistor 140 is formed. The first interlayer insulating layer 116 is preferably formed in a structure in which a flash cell 120 and an oxide film 112 for protecting a transistor and a dielectric material film 114 for insulating between layers are stacked.

The formation of the NAND flash cell 120 and the drain and source selection transistors 130 and 140 may be performed by screen oxide films (not shown) that suppress crystal defects on the surface of the substrate on the semiconductor substrate 110 or serve as buffer layers for surface treatment and ion implantation. It is preferable to form an ion layer (not shown) for the well and the threshold voltage control by depositing ion) and then ion implantation. After removing the screen oxide film, a tunnel oxide film (not shown), a first conductive film (not shown), and a pad nitride film (not shown) are deposited.

After the photoresist is coated on the pad nitride layer, a photolithography process using a photoresist mask is performed to form a photoresist pattern (not shown). An etching process using the photoresist pattern as an etching mask may be performed to etch the pad nitride film, the first conductive film, the tunnel oxide film, and the semiconductor substrate to form the trench 18 having an STI structure. A high density plasma (HDP) oxide film is deposited on the entire structure to fill the trench. It is preferable to form the device isolation film 111 by performing a planarization process using the pad nitride film as a stop layer to remove the HDP oxide film on the pad nitride film.

The pad nitride layer may be formed to protrude a portion of the device isolation layer 111 by performing a nitride strip process using a phosphate dip out (H ₃ PO ₄ dip out). A pretreatment cleaning process using DHF is performed to remove the native oxide film and residues formed on the first conductive film. A second conductive film (not shown) is deposited on the entire structure, and then a portion of the second conductive film is patterned to form a floating gate electrode.

A dielectric film (not shown) is deposited along the step of the entire structure, and a third conductive film (not shown), a tungsten silicide film (WSi _x ), and a hard mask film (not shown) are sequentially formed to form a control gate. do. As the dielectric film, it is preferable to form a dielectric film having an ONO (SiO ₂ -Si ₃ N ₄ -SiO ₂ ) structure. It is preferable to form a control gate electrode by performing a gate mask and etching process and a self aligned mask and etching process. As a result, the gate electrode for the flash cell and the gate electrode for the transistor are formed. Thereafter, it is preferable to perform an ion implantation process to form a source / drain. In order to protect the gate electrodes formed above, it is effective to form an oxide film along the step on the entire structure. A dielectric material film for interlayer insulation is formed sequentially.

3 and 4B, through the patterning process, the first interlayer insulating layer 116 on the source and the drain is removed to form a source line contact and a drain contact, and then the contact holes are filled with a conductive film. The source line plug 142 and the drain contact plug 132 are formed.

It is preferable to form a photoresist pattern (not shown) which opens the source line region and the drain region by applying a photoresist layer on the first interlayer insulating layer 116 and performing a photolithography process using a photoresist mask. Since it is a NAND flash device, it is effective to open the source region and the drain region of the source select transistor 140 and the drain select transistor 130. The photoresist mask may be a mask in which a drain contact mask and a source line contact mask are mixed to form two contacts at the same time. It is preferable to form a source line contact hole and a drain contact hole by removing the first interlayer insulating layer 116 through an etching process using the photoresist pattern as an etching mask. The photoresist pattern is removed through a predetermined photoresist strip process.

After depositing a conductive film on the entire structure, a planarization process using the first interlayer insulating film 116 as a stop film is performed to remove the conductive film on the first interlayer insulating film 116 to thereby remove the source line plug 142 and the drain contact plug 132. Is preferably formed. The planarization process preferably uses surface etching or chemical mechanical polishing. Plug ion implantation may be carried out to maintain the characteristics of the cell junction before depositing the conductive film.

3 and 4C, the etch stop layer 118 and the second interlayer insulating layer 119 are sequentially formed. The second interlayer insulating layer 119 and the etch stop layer 118 on the source line plug 142 and the drain contact plug 132 are patterned to form a source metal contact hole and a drain metal contact hole. The source metal contact hole and the drain metal contact hole are buried and planarized with a metal film to form the source metal contact 144 and the drain metal contact 134. A metal wiring process is performed to form a metal landing pad 160 on the source metal contact 144 and a bit line 150 on the drain metal contact 134.

The etch stop layer 118 may be formed by using a nitride layer to protect the plug of the lower portion during the etching process for forming the metal contact hole and to serve as a stop layer of the etching process. As the second interlayer insulating film 119, it is preferable to use a dielectric material film for electrical insulation between the upper and lower structures. As the dielectric material film, a low dielectric constant film and an oxide film can be used.

The source metal contact 144 and the drain metal contact 134 may be formed by applying a photoresist film on the second interlayer insulating film 119, and then performing a photolithography process using a photoresist mask, thereby forming the source line plug 142 and the drain contact. It is preferable to form a photoresist pattern (not shown) that opens the upper portion of the plug 132. By performing an etching process using the photoresist pattern as an etching mask, the second interlayer insulating layer 119 is removed, and the exposed etch stop layer 118 is removed to form a source metal contact hole on the source line plug 142. The drain metal contact hole may be formed on the drain contact plug 132. A metal film is deposited on the entire structure to fill the source metal contact hole and the drain metal contact hole, and then a planarization process is performed to remove the metal film on the second interlayer insulating layer 119 to remove the source metal contact 144 and the drain metal contact 134. Is preferably formed.

Thus, while the source line plug is conventionally connected to the metal landing pad through the metal contact, and the drain contact plug is in contact with the bit line without a separate contact, the present invention provides a metal contact with the source line plug 142 and the drain contact plug ( 132, the metal contacts 134 and 144 may be formed on the upper surface of the metal contact pads 160 and the bit line 150, respectively. In this case, the source metal contact 144 and the drain metal contact 134 may be formed to be extended to the left and right as much as possible between the gate terminals of the select transistor as long as design rules allow. This is because the metal contact (source metal contact and drain metal contact) can be formed to the same size as the lower plug (source line plug and drain contact plug) to minimize the resistance between the two contacts. In the present invention, by precisely adjusting the excessive etching time of the etch stop film, it is possible to prevent the influence of the misalignment between the two layers.

The metal wiring process refers to a wiring process including a metal film deposition and patterning process or a wiring process using a damascene technique.

As described above, the present invention forms a source line plug and a drain contact plug at the same time, and then forms a source metal contact for contact with the metal landing pad and a drain metal contact for contact with the bit line on each of the unnecessary process steps. Can be reduced.

In addition, since the integrated contact proceeds, the occurrence of defects due to the overlay error occurring at the time of contact formation can be reduced.

1 is an array diagram of a conventional NAND flash device.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

3 is an array diagram of a NAND flash device according to the present invention.

4A to 4C are cross-sectional views taken along line III-III 'of FIG. 3 for explaining a method of manufacturing a NAND flash device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 110: semiconductor substrate 11, 111: device isolation film

12, 16, 116, 119: interlayer insulating film 14, 142: source line plug

18, 132: drain contact plug 20, 120: cell

30, 130: drain select transistor 40, 140: source select transistor

50, 150: bit line 52, 144: source metal contact

60, 160: metal landing pad 112: oxide film

114: dielectric material film 118: etch stop film

134: Drain Metal Contact

Claims (3)

Providing a semiconductor substrate having a drain select transistor for selecting a NAND flash cell and a drain terminal of the cell and a source select transistor for selecting a source terminal for selecting a source terminal of the cell; Forming a first interlayer insulating film on the semiconductor substrate; Patterning the first interlayer insulating film, and then filling the planarity with a conductive film to form a drain contact plug on a drain region of the drain select transistor and a source line plug on a source region of the source select transistor; Forming a second interlayer insulating film on the first interlayer insulating film; Patterning the second interlayer insulating film, and then filling the buried planarity with a metal film to form a drain metal contact on the drain contact plug and a source metal contact on the source line plug; And Forming a bit line on the drain metal contact and forming a metal landing pad on the source metal contact. The method of claim 1, wherein before the second interlayer insulating film forming process, And forming an etch stop layer to reduce alignment errors of the drain and source metal contacts. The method of claim 1, And forming the drain contact plug and the drain metal contact in the same size, and forming the drain contact plug and the drain metal contact in the same size.