KR20050053255A - Phase-changable memory device and method of forming the same - Google Patents

Abstract

Disclosed are a phase change memory device and a method of forming the same, which can minimize an operation error. This phase change memory element is formed as follows. First, a plurality of lower electrode contacts electrically connected to the semiconductor substrate are formed through the interlayer insulating layer on the semiconductor substrate. A plurality of lower electrodes overlapping the plurality of lower electrode contacts are formed on the interlayer insulating layer. A phase conversion film, an upper electrode film, and an insulating film are sequentially stacked on the semiconductor substrate on which the lower electrodes are formed. Anisotropic etching is performed to etch the insulating film, the upper low electrode film, and the phase change element film to expose the interlayer insulating film between the lower electrodes. In this case, the phase conversion film, the upper electrode film and the insulating film are thickly stacked on the lower electrode, and thinly stacked on the sidewall of the lower electrode. The front anisotropic etching is performed such that the top and side surfaces of the lower electrodes are covered by at least the phase change film and the upper electrode film.

Description

Phase-changable memory device and method of forming the same

The present invention relates to a nonvolatile memory device and a method of forming the same, and more particularly to a phase change memory device and a method of forming the same.

Nonvolatile memory devices have a feature that data stored therein is not destroyed even if their power supply is cut off. Such nonvolatile memory devices mainly employ flash memory cells having a stacked gate structure. The stacked gate structure includes a tunnel oxide layer, a floating gate, an inter-gate dielectric layer, and a control gate electrode sequentially stacked on a channel. Therefore, in order to improve the reliability and program efficiency of the flash memory cells, the film quality of the tunnel oxide film should be improved and the coupling ratio of the cells should be increased.

Instead of the flash memory devices, new nonvolatile memory devices such as phase change memory devices have recently been proposed. The phase change memory devices may execute a program, a read, etc. using the resistance difference according to the phase change.

1 and 2 sequentially illustrate a method of forming a phase change memory device according to the prior art.

Referring to FIG. 1, a lower electrode contact 5 is formed on the semiconductor substrate 1 to penetrate the interlayer insulating layer 3 and electrically contact the semiconductor substrate 1. A phase conversion film 7, an upper electrode film 9, and an insulating film 11 are sequentially stacked on the interlayer insulating film 3 including the lower electrode contact 5. The phase change film 7 is formed of Ge _X Sb _Y Te _Z.

Referring to FIG. 2, the insulating film 11, the upper electrode film 9, and the interlayer insulating film 3 are sequentially etched to expose the interlayer insulating film 3. In this case, etching damage may occur on the side surface E of the phase conversion layer 7 in the etching process, resulting in nonuniformity of resistance of the phase conversion layer 7. This may cause an operation error in the subsequent operation of the phase change memory element.

In order to solve the above problems, the technical problem of the present invention is to provide a phase change memory device and a method of forming the same that can minimize the operation error.

According to an aspect of the present invention, there is provided a phase change memory device including: a plurality of lower electrode contacts electrically connected to the semiconductor substrate through an interlayer insulating layer on the semiconductor substrate; A plurality of lower electrodes respectively overlapping the plurality of lower electrode contacts on the interlayer insulating layer; A phase conversion layer covering upper and side surfaces of the lower electrode; The upper electrode layer and the insulating layer on the upper electrode layer are sequentially stacked on the phase change layer, the ends of which are aligned with the ends of the phase change layer. At this time, the phase conversion film is characterized in that the thickness of the upper portion of the lower electrode than the side of the lower electrode.

In the phase change memory device, the lower electrode and the upper electrode film are preferably titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), iridium (Ir), platinum (Pt), or osmium. And at least one metal selected from the group consisting of (Os), ruthenium (Ru), rhodium (Rh) and palladium (Pd) or a nitride film of the metal. The phase conversion film is preferably made of Ge _X Sb _Y Te _Z. The insulating film is preferably made of plasma enhanced tetraethyl orthosilicate (Si (OC ₂ H ₅ ) ₄ ).

A method of forming a phase change memory device according to the present invention for achieving the above technical problem is as follows. First, a plurality of lower electrode contacts electrically connected to the semiconductor substrate are formed through the interlayer insulating layer on the semiconductor substrate. A plurality of lower electrodes overlapping the plurality of lower electrode contacts are formed on the interlayer insulating layer. A phase conversion film, an upper electrode film, and an insulating film are sequentially stacked on the semiconductor substrate on which the lower electrodes are formed. Anisotropic etching is performed to etch the insulating film, the upper low electrode film, and the phase change element film to expose the interlayer insulating film between the lower electrodes. In this case, the phase conversion film, the upper electrode film and the insulating film are thickly stacked on the lower electrode, and thinly stacked on the sidewall of the lower electrode. The front anisotropic etching is performed such that the top and side surfaces of the lower electrodes are covered by at least the phase change film and the upper electrode film.

In this method, the front anisotropic etching is preferably performed using a gas containing carbon tetrachloride (CF ₄ ), chlorine (Cl ₂ ) and argon (Ar). At least the phase change film and the insulating film are preferably formed by a physical vapor deposition process.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout.

3 is a cross-sectional view of a phase change memory device according to an embodiment of the present invention.

Referring to FIG. 3, an interlayer insulating layer 22 is disposed on the semiconductor substrate 20. The interlayer insulating layer 22 may be formed of a hydrogen silsesquioxane (HSQ), boron phosphorus silicate glss (BPSG), high density plasma (HDP) oxide, plasma enhanced tetraethyl orthosilicate (PETOS), undoped silicate glass (USG), and phosphorus silicalicate glss (PSG). , PE-SiH ₄ and Al ₂ O _{3 It} may be made of at least one material selected from the group containing. A plurality of lower electrode contacts 24 penetrating the interlayer insulating layer 22 and electrically connected to the semiconductor substrate 20 are disposed. The lower electrode contact 24 may be made of one material selected from the group consisting of tungsten, copper, aluminum, and polysilicon. A plurality of lower electrodes 26 overlapping the plurality of lower electrode contacts 24 are disposed on the interlayer insulating layer 22 having the lower electrode contacts 24. The lower electrode 26 has a thickness of, for example, 700 kPa. The lower electrode 26 includes titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), iridium (Ir), platinum (Pt), osmium (Os), ruthenium (Ru), and rhodium (Rh). ) And at least one metal selected from the group having palladium (Pd) or a nitride film of the metal.

3, the top and side surfaces of the lower electrode 26 are covered with the phase change film 28. The phase change film 28 is made of Ge _X Sb _Y Te _Z. For example, X and Y are 2 and Z is 5. The entire upper surface and some side surfaces of the phase change film 28 are covered with the upper electrode film 30. The upper electrode layer 30 may include titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), iridium (Ir), platinum (Pt), osmium (Os), ruthenium (Ru), and rhodium ( Rh) and at least one metal selected from the group consisting of palladium (Pd) or a nitride film of the metal. The entire upper surface and some side surfaces of the upper electrode film 30 are covered with the insulating film 32. The insulating layer 32 is made of plasma enhanced tetraethyl orthosilicate (Si (OC ₂ H ₅ ) ₄ ). End portions of the insulating layer 32 and the upper electrode layer 30 are aligned with the phase change layer 28.

In the phase change memory element of FIG. 3, the phase change film 28 has a thickness thicker on the upper surface of the lower electrode 26 than on the side of the lower electrode 26. The phase change film 28, in which the entire upper portion and some side surfaces of the phase change film 28 are covered with the upper electrode film 30, is actually exposed, is much smaller than in the related art. Therefore, compared with the related art, the degree of etching damage can be minimized, thereby reducing the operation error of the phase change memory device.

4 to 8 sequentially illustrate the method of forming the phase change memory device of FIG.

Referring to FIG. 4, an interlayer insulating film 22 is stacked on the semiconductor substrate 20. The interlayer insulating layer 22 may be formed by one method selected from among spin on glass, physical vapor deposition, and chemical vapor deposition. The interlayer insulating layer 22 may be formed of at least one material selected from the group consisting of HSQ, BPSG, HDP oxide, PETEOS, USG, PSG, PE-SiH ₄ and Al ₂ O ₃ . Although not illustrated, transistors including a gate electrode (not shown) and source / drain regions (not shown) may be formed in the semiconductor substrate 20 before the interlayer insulating layer 22 is stacked, and the interlayer insulating layer 22 may be formed. 22 may be formed to cover the transistors. The interlayer insulating layer is patterned to form a plurality of contact holes (not shown) exposing the source / drain regions. The plurality of contact holes are filled with a conductive material to form a lower electrode contact 24. The lower electrode contact 24 may be formed of one material selected from the group consisting of tungsten, copper, aluminum, and polysilicon. The lower electrode layer 26 is stacked on the interlayer insulating layer 22 including the lower electrode contact 24. The lower electrode layer 26 may be formed to have a thickness of, for example, 700 GPa. The lower electrode layer 26 may include titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), iridium (Ir), platinum (Pt), osmium (Os), ruthenium (Ru), and rhodium ( Rh) and palladium (Pd) may be formed of at least one metal selected from the group or a nitride film of the metal. Photoresist patterns PR are formed on the lower electrode layer 26 to overlap the lower electrode contacts 24, respectively.

Referring to FIG. 5, the lower electrode layer 26 is etched using the photoresist patterns PR as an etch mask to expose the interlayer insulating layer 22. In this case, a gas containing a halogen group element may be used as the etching gas. Accordingly, a plurality of lower electrodes 26 overlapping the lower electrode contacts 24 are formed. The plurality of lower electrodes 26 may be formed at, for example, 300 nm intervals.

Referring to FIG. 6, a phase conversion film 28 is stacked on an entire surface of the semiconductor substrate on which the lower electrode 26 is formed. The phase change film 28 is formed of Ge _X Sb _Y Te _Z , where, for example, X and Y are 2 and Z is 5. The phase change film 28 may be formed to have a thickness of 1000 kPa by, for example, physical vapor deposition (PVD) at a temperature of 200 ° C. In this case, the phase conversion film 28 is formed on the lower electrode 26 to have a thickness of 1000 Å, but on the sidewall of the lower electrode 26 and the interlayer insulating film 22, in particular, the lower electrodes 26. It is formed thinner than a thickness of 1000 Å on the sidewalls between and the interlayer insulating film 22.

Referring to FIG. 7, an upper electrode film 30 is stacked on the phase change film 28. The upper electrode film 30 may be formed to have a thickness of, for example, 700 Å. The upper electrode layer 30 may include titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), iridium (Ir), platinum (Pt), osmium (Os), ruthenium (Ru), and rhodium ( Rh) and palladium (Pd) may be formed of at least one metal selected from the group or a nitride film of the metal. The upper electrode film 30 may be formed by, for example, chemical vapor deposition (CVD) at a temperature of 150 ° C. The upper electrode film 30 may also be formed thinner than the lower electrode 26 between the lower electrodes 26.

Referring to FIG. 8, an insulating film 32 is stacked on the upper electrode film 30. The insulating layer 32 may be formed to have a thickness of 1000 Å with PETEOS. The insulating layer 32 may be formed by, for example, a physical vapor deposition (PVD) method at a temperature of 200 ° C. The insulating layer 32 may also be formed thinner than the lower electrode 26 between the lower electrodes 26.

Referring to FIG. 3, the anisotropic etching process may be performed to sequentially etch the insulating layer 32, the upper electrode layer 30, and the phase change layer 28 to form the interlayer between the lower electrodes 26. The insulating film 22 is exposed. The front anisotropic etching process is preferably performed using a gas containing carbon tetrachloride (CF ₄ ), chlorine (Cl ₂ ) and argon (Ar). As a result, since the films between the lower electrodes 26 are relatively thinner than those on the lower electrode 26, the sidewalls of the lower electrode 26 are separated from the phase change film 28 and the upper electrode as shown in FIG. 3. The film 30 is formed to cover. In addition, since the thickness of the phase change layer 28 etched in the front anisotropic etching process is thin, the etching damage can be reduced compared to the conventional. Therefore, an operation error of the phase change memory device may be minimized by minimizing the nonuniformity of the resistance of the phase change layer 28 due to etching damage.

Therefore, according to the phase change memory device and the method of forming the same according to the present invention, it is possible to reduce the etching damage and minimize the operation error of the phase change memory device.

1 and 2 sequentially illustrate a method of forming a phase change memory device according to the prior art.

3 is a cross-sectional view of a phase change memory device according to an embodiment of the present invention.

4 to 8 sequentially illustrate the method of forming the phase change memory device of FIG.

* Explanation of symbols for the main parts of the drawings

1, 20: semiconductor substrate 3, 22: interlayer insulating film

5, 24: lower electrode contact 26: lower electrode

7, 28: phase change film 9, 30: upper electrode film

11, 32: insulating film

Claims (10)

Forming a plurality of bottom electrode contacts electrically connected to the semiconductor substrate through the interlayer insulating film on the semiconductor substrate; Forming a plurality of lower electrodes overlapping the plurality of lower electrode contacts, respectively, on the interlayer insulating film; Stacking a phase conversion film, an upper electrode film, and an insulating film on the semiconductor substrate on which the lower electrodes are formed; And Performing an entire anisotropic etching to etch the insulating film, the upper low electrode film and the phase change element film to expose an interlayer insulating film between the lower electrodes, In the stacking of the phase change film, the upper electrode film, and the insulating film, the phase change film, the upper electrode film, and the insulating film are thickly stacked on the lower electrode, and thinly stacked on the sidewall of the lower electrode. And the front side anisotropic etching is performed such that the top and side surfaces of the lower electrodes are covered by at least the phase change layer and the upper electrode layer. The method of claim 1, The lower electrode and the upper electrode layer include titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), iridium (Ir), platinum (Pt), osmium (Os), ruthenium (Ru), and rhodium ( And at least one metal selected from the group consisting of Rh) and palladium (Pd) or a nitride film of the metal. The method of claim 1, And the phase change film is formed of Ge _X Sb _Y Te _Z. The method of claim 1, And the insulating film is formed of plasma enhanced tetraethyl orthosilicate (Si (OC ₂ H ₅ ) ₄ ). The method of claim 1, The front side anisotropic etching step is performed using a gas containing carbon tetrachloride (CF ₄ ), chlorine (Cl ₂ ) and argon (Ar). The method of claim 1, And at least the phase change film and the insulating film are formed by a physical vapor deposition process. A plurality of lower electrode contacts electrically connected to the semiconductor substrate through the interlayer insulating layer on the semiconductor substrate; A plurality of lower electrodes respectively overlapping the plurality of lower electrode contacts on the interlayer insulating layer; A phase conversion layer covering upper and side surfaces of the lower electrode; The upper electrode film and the insulating film on the upper electrode film is sequentially stacked on the phase change film, the ends of which are aligned with the ends of the phase change film, And the phase change film has a thicker thickness on top of the lower electrode than on the side of the lower electrode. The method of claim 7, wherein The lower electrode and the upper electrode layer include titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), iridium (Ir), platinum (Pt), osmium (Os), ruthenium (Ru), and rhodium ( Rh) and at least one metal selected from the group consisting of palladium (Pd) or a nitride film of said metal. The method of claim 7, wherein And the phase change film is formed of Ge _X Sb _Y Te _Z. The method of claim 7, wherein And the insulating film is formed of plasma enhanced tetraethyl orthosilicate (Si (OC ₂ H ₅ ) ₄ ).