KR20050053249A - Method for forming a transistor in a semiconductor device - Google Patents

Abstract

Disclosed is a method of forming a transistor of a semiconductor device. A gate structure consisting of a nitride oxide film pattern, a gate oxide film pattern, and a gate polysilicon film pattern is formed on the substrate, and an oxynitride film is continuously formed. Subsequently, after forming the preliminary source / drain electrodes on the substrate, spacers are formed on both sidewalls of the gate structure, and ion implantation is performed again to form the preliminary source / drain electrodes as source / drain electrodes having an LED structure. . After the silicide film and the silicon oxide film are formed on the substrate, the silicon oxide film is polished until the surface of the gate polysilicon film pattern is exposed. Subsequently, after exposing the nitride oxide pattern of the gate electrode, a gate electrode including an insulating film having a high dielectric constant, a gate barrier metal film, and a gate metal film is formed on the removed resultant.

Description

Method for forming a transistor in a semiconductor device

The present invention relates to a method for forming a transistor in a semiconductor device.

In recent years, with the rapid spread of information media such as computers, semiconductor devices are also rapidly developing. In terms of its function, the semiconductor device is required to operate at a high speed and to have a large storage capacity. In response to these demands, manufacturing techniques have been developed to improve the degree of integration, reliability, response speed, and the like of semiconductor devices. As a general-purpose memory device that can freely input and output information, DRAM (Dynamic Random Access Memory) is widely known.

As described above, since the semiconductor device is highly integrated, the line width and impurity region of the gate electrode of the transistor, that is, the region of the source / drain electrode, are also reduced. Therefore, recent semiconductor devices require the formation of a shallow junction, that is, a source / drain electrode having an LED structure.

1A to 1D are cross-sectional views illustrating a method of forming a transistor of a conventional semiconductor device.

Referring to FIG. 1A, the trench isolation layer 12 is formed on the substrate 11. Accordingly, the substrate 11 is divided into an active region and an inactive region. In order to control the threshold voltage, impurities are injected into the substrate. Subsequently, a gate oxide film 13 is formed on the substrate 11 by thermal oxidation using oxygen gas or hydrogen gas in a temperature atmosphere of 800 to 900 ° C., and a gate polysilicon film 14 is formed thereon.

Referring to FIG. 1B, the gate polysilicon layer 14 and the gate oxide layer 13 are patterned. As a result, a gate structure including the gate oxide film pattern 13a and the gate polysilicon film pattern 14a is formed on the substrate 11. Subsequently, ion implantation using the gate structure as a mask is performed to form the preliminary source / drain electrodes 15 on the substrate 11 adjacent to the gate structure.

Referring to FIG. 1C, a spacer 20 including a low pressure silicon oxide layer 16 and a silicon nitride layer 17 is formed on sidewalls of the gate structure. That is, the spacer 20 is formed through lamination and front surface etching. Thus, a gate electrode having the gate structure and the spacer 20 is obtained. Subsequently, ion implantation is performed using the gate electrode as a mask to form the preliminary source / drain electrodes 15a and 15b as source / drain electrodes 18a and 18b having an LDD structure.

Referring to FIG. 1D, a silicide layer 19 is formed on the substrate 11 of the gate polysilicon layer pattern 14a and the source / drain electrodes 18a and 18b by performing a self-aligned silicide process. Thus, a transistor having a gate electrode and a source / drain electrode and having a silicide film formed thereon is formed.

Here, when the gate oxide film is formed by the thermal oxidation method, the leakage current may be large because the thickness is very thin. Therefore, it can act as a cause of increasing power consumption. In the case of using the gate polysilicon film, since the ion reduction region may occur in the electrodes of the transistor, it is not easy to adjust the electric gate thickness. In addition, the ions implanted to form the source / drain electrodes may affect the threshold voltage by penetrating into the channel region by heat treatment. In addition, hot carriers frequently occur.

As described above, when the transistor is formed through the conventional method, there is a problem in that the reliability of the semiconductor device is lowered due to the above-described defects.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a transistor of a semiconductor device in which a gate barrier metal film and a gate metal film can be applied using an inlay technique.

The transistor forming method of the present invention for achieving the above object,

Forming a trench isolation layer on the substrate to separate the active region and the inactive region;

Implanting ions into the active region to form a well;

Forming a gate structure including the nitride oxide pattern, the gate oxide pattern, and the gate polysilicon pattern;

Continuously forming an oxynitride film on a surface of the substrate and the gate structure;

Ion implanting the gate structure as a mask to form a preliminary source / drain electrode on a substrate adjacent to the gate structure;

Forming spacers on both sidewalls of the gate structure;

Ion implanting the gate structure and the spacer with a mask to form the preliminary source / drain electrodes as source / drain electrodes of an LED structure;

Forming a silicide film on the substrate of the source / drain electrode;

Forming a silicon oxide film on the resultant product;

Polishing the silicon oxide layer until the surface of the gate polysilicon layer pattern of the gate electrode is exposed;

Removing the gate polysilicon pattern and the gate oxide pattern of the gate electrode to expose the nitride oxide pattern of the gate electrode;

Continuously forming an insulating film having a high dielectric constant on sidewalls and bottom surfaces of the removed results;

Forming a gate barrier metal film along a surface of the insulating film; And

Forming a gate electrode by sufficiently filling the gate metal film in the resultant film formed with the insulating film and the gate barrier metal film.

The oxide nitride film pattern may be formed to have a thickness of 10 to 15 kPa in a temperature atmosphere of 750 to 900 ° C., and the silicide film may be formed using cobalt, titanium nitride, or a mixture thereof. The dielectric film having a dielectric constant is preferably a hafnium oxide film or a tantalum oxide film, the gate barrier metal film is a titanium nitride film, and the gate metal film is an aluminum film or a copper film.

In addition, it is preferable to further include the step of removing the oxide film remaining on the substrate before forming the nitride oxide film, a mixture of NH ₄ OH, H ₂ O ₂ and H ₂ O having a mixing ratio of about 1: 1: 5 Use a solution. In addition, it is preferable to perform washing further using a hydrofluoric acid solution.

As described above, according to the present invention, reliability of a semiconductor device can be ensured by applying an insulating film having a high dielectric constant as the gate insulating film and applying a nitride oxide film against the penetration of ions such as boron, the penetration of a hot carrier, and the like. As a component of the gate electrode, a material having a low resistance of 5 Ω / square or less, such as a gate barrier metal film, a gate metal film, or the like, can be used to improve the operation speed. Further, by forming the gate electrode after forming the source / drain electrodes, it is possible to secure more excellent reliability and to prevent the silicide film from being formed in the portion where the spacer is formed.

Therefore, when the method of the present invention is applied to the manufacture of a semiconductor device, it is possible to implement a transistor having better reliability.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views illustrating a method of forming a transistor in a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, the trench isolation layer 32 is formed on the substrate 31. Accordingly, the substrate 31 is divided into an active region and an inactive region. Subsequently, ions are implanted into the active region to form wells. In this case, the ions for forming the well may be arbitrarily defined as p type or n type. Then, heat treatment is performed to activate the ions. As such, by forming a well in the substrate 31, the threshold voltage is adjusted. The oxide film remaining on the substrate 31 is removed using a mixed solution of NH ₄ OH, H ₂ O _2, and H ₂ O having a mixing ratio of 1: 1: 1, and a hydrofluoric acid-based solution is used. To wash.

Subsequently, the nitride oxide film 33, the gate oxide film 34, and the polysilicon film 35 are sequentially formed on the substrate 31. Here, the nitride oxide film 33 is formed using nitrogen oxide gas in a temperature atmosphere of about 800 ℃. In addition, while the nitride oxide film 33 is formed, the gate oxide film 34 is formed.

Referring to FIG. 2B, the nitride oxide layer 33, the gate oxide layer 34, and the polysilicon layer 35 may be nitrided, the gate oxide layer pattern 34a, and the polysilicon layer pattern by patterning by etching. It forms as (35a). Accordingly, a gate structure including a nitride oxide pattern 33a, a gate oxide pattern 34a, and a gate polysilicon layer pattern 35a is formed on the substrate 31. Subsequently, an oxynitride film 36 is continuously formed on the surfaces of the substrate 31 and the gate structure. In addition, ion implantation is performed using the gate structure as a mask to form preliminary source / drain electrodes 37a and 37b on the substrate 31 adjacent to the gate structure.

Referring to FIG. 2C, after the low pressure silicon oxide layer is laminated on the substrate 31, the entire surface is etched. Accordingly, spacers 38 formed of the low pressure silicon oxide layer are formed on both sidewalls of the gate structure. The preliminary source / drain electrodes 37a and 37b are formed as the source / drain electrodes 39a and 39b of the LED structure by ion implantation using the gate structure and the spacer 38 as a mask. Subsequently, in order to lower the resistance of the source / drain electrodes 39a and 39b, a silicide layer 40 is formed on the substrate 31 of the source / drain electrodes 39a and 39b using a material such as cobalt or titanium nitride. do. That is, after removing the remaining natural oxide film on the substrate 31, a material for forming the silicide film 40 is deposited, and rapid heat treatment at a temperature of 600 ℃ or less to promote the reaction between the material and silicon , Unreacted material is removed using SC-1 solution. Subsequently, the silicide layer 40 is formed on the substrate 31 of the source / drain electrodes 39a and 39b by performing heat treatment at a high temperature of 650 ° C. or higher.

Referring to FIG. 2D, a silicon oxide film 41 is formed on the substrate 31 having the result through a chemical vapor deposition process. Subsequently, the silicon oxide layer 41 is polished until the surface of the gate polysilicon layer pattern 35a of the gate structure is exposed. At this time, the polishing is accomplished by chemical mechanical polishing. Subsequently, the gate polysilicon film pattern 35a exposed by the polishing is removed. The gate oxide pattern 34a exposed by the removal is removed. At this time, the removal is performed using HF solution. As such, the nitride oxide pattern 33a of the gate structure is exposed by removing the gate polysilicon pattern 35a and the gate oxide pattern 34a.

Referring to FIG. 2E, an insulating film 42 having a high dielectric constant is continuously formed on the sidewalls and the bottom of the removed resultant. In this case, the insulating film 42 has a high dielectric constant, and a hafnium oxide film or a tantalum oxide film is applied. After the insulating film 42 is formed, heat treatment is performed using a N ₂ O gas in a temperature atmosphere of about 750 to 850 ° C. Here, even when the heat treatment is performed, an oxide film is prevented from being formed below the insulating film 42 in the nitride oxide film pattern 33a. Subsequently, a gate barrier metal film 43 is formed along the surface of the insulating film 42. In this case, the gate barrier metal layer 43 mainly uses titanium nitride. In addition, the gate metal film 44 is sufficiently embedded in the resultant film formed with the insulating film 42 and the gate barrier metal film 43 to form a gate electrode.

Therefore, a thin film having a high dielectric constant is used as the gate insulating film, and a thin film having a low resistance is used as the gate electrode material. Therefore, leakage current generated in the gate insulating film can be reduced. In particular, when the tantalum oxide film is used as the gate insulating film, the thickness thereof may be about 25 GPa, but the dielectric constant is about 20 to 26, which is five times higher than that of the oxide film. Therefore, the occurrence of leakage current can be reduced. In addition, by applying the nitride oxide film, it is possible to prevent the penetration of ions generated in a subsequent step. In addition, since a material of 5 Ω / square or less is required as the gate electrode material, it is possible to sufficiently secure reliability such as a threshold voltage. In addition, since the silicide film can be prevented from being formed in the portion having the spacer, it is possible to secure superior reliability.

As described above, according to the present invention, it is possible to form a transistor having excellent electrical characteristics. Therefore, the present invention has the effect of improving the reliability of the semiconductor device.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

1A to 1D are cross-sectional views illustrating a method of forming a transistor of a conventional semiconductor device.

2A through 2E are cross-sectional views illustrating a method of forming a transistor in a semiconductor device according to an embodiment of the present invention.

Claims (5)

Forming a trench isolation layer on the substrate to separate the active region and the inactive region; Implanting ions into the active region to form a well; Forming a gate structure including the nitride oxide pattern, the gate oxide pattern, and the gate polysilicon pattern; Continuously forming an oxynitride film on a surface of the substrate and the gate structure; Ion implanting the gate structure as a mask to form a preliminary source / drain electrode on a substrate adjacent to the gate structure; Forming spacers on both sidewalls of the gate structure; Ion implanting the gate structure and the spacer with a mask to form the preliminary source / drain electrodes as source / drain electrodes of an LED structure; Forming a silicide film on the substrate of the source / drain electrode; Forming a silicon oxide film on the resultant product; Polishing the silicon oxide layer until the surface of the gate polysilicon layer pattern of the gate electrode is exposed; Removing the gate polysilicon pattern and the gate oxide pattern of the gate electrode to expose the nitride oxide pattern of the gate electrode; Continuously forming an insulating film having a high dielectric constant on sidewalls and bottom surfaces of the removed results; Forming a gate barrier metal film along a surface of the insulating film; And Forming a gate electrode by sufficiently filling a gate metal film in a resultant product in which the insulating film and the gate barrier metal film are formed. The method of claim 1, wherein the nitride oxide pattern is formed to have a thickness of about 10 to about 15 microseconds in a temperature atmosphere of about 750 to about 900 degrees Celsius. The method of claim 1, wherein the silicide film is formed using cobalt, titanium nitride, or a mixture thereof. The method of claim 1, wherein the insulating film having a high dielectric constant is a hafnium oxide film or a tantalum oxide film. The method of claim 1, wherein the gate barrier metal film is a titanium nitride film, and the gate metal film is an aluminum film or a copper film.