KR20050048411A - Display apparatus and method of manufacturing the same - Google Patents

Abstract

Disclosed are a display device and a method of manufacturing the same, which can prevent a malfunction of a gate driver. The lower substrate includes a first electrode wiring and a first insulating film provided in the display unit, the driving unit, and the pad unit, and the first insulating layer partially exposes the first electrode wiring in the driving unit and the pad unit. A second electrode wiring electrically connected to the exposed first electrode wiring is provided on the first insulating film, and a second insulating film is provided on the lower substrate on which the second electrode wiring is formed. The second insulating film is partially exposed on the second insulating film in the display portion and the pad portion. The conductive film is electrically connected to the exposed second electrode wiring. Therefore, malfunction of the gate driver can be prevented.

Description

DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME}

The present invention relates to a display device and a manufacturing method thereof, and more particularly, to a display device and a method for manufacturing the same that can prevent the malfunction of the drive unit.

In general, the liquid crystal display device includes a lower substrate, an upper substrate, and a liquid crystal layer interposed between the lower substrate and the upper substrate.

The lower substrate includes a display area and a peripheral area adjacent to the display area. In the display area, a plurality of pixels are provided in a matrix form. Each of the plurality of pixels includes a gate line, a data line, a thin film transistor (hereinafter, referred to as a TFT) connected to the gate line and the data line, and a pixel electrode coupled to the TFT.

In the peripheral region, a gate driving circuit for applying a driving voltage to the gate line is formed by a TFT process. As such, by directly forming the gate driving circuit on the lower substrate, the volume and size of the liquid crystal display device can be reduced.

However, when the gate driving circuit is formed on the lower substrate, parasitic capacitance is generated between the gate driving circuit and the common electrode formed on the upper substrate. This parasitic capacitance causes a malfunction of the gate driving circuit.

Accordingly, it is an object of the present invention to provide a display device for preventing a malfunction of a gate driving circuit.

It is also an object of the present invention to provide a manufacturing method suitable for manufacturing the above display device.

According to an aspect of the present invention, a display device includes a lower substrate including a display unit for displaying an image, a driver driving the display area, and a pad unit providing various signals to the driver, and an upper substrate facing the lower substrate. do.

The lower substrate includes a first electrode wiring, a first insulating film, a second electrode wiring, a second insulating film, and a conductive film.

The first electrode wiring is provided on the display part, the driving part, and the pad part, and the first insulating film is provided on the lower substrate on which the first electrode wiring is formed. A first contact hole is formed in the first insulating layer to partially expose the first electrode wiring in the driving unit and the pad unit.

The second electrode wiring is provided on the first insulating film, and is electrically connected to the first electrode wiring exposed by the first contact hole. The second insulating layer is formed on the lower substrate on which the second electrode wiring is formed, and a second contact hole is formed in the display portion and the pad portion to partially expose the second electrode wiring. The conductive layer is formed on the second insulating layer and is electrically connected to the second electrode wiring exposed by the second contact hole.

In addition, according to another aspect of the present invention, there is provided a method of manufacturing a display device. Manufacturing a second substrate facing the substrate, and coupling the lower substrate and the upper substrate to each other by a coupling member between the lower substrate and the upper substrate in correspondence to the driving unit.

The lower substrate may have a first electrode wiring formed on the display unit, the driving unit, and the pad unit, and then a first insulating layer is formed on the lower substrate on which the first electrode wiring is formed, and the first insulating layer is patterned to form the first insulating layer. A first contact hole for partially exposing the first electrode wiring is formed in the pad part. Thereafter, a second electrode wiring is formed on the first insulating film to be electrically connected to the first electrode wiring exposed by the first contact hole, and a second insulating film is formed on the lower substrate on which the second electrode wiring is formed. To form. Next, the second insulating layer is patterned to form a second contact hole for partially exposing the second electrode wiring in the display unit and the pad unit, and the second exposed hole is exposed by the second contact hole on the second insulating layer. This is completed by forming a conductive film electrically connected to the electrode wiring.

According to the display device and the method of manufacturing the same, the first and second electrode wirings provided in the driving part are entirely covered by the second insulating film, thereby preventing malfunction of the driving part.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

1 is a cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a plan view of the lower substrate shown in FIG.

Referring to FIG. 1, a liquid crystal display device 400 according to an exemplary embodiment of the present invention may include a lower substrate 100, an upper substrate 200 facing the lower substrate 100, and an upper portion of the lower substrate 100. The liquid crystal layer 300 interposed between the substrate 200 and the sealant 350 for coupling the lower substrate 100 and the upper substrate 200 to each other.

As shown in FIG. 2, the lower substrate 100 includes a display area DA displaying an image, a gate driving area GDA adjacent to the display area DA, a data driving area DDA, and a gate pad. It is divided into regions GPA.

The display area DA includes a plurality of gate lines GL extending in a first direction and a plurality of data lines DL extending in a second direction perpendicular to the first direction. A plurality of pixel areas in a matrix form is defined in the display area DA by the plurality of gate lines GL and data lines DL.

Each pixel area includes a TFT 120 and a pixel electrode 141. A first gate electrode of the TFT is connected with a corresponding gate line, a first data electrode is connected with a corresponding data line, and a second drain electrode is coupled with the pixel electrode.

The gate driving region GDA is formed adjacent to one end of the plurality of gate lines GL, and the gate driving signals are sequentially output to the plurality of gate lines GL in the gate driving region GDA. The gate side driving circuit 150 is provided. Here, the gate side driving circuit 150 is formed through the same process as the TFT 120.

Meanwhile, a data driving area DDA is formed adjacent to one end of the plurality of data lines DL, and a data side for outputting data signals to the plurality of data lines DL in the data driving area DDA. The driving circuit 160 is provided. The data side driving circuit 160 is mounted in the data driving region DDA in a chip form.

Although not illustrated, the lower substrate 100 may include a gate pad area including a gate pad providing various signals to the gate driving circuit 150 and a data pad providing various signals to the data driving circuit 160. It further comprises a data pad area provided.

Referring back to FIG. 1, the lower substrate 100 is a substrate provided with a plurality of layers on the first substrate 110. On the first substrate 110, the first gate electrode 121a corresponds to the display area DA, and the second gate electrode 121b and the gate pad area GPA correspond to the gate driving area GDA. Correspondingly, the third gate electrode 121c is formed.

In addition, a gate insulating layer 122 is formed on the first substrate 110, and the gate insulating layer 122 is formed in the gate driving region GDA and the gate pad region GPA. The third gate electrode 121c is exposed.

The active layer 124 and the ohmic contact layer 125 are formed on the gate insulating layer 130 corresponding to the display area DA to include a region where the first gate electrode 121a is formed.

Second data electrodes spaced apart from the first data electrode 123a and the first data electrode 123a on the gate insulating layer 122 and the ohmic contact layer 124 in correspondence with the display area DA. 123b is formed. In addition, a third data electrode 123c is formed on the gate insulating layer 122 and the exposed second gate electrode 121b corresponding to the gate driving region GDA. A fourth data electrode 123d is formed on the gate insulating layer 122 and the exposed third gate electrode 121c corresponding to the gate pad region GPA.

Subsequently, a passivation layer 130 is formed on the gate insulating layer 122, the second data electrode 123a, the second data electrode 123b, the third data electrode 123c, and the fourth data electrode 123d on the first substrate. Is formed. The passivation layer 130 exposes the second data electrode 123b and the fourth data electrode 123d in the display area DA and the gate pad area GPA, respectively.

Next, a pixel electrode 141 is formed on the passivation layer 150 and the exposed second data electrode 123b corresponding to the display area DA, and the passivation layer 130 corresponding to the gate pad area GPA. ) And a pad electrode 142 is formed on the exposed fourth data electrode 123d.

The upper substrate 200 is a substrate on which the color filter 220 made of R, G, and B color pixels and the common electrode 230 made of a transparent conductive material are sequentially formed on the second substrate 210. The upper substrate 200 is coupled to the lower substrate 100 in a state spaced apart at a predetermined interval.

The liquid crystal layer 300 is interposed between the upper substrate 100 and the lower substrate 200 corresponding to the display area DA.

The sealant 350 is interposed between the lower substrate 100 and the upper substrate 200 to correspond to the gate driving region GDA. That is, the sealant 350 is interposed between the third data electrode 123c and the common electrode 230 to generate the sealant 350 between the third data electrode 123c and the common electrode 230. Reduces parasitic capacitances.

Since the sealant 350 has a dielectric constant smaller than that of the liquid crystal layer 300, parasitic capacitance is greater than that of the liquid crystal layer 300 interposed between the common electrode 230 and the third data electrode 123c. Can be reduced.

When the sealant 350 is formed on the gate driving circuit 150 (refer to FIG. 2), the sealant 350 may not cover the gate driving circuit 150 entirely due to a process error. Occurs. However, since the passivation layer 130 covers the gate driving circuit 150, the gate driving circuit 150 may be prevented from being contaminated or corroded by foreign matter.

3A to 3F are views illustrating a manufacturing process of the lower substrate shown in FIG. 2.

Referring to FIG. 3A, sputtering a first metal film (not shown) made of aluminum (Al), chromium (Cr), or molybdenum tungsten (MoW) on a first substrate 110 made of an insulating material such as glass or ceramic. Vapor deposition by the method. Thereafter, the first metal layer is patterned by a photolithography process using the first mask 171 to form the first gate electrode 121a in the display area DA. At the same time, the second gate electrode 121b is formed in the gate driving region GDA, and the third gate electrode 121c is formed in the gate pad region GPA.

Referring to FIG. 3B, silicon nitride is deposited on the first substrate 110 on which the first to third gate electrodes 121a, 121b, and 121c are formed by plasma-enhanced chemical vapor deposition (PECVD). The gate insulating film 122 is formed. Thereafter, the gate insulating layer 122 is patterned using the second mask 172 to expose the first gate hole 122a and the third contact hole 122b to the gate insulating layer 122. A second contact hole 122b exposing the gate electrode 121c is formed.

Referring to FIG. 3C, an amorphous silicon film (not shown) is deposited on the gate insulating layer 122 by a plasma chemical vapor deposition method, and an n + doped amorphous silicon film (not shown) is deposited on the gate insulating film 122. By deposition. At this time, the amorphous silicon film and the n + doped amorphous silicon film are deposited in-situ in the same chamber of the plasma chemical vapor deposition facility.

Subsequently, the active layer 124 and the ohmic contact layer 126 are formed on the gate insulating layer 122 to correspond to the region where the first gate electrode 121a is formed through a photolithography process using the third mask 173. Form.

Referring to FIG. 3D, a second metal film (not shown) such as chromium (Cr) is deposited on the first substrate 110 on which the gate insulating layer 122 and the ohmic contact layer 125 are formed by a sputtering method. Subsequently, in the photolithography process using the fourth mask 174, the second metal layer is patterned to form a second spaced apart from the first data electrode 123a and the first data electrode 123a at a predetermined interval in the display area DA. 2 data electrodes 123b are formed.

At the same time, a third data electrode 123c electrically connected to the second gate electrode 121b exposed through the first contact hole 122a is formed in the gate driving region GDA. In addition, a fourth data electrode 123d electrically connected to the third gate electrode 121c exposed through the second contact hole 122b is formed in the gate pad region GPA.

Subsequently, the ohmic contact layer 125 exposed between the first data electrode 123a and the second data electrode 123b is removed by a reactive ion etching (RIE) method. Then, the active layer 124 exposed between the first data electrode 123a and the second data electrode 123b is provided to the channel region of the TFT 120.

3E, a passivation layer 130 including a silicon nitride layer (SiNx) or a silicon oxide layer (SiOx) is formed on the first substrate. A fourth contact hole 131 exposing the second data electrode 123b and a fourth exposing fourth data electrode 123d in the passivation layer 130 through a patterning process using a fifth mask 175. The contact hole 132 is formed.

Referring to FIG. 3F, a transparent conductive film, such as indium tin oxide (ITO) or indium zinc oxide (IZO), is deposited on the first substrate.

Thereafter, the transparent conductive film is patterned through the sixth mask 176 to form the pixel electrode 141 in the display area DA. The pixel electrode 141 is electrically connected to the second data electrode 123b of the TFT 120 exposed through the third contact hole 131. At the same time, a pad electrode 142 is formed in the gate pad region GPA. The pad electrode 142 is electrically connected to the fourth data electrode 123d exposed through the fourth contact hole 132. As a result, the lower substrate 100 is completed.

According to such a display device and a manufacturing method thereof, the passivation layer covers the second gate electrode and the third data electrode as a whole in the driving unit of the lower substrate, and a sealant is interposed between the lower substrate and the upper substrate in correspondence with the driving unit. .

Therefore, parasitic capacitance generated between the common electrode formed on the upper substrate and the gate driver can be reduced. As a result, malfunction of the gate driver can be prevented.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

1 is a cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a plan view of the lower substrate shown in FIG. 1.

3A to 3F are views illustrating a process of manufacturing the lower substrate shown in FIG. 1.

<Explanation of symbols for the main parts of the drawings>

100: lower substrate 120: TFT

130: protective film 141: pixel electrode

142: pad electrode 200: upper substrate

220: color filter 230: common electrode

300: liquid crystal layer 350: sealant

400: liquid crystal display

Claims (7)

A lower substrate including a display unit displaying an image, a driver driving the display area, and a pad unit providing various signals to the driver; And An upper substrate facing the lower substrate, The lower substrate, A first electrode wiring provided in the display unit, the driving unit, and the pad unit; A first insulating layer provided on the lower substrate on which the first electrode wiring is formed, and having a first contact hole partially exposing the first electrode wiring in the driving part and the pad part; A second electrode wiring provided on the first insulating film and electrically connected to the first electrode wiring exposed by the first contact hole; A second insulating layer provided on the lower substrate on which the second electrode wiring is formed, and having a second contact hole partially exposing the second electrode wiring in the display portion and the pad portion; And And a conductive film disposed on the second insulating film and electrically connected to the second electrode wiring exposed by the second contact hole. The method of claim 1, wherein the first electrode wiring, A first gate electrode provided on the display unit; A second gate electrode provided in the driving unit; And And a third gate electrode provided in the pad part. The method of claim 2, wherein the second electrode wiring, A first data electrode provided on the first insulating layer on which the first gate electrode is located; A second data electrode spaced apart from the first data electrode at a predetermined interval on the first insulating layer on which the first gate electrode is located; A third data electrode electrically connected to the second gate electrode; And And a fourth data electrode electrically connected to the third gate electrode. The method of claim 3, wherein the conductive film, A pixel electrode electrically connected to the second data electrode; And And a pad electrode electrically connected to the fourth data electrode. The liquid crystal display device of claim 1, further comprising: a liquid crystal layer interposed between the lower substrate and the upper substrate corresponding to the display unit; And And a coupling member interposed between the lower substrate and the upper substrate corresponding to the driving part. The display device of claim 1, wherein the second insulating layer covers the first and second electrode wirings positioned in the driving unit as a whole. Manufacturing a lower substrate including a display unit displaying an image, a driver driving the display area, and a pad unit providing various signals to the driver; Manufacturing a second substrate facing the upper substrate; And Coupling the lower substrate and the upper substrate through a coupling member between the lower substrate and the upper substrate corresponding to the driving unit; Manufacturing the lower substrate, Forming a first electrode wiring on the display unit, the driving unit, and the pad unit; Forming a first insulating film on the lower substrate on which the first electrode wiring is formed; Patterning the first insulating layer to form a first contact hole partially exposing the first electrode wiring in the driving unit and the pad unit; Forming a second electrode wiring on the first insulating layer, the second electrode wiring electrically connected to the first electrode wiring exposed by the first contact hole; Forming a second insulating film on the lower substrate on which the second electrode wiring is formed; Patterning the second insulating layer to form a second contact hole partially exposing the second electrode wiring in the display unit and the pad unit; And And forming a conductive film on the second insulating film, the conductive film being electrically connected to the second electrode wiring exposed by the second contact hole.