KR20050014173A - Manufacturing method for semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, in order to prevent damage to a hard mask layer overlapping with a gate electrode, the interlayer insulating film applied after the formation of the gate electrode is planarized with a high selectivity slurry so as to harden the height and height After the landing plug contact hole is formed, the applied polycrystalline silicon layer is separated by an etch back process to form a landing plug, so that pinocchio defects are reduced and subsequent process margins are increased, thereby improving process yield and device reliability. .

Description

Manufacturing method for semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to prevent damage to a hard mask layer for protecting a gate electrode of a metal oxide semi conductor field effect transistor (hereinafter referred to as a MOS FET) and to form a landing plug. The present invention relates to a method for manufacturing a semiconductor device capable of preventing a decrease in refresh characteristics due to substrate damage at the time.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.

The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate. It is inversely proportional to the lens aperture (NA, numerical aperture) of the device.

[R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.

In addition to the reduction exposure apparatus, the process method includes a method of using a phase shift mask as a photo mask, or forming a separate thin film on the wafer to improve image contrast. A contrast enhancement layer (CEL) method or a tri layer resister (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers. In addition, a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings has a larger design rule than the above line / space pattern. As the device becomes more integrated, the size of the contact hole and the distance between the peripheral wirings are reduced, and the contact hole diameter and The aspect ratio, which is the ratio of depths, increases. Therefore, in the highly integrated semiconductor device having the multilayer conductive wiring, accurate and strict alignment between the masks in the contact forming process is required, so that the process margin is reduced or the process must be performed without any margin.

These contact holes can be used for misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, The mask is formed by considering factors such as registration between the masks.

As a method of forming the contact hole as described above, there are a direct etching method, a method using a sidewall spacer, a SAC method, and the like.

In the above method, the direct etching method and the sidewall spacer forming method cannot be used for manufacturing a device having a design rule of 0.3 μm or less in the current technology level, and thus there is a limitation in high integration of the device.

In addition, the SAC method, which is designed to overcome the limitations of the lithography process in forming contact holes, can be divided into polysilicon layer, nitride film, or oxynitride film, depending on the material used as the etch barrier layer. Can be used as an etch shield.

Although not shown, the method of manufacturing a landing plug of a semiconductor device according to the related art is as follows.

First, a gate oxide film is formed on a semiconductor substrate, and a gate electrode overlapping the hard mask layer pattern is formed on the gate oxide film, and then insulating spacers made of nitride are formed on sidewalls of the hard mask layer pattern and the gate electrode. After that, the interlayer insulating film is applied to the entire surface of the structure and then planarized.

The gate electrode is a low-resistance structure in which W or tungsten silicide is stacked on polycrystalline silicon, and in order to pattern the gate electrode, the thickness of the hard mask layer pattern is increased to increase the aspect ratio.

Then, the landing plug contact hole is formed by a photolithography process using an etching mask for the landing plug. At this time, as can be seen in Figure 1, it can be seen that the loss of the hard mask layer occurs a lot, the top is sharp, this shape to avoid damage even if the slurry has a selectivity to the nitride film in the subsequent CMP process Can't.

The contact hole is then filled by applying a polycrystalline silicon layer for landing plug to the entire surface of the structure. In this case, it has a structure as shown in FIG. 2, but until the point ⓐ is etched to prevent the polysilicon layer bridge at the wafer level.

Then, the upper portion of the polysilicon layer is etched by a CMP process, and a predetermined thickness is etched and separated to form a landing plug. As can be seen in Figure 3, the part ⓑ is the remaining thickness of the hard mask layer pattern, the thickness should be maintained at least about 800Å to prevent the occurrence of defects in the subsequent process.

In the method of manufacturing a semiconductor device according to the prior art as described above, the aspect ratio in the shape of the gate electrode is increased so that the hard mask layer on the top of the gate electrode is damaged in the gate electrode patterning process so that the top is sharp and the selectivity of the slurry in the subsequent process. Nevertheless, there is a problem in that it is difficult to maintain a certain thickness, such as a Pinocchio defect connected to the adjacent cells as shown in FIG.

The present invention is to solve the above problems, the object of the present invention is

Flatten the top of the interlayer insulating film to match the height of the hard mask layer, form a landing plug contact hole, and then remove the polysilicon layer using an etch back to minimize loss of the hard mask layer to prevent the occurrence of uncooling in subsequent processes. By providing a method of manufacturing a semiconductor device that can improve the process yield and the reliability of the device.

1 is a cross-sectional SEM photograph of a semiconductor device in a landing plug contact hole is formed according to the prior art.

FIG. 2 is a cross-sectional SEM photograph of a semiconductor device in which a polysilicon layer for landing plug is coated according to the prior art. FIG.

3 is a cross-sectional SEM photograph of a semiconductor device in a landing plug is formed according to the prior art.

Figure 4 is a planar SEM photograph of a semiconductor device in a Pinocchio failure state according to the prior art.

5a to 5c is a manufacturing process diagram of a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10 semiconductor substrate 12 gate oxide film

14 gate electrode 16 hard mask layer

18 spacer 20 interlayer insulating film

22: landing plug contact hole 24: polysilicon layer

Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,

Forming a gate oxide film on the semiconductor substrate;

Forming a gate electrode overlapping the hard mask layer pattern on the gate oxide film;

Forming an insulating spacer on sidewalls of the hard mask layer pattern and the gate electrode;

Forming an interlayer insulating film on the entire surface of the structure;

CMP etching the upper portion of the interlayer insulating layer to expose the upper portion of the hard mask layer pattern;

Selectively etching the interlayer dielectric layer with a landing plug contact mask to form a landing plug contact hole;

Forming a polysilicon layer on the entire surface of the structure;

The polysilicon layer is separated by an etch back process to form a landing plug.

In addition, another feature of the present invention,

In order to reduce the step between the cell region and the peripheral circuit region before the CMP process, a selective etching process is performed to remove a part of the interlayer dielectric layer thickness of the cell region using a cell open mask, or after forming the contact hole, a nitride film is formed on the sidewall of the contact hole. And forming a spacer, wherein the nitride spacer is formed of a plasma induced CVD nitride film or a low pressure CVD nitride film, and a buffer oxide film is formed before or after the nitride film spacer is formed.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

5A to 5C are manufacturing process diagrams of a semiconductor device according to the present invention.

First, the gate oxide film 12 is formed on the semiconductor substrate 10, and the gate electrode 14 and the gate having a low resistance structure in which W or tungsten silicide are stacked on the polycrystalline silicon on the gate oxide film 12. After forming the hard mask layer 16 pattern of the nitride film material overlapping with the electrode 14, the insulating spacer 18 of the nitride film material is formed on the sidewalls of the gate electrode 14 and the hard mask layer 16 pattern. An interlayer insulating film 20 made of oxide film is formed on the entire surface of the structure. (See FIG. 5A).

Next, the interlayer insulating film 20 is planarized by CMP etching using a slurry having a high selectivity ratio between the oxide film and the nitride film, for example, a selectivity ratio of the nitride film to the oxide film of 10: 1 or more, and the hard mask layer 16 pattern. As an etch barrier to have the same height. In order to reduce the step between the cell region and the peripheral circuit region before the CMP, a selective etching process may be performed to remove a part of the thickness of the interlayer insulating layer 20 of the cell region using a cell open mask.

Thereafter, the interlayer insulating layer 20 is patterned using a landing plug mask to form a landing plug contact hole 22 to expose the semiconductor substrate 10. In this case, after the contact hole 22 is formed, a plasma-induced CVD nitride film or a low pressure CVD nitride film is applied to the entire surface to reduce the damage of the hard mask layer 16 pattern, and then etched back to form nitride film spacers on the sidewalls of the contact holes. The buffer oxide film may be formed before or after the application of the spacer nitride film. (See FIG. 5B).

Then, the polysilicon layer 24 is applied to the entire surface of the structure, and then etched back to form landing plugs having a polysilicon layer 24 pattern filling the contact hole 22. (See FIG. 5C).

As described above, in the method of fabricating a semiconductor device according to the present invention, in order to prevent damage to the hard mask layer overlapping the gate electrode, the interlayer insulating film applied after forming the gate electrode is planarized with a high selectivity slurry to hard mask layer. And the landing plug was formed by separating the applied polycrystalline silicon layer after the formation of the landing plug contact hole by the etch back process, thereby reducing pinocchio defects and increasing subsequent process margins, thereby improving process yield and device reliability. There is an advantage to this.

Claims (5)

Forming a gate oxide film on the semiconductor substrate; Forming a gate electrode overlapping the hard mask layer pattern on the gate oxide film; Forming an insulating spacer on sidewalls of the hard mask layer pattern and the gate electrode; Forming an interlayer insulating film on the entire surface of the structure; CMP etching the upper portion of the interlayer insulating layer to expose the upper portion of the hard mask layer pattern; Selectively etching the interlayer dielectric layer with a landing plug contact mask to form a landing plug contact hole; Forming a polysilicon layer on the entire surface of the structure; And forming a landing plug by separating the polysilicon layer by an etch back process. The semiconductor device of claim 1, wherein a selective etching process is performed to remove a part of the interlayer dielectric layer thickness of the cell region using a cell open mask to reduce the step between the cell region and the peripheral circuit region before the CMP process. Manufacturing method. The method of claim 1, further comprising forming a nitride film spacer on a sidewall of the contact hole after the contact hole is formed. The method of claim 3, wherein the nitride film spacer is formed of a plasma induced CVD nitride film or a low pressure CVD nitride film. The method of manufacturing a semiconductor device according to claim 3, further comprising the step of forming a buffer oxide film before or after the nitride film spacer is formed.