KR20040064965A - Non-volatile semiconductor memory device - Google Patents

Abstract

The present invention relates to a nonvolatile semiconductor memory device. To this end, the present invention forms drains A and B (D1) and D2 on both sides of a surface, respectively, between the drain A (D1) and the drain B (D2). A silicon substrate 10 having a source S formed thereon; A first oxide film sequentially stacked on the silicon substrate 10 with both ends simultaneously overlapping between the drain A (D1) and the source S and between the drain B (D2) and the source S ( A charge storage unit 20 comprising a 21, a nitride film 22, and a second oxide film 23; And a unit cell as a conductive layer 30 stacked on the charge storage unit 20 to form a control gate. The unit cell is improved to improve the unit cell. It is characterized by increasing the data density by enabling simultaneous storage and erasure of Bit and Multi-Bit data.

Description

Non-volatile semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device. More particularly, the present invention relates to a non-volatile semiconductor memory device. A volatile semiconductor memory device.

In general, semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), are volatile and fast data input / output that loses data over time. It can be maintained as it is, but it can be divided into read only memory (ROM) which has slow input / output of data. Dual ROM can be categorized into ROM, Programmable ROM (PROM), Eraseable PROM (EPROM), and Electrically EPROM (EEPROM), among which EEPROM and Flash allow you to program and erase data, especially in an electrical way. As memory is used for various purposes, demand is increasing drastically.

Flash memory cells having an EEPROM cell or a batch erase function generally have a stacked gate structure in which a floating gate and a control gate are stacked.

Meanwhile, stand-alone EEPROM, Flash-memory and embedded (SONOS (Silicon-Oxide-Nitride-Oxide-Si sub) and MONOS (Metal-Oxide-Nitride-Oxide-Si sub) structures Multi-Bit, 2-Bit and 1-Bit Operation used in Embedded) type EEPROM and Flash memory are mainly designed to increase the efficiency of program and erase. We adopt concept of.

The basic structure of the device to which the concept of reverse lead is applied is, as shown in FIG. 1, in which the nitride film 3 and the second oxide film 4, which are provided as the first oxide film 2 and the floating gate, are sequentially disposed on the silicon substrate 1. The second oxide film 3 is formed in such a manner that the conductive film 5 provided as a control gate is stacked on the second oxide film 3 as a unit memory cell, and the unit cell has a structure deposited on the silicon substrate 1. Looking at one cell configuration, the unit cell is formed as a structure in which one gate (G) and two terminals (ie, a source (S) and a source (D)) are formed.

Therefore, the charge stored by the operation of the multi-bit through the coupling structure is asymmetrically overlapped between the gate gate and the gate edge on the left side. The charges are stored in the channel of -sub) in the range of several hundred Å by CHEI (Channel Hot Electron Injection) or CHISEL (CHannel Initiated Secondary ELectron Injection) method.

On the other hand, when the charge is stored on the right side, it is stored by changing the positions of the source S and the drain D and executing a program.

However, as mentioned above, since 2-Bit operation can only be performed by a sequential charge storage method, a method of simultaneously storing data of 2-Bit cannot be used at all.

Therefore, the present invention has been invented to solve the above-mentioned problems of the prior art, and a main object of the present invention is to be able to store charge of 2-Bit at the same time during 2-Bit operation.

In addition, the present invention has another object to enable the determination of the presence or absence of 2-Bit in one reading method.

Still another object of the present invention is to enable simultaneous erasing even when 2-bit is erased.

1 is a side cross-sectional view showing a conventional unit cell structure;

2 is a plan view showing an arrangement state of a unit cell according to the present invention;

3 is a cross-sectional view taken along the line A-A of FIG.

Explanation of symbols on the main parts of the drawings

10: silicon substrate 20: charge storage unit

21: first oxide film 22: nitride film

23: second oxide film 30: conductive film

G: Gate S: Source

D1: Drain A D2: Drain B

In order to achieve the above object, the present invention provides a silicon substrate for forming drains A and B on both sides of the surface, and a source formed between the drains A and B; A charge storage unit including a first oxide film, a nitride film, and a second oxide film sequentially stacked on the silicon substrate while the both ends of the drain A and the source and the drain B and the source overlap each other at the same time; And a unit cell as a conductive layer stacked on the charge storage unit to form a control gate.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2, one source S and two drain regions, that is, drains A (D1) and B (D2), one gate in a unit cell of the silicon substrate 10, as shown in FIG. 2. A structure (G) and a charge storage unit 20 capable of storing charges are provided between the conductive film 30 and the silicon substrate 10.

In other words, as shown in FIG. 3, two drain regions, Drain A (D1) and Drain B (D2), are formed on the silicon substrate 10, and both drains A, B (D1) ( A source S may be formed between the D2s, and a charge storage unit 20 may be deposited on the surface of the silicon substrate 10 to allow charge to be stored thereon. As described above, a part of the end portion overlaps the drains A (D1), B (D2) and the source S.

In addition, the conductive layer 30 is deposited on the charge storage unit 20 deposited on the surface of the silicon substrate 10.

In this case, the charge storage unit 20 is ONO (Oxide) in which the first oxide layer 21, the nitride layer 22, the nitride layer 22, and the second oxide layer 23 are sequentially stacked on the silicon substrate 10. / Nitride / Oxide) layer.

In such a configuration, the nitride film 22 of the charge storage unit 20 functions as a float gate, and the conductive film 30 deposited on the charge storage unit 20 functions as a control gate.

In the charge storage unit 20, the upper second oxide layer 23 is generally 50 to 200 mV, the nitride film 22 as a float gate is 40 to 150 mV, and the tunneling oxide layer 11 (tunneling oxide) 11 is about 15 to 60 mV. do.

In this case, the nitride film 22 is made of aluminum (Al) oxide / zirconium (Zr) oxide / hafnium (Hf) to obtain a lower threshold voltage than the threshold voltage (Vth) of the nitride film 22 or the oxide films 21 and 23. It can also be used as a / lanthanum (La) oxide.

Alternatively, a combination of aluminum (Al) oxide / zirconium (Zr) oxide / hafnium (Hf) / lanthanum (La) oxide may be used instead of the nitride film 12.

In addition, even in the case of the second oxide film 23, which is a lower tunneling oxide film, or the upper first oxide film 21, Al ₂ O ₃ , AlON, SBT, HfO ₂ , HfZrO, Zr-Silicates, Zr It may be replaced by -Si-Oxynitride or as a combination film.

In addition, the charge storage unit 20 may be replaced with a multi-layer form of ONONO (Oxide-Nitride-Oxide-Nitride-Oxide) in which the second nitride film and the third oxide film are deposited on top of the ONO structure.

The method of storing 1-Bit data according to the present invention according to the above configuration first prevents the increase of the threshold voltage due to residual charge by using a hot-hole erasure method or an FN erase method. After 5-9V at the gate G, 5-8V at the drain A (D1), and drain B (D2) are floating, the charge is stored toward the edge of the gate G adjacent to the drain A (D1). Be sure to

Similarly, in order for the charge to be stored at the edge of the gate G adjacent to the drain B (D2), 5 to 9 V and the drain A (D1) are floated to the gate G, and the drain B (D2) is 5 to 8 V do.

On the other hand, in order to reduce the voltage applied to the gate G or the source S / drains A and B (D1) ((D2), a reverse bias (0 V to -5 V) is applied to the silicon substrate 10.

The 1-Bit data stored in this way is read in the following way. For example, as described above, the method of reading the charge stored at the edge of the gate G adjacent to the drain A (D1) is 0.5V to 3V at the source S, the power supply voltage at the gate G, and the OV at the drain A (D1). Reverse method to read current flow by applying (Ground) and 0.5V ~ 3V to drain B (D2), supply voltage to gate (G), OV (Ground) to drain A (D1) to read current flow There is a way.

In the former case, the program direction and the reading direction are opposite to each other. In the latter case, the stored charge is read using the drain B (D2), which is a terminal not used in the program.

The method of simultaneously storing data of 2-Bit according to the present invention is as follows.

When 5 to 9 V is applied to the gate G, 0 to 3 V to the source S, and 5 to 8 V are respectively applied to the drain A (D1) and the drain B (D2) at the same time, the charges are generated by the channel hot electron injection (CHEI) method. It is stored at the edge of the gate G adjacent to the drains A, B (D1) and D2.

When the charge is stored in this manner, the time is significantly shorter than that of storing 2-bit data in the sequential method as in the prior art.

Here's how to read 2-Bit data.

The first is the presence of charge stored at the edge of the gate (G) adjacent to the drain A (D1) by applying 0.5V to 3V to the source S, the supply voltage to the gate G, and OV (Ground) to the drain A (D1). Is determined first, and then a source voltage of 0.5 V to 3 V is applied to the source S, a power supply voltage to the gate G, and OV (Ground) is applied to the drain B (D2), and the edge of the gate G adjacent to the drain B (D2) is determined. Determine if there is any charge stored on the page.

Another method is to simultaneously determine the charge of 2-Bit stored at the edges of the gate G adjacent to the drains A and B (D1) ((D2). Using B (D1) ((D2), OV (Ground) and source (S), apply 0.5V ~ 3V to determine the amount of current flowing. Since it is reduced to below, it has the advantage of reading 2-bit data at once.

A method of erasing the charge stored at the edge of the gate G adjacent to the drains A, B (D1) and D2 is as follows.

-5V to -9V is applied to the gate G, and 5 to 8V are applied to the drains A and B (D1) and D2.At the same time, when the source S is floated or formed as ground, 2-Bit data is simultaneously applied. It can be erased.

As described above, the present invention allows a pair of drains, ie, drains A (D1) and B (D2), to be simultaneously formed on both sides with the source S in the middle to simultaneously store and charge charges of 2-Bit during operation of 2-Bit. It can be erased, and the presence or absence of 2-bit can be determined at once.

On the other hand, while many matters have been described in detail in the above description, they should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention.

Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

As described above, according to the present invention, the unit cell includes one source S, two drain regions Drain A (D1) and Drain B (D2), one gate (G), the gate (G), and a silicon substrate. By improving the configuration that the charge storage unit 20 is provided between the (10), the data of the 1-Bit and multi-Bit can be simultaneously stored and erased during the operation of 1-Bit and multi-Bit There is a very useful effect of increasing the density.

Claims (20)

Silicon substrates each having drains A and B formed on both sides of the surface, and a source formed between the drains A and B; A charge storage unit including a first oxide film, a nitride film, and a second oxide film sequentially stacked on the silicon substrate while both ends of the drain A and the source and the drain B and the source overlap each other at the same time; And A conductive layer stacked on the charge storage unit to form a control gate; A nonvolatile semiconductor memory device comprising a unit cell. The nonvolatile semiconductor memory device of claim 1, wherein the nitride layer of the charge storage unit is formed of one of HfO ₂ , Al ₂ O ₃ , HfAlO, HfSiO, HfSiON, HfZrO, and HfZrON. The nonvolatile semiconductor memory device of claim 1, wherein the nitride layer of the charge storage unit is formed of a combination of HfO ₂ , Al ₂ O ₃ , HfAlO, HfSiO, HfSiON, HfZrO, and HfZrON. The nonvolatile semiconductor memory device of claim 1, wherein the charge storage unit has a multilayer structure in which a second nitride layer and a third oxide layer are stacked on the first oxide layer, the nitride layer, and the second oxide layer. The method of claim 1, wherein when the unit cell is programmed, 5 to 9 V is applied to the gate, 5 to 8 V is applied to the drain A, 0 V to 3 V is applied to the source, and the drain B is floated to store charge toward the edge of the gate adjacent to the drain A. Nonvolatile semiconductor memory device to store 1-bit data The nonvolatile semiconductor memory device of claim 5, wherein the data is stored by applying 0.5V to 3V to a source cell, a power supply voltage to a gate, and OV (Ground) to a drain A. 7. 6. The nonvolatile semiconductor memory device according to claim 5, wherein the unit cell reads data stored by applying 0.5V to 3V to drain B, a power supply voltage to a gate, and OV (Ground) to drain A. The method of claim 1, wherein when programming the unit cell, 5 to 9 V is applied to a gate, a drain A is floating, a source is applied to 0 V to 3 V, and a drain B is applied to 5 to 8 V, toward the edge of the gate adjacent to the drain B side. A nonvolatile semiconductor memory device in which charge is stored so that 1-bit data is stored. 10. The nonvolatile semiconductor memory device of claim 8, wherein the unit cell reads data stored by applying 0.5V to 3V to a source, a power supply voltage to a gate, and OV (Ground) to a drain B. 10. The nonvolatile semiconductor memory device of claim 8, wherein the unit cell reads data stored by applying 0.5V to 3V to drain A, a power supply voltage to a gate, and OV (Ground) to drain B. The method of claim 1, wherein 5 to 9 V, a drain A 5 to 8 V, a source 0 V to 3 V, and a drain B float to the gate during programming of the unit cell so that charge is stored toward the edge of the gate adjacent to the drain A. After the 1-Bit data is stored, the gate 5V, 9V, drain A is floated, the source is applied as 0V ~ 3V, and drain B is 5 ~ 8V to the edge of the gate adjacent to the drain B side A non-volatile semiconductor memory device which stores 2-bit data sequentially by allowing charge to be stored toward the 1-bit data. The method of claim 1, wherein 5 to 9 V, a drain A 5 to 8 V, a drain B 5 to 8 V, and a source 0 V to 3 V are applied to the gate of the unit cell when the unit cell is programmed to charge toward the edge of the gate adjacent to the drain A. Is stored and at the same time the charge is also stored toward the edge of the gate adjacent to the drain B to simultaneously perform 2-bit data. The method of claim 1, wherein the charge stored at the gate edges adjacent to the drains A and B in the unit cell applies -5V to -9V to the gate and floats the source while simultaneously applying 5 to 8V to the drains A and B. Or a nonvolatile semiconductor memory device capable of simultaneously erasing 2-bit data when grounded. 14. The method of claim 13, wherein in the unit cell, a threshold voltage output by applying 0.5V to 3V to the drain A, a power supply voltage to the gate, and an OV (Ground) to the drain B is equal to an initial threshold voltage. A nonvolatile semiconductor memory device for erasing verification. 15. The method of claim 13, wherein erase verification is performed by comparing whether or not a threshold voltage output by applying 0 V to the drain A, a power supply voltage to the gate, and 0.5 to 3 V to the drain B in the unit cell is equal to an initial threshold voltage. Nonvolatile Semiconductor Memory Device. The method of claim 14 or 15, wherein the erase completion operation in the unit cell is applied by applying 0V to the drain A and the drain B, and applying a voltage of 0.5V to 3V to the source to output an initial threshold voltage. A nonvolatile semiconductor memory device performed as being in the same state. The nonvolatile semiconductor of claim 1, wherein the first oxide layer of the charge storage unit is made of one of Al ₂ O ₃ , AlON, SBT, HfO ₂ , HfZrO, Zr-Silicates, and Zr-Si-Oxynitride to have a low threshold voltage. Memory device. The method of claim 1, wherein the first oxide layer of the charge storage unit is formed by a combination of Al ₂ O ₃ , AlON, SBT, HfO ₂ , HfZrO, Zr-Silicates, and Zr-Si-Oxynitride to have a low threshold voltage. Volatile semiconductor memory device. The non-volatile semiconductor of claim 1, wherein the second oxide layer of the charge storage unit is made of one of Al ₂ O ₃ , AlON, SBT, HfO ₂ , HfZrO, Zr-Silicates, and Zr-Si-Oxynitride to have a low threshold voltage. Memory device. 2. The ratio of claim 1, wherein the second oxide layer of the charge storage unit is formed by a combination of Al ₂ O ₃ , AlON, SBT, HfO ₂ , HfZrO, Zr-Silicates, and Zr-Si-Oxynitride to have a low threshold voltage. Volatile semiconductor memory device.