KR20040055250A - Liquid crystal display device for preventing point defect and fabricating method thereof - Google Patents

Abstract

PURPOSE: An LCD device for preventing dot inferiority is provided to form dummy lines adjacent to data lines, and to overlap pixel electrodes with a portion of the dummy lines, so that all pixels have identical parasitic capacitance, thereby improving screen display quality. CONSTITUTION: Data lines(215) and gate lines(210) are arrayed in vertical direction on a transparent substrate, and form plural pixel areas. TFTs(205) are formed on crossed points of the data lines(215) and the gate lines(210). Dummy lines(270) are formed abreast a portion of the data lines(215), and are electrically connected with the TFTs(205). Semiconductor layers(250) are formed on crossed points of the data lines(215) and the gate lines(210), and form channels of the TFTs(205). Pixel electrodes(220) are overlapped with a portion of the dummy lines(270) in the pixel areas, and are electrically connected to the TFTs(205).

Description

Liquid crystal display and manufacturing method thereof to prevent dot defects {LIQUID CRYSTAL DISPLAY DEVICE FOR PREVENTING POINT DEFECT AND FABRICATING METHOD THEREOF}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device in which the same parasitic capacitance is formed for all pixels.

In the liquid crystal display, a TFT substrate having a gate line and a data line arranged in a matrix form and having a thin film transistor (TFT) formed at an intersection thereof is bonded to the TFT substrate. A color filter substrate, a data driver positioned on one side of the TFT substrate and connected to the data line to apply a data signal, and a gate driver positioned on one side of the gate line and connected to the gate line to transfer a gate signal. It is configured to include.

Referring to the operation of the liquid crystal display, when an arbitrary pixel is switched by a switch element, the pixel transmits light of a light source. The switch element is mainly composed of a TFT in which a semiconductor layer is formed of amorphous silicon.

1 is a plan view showing a part of a TFT substrate of a conventional liquid crystal display device.

As shown in the drawing, each pixel includes a pixel electrode 120 formed in a pixel region defined by the gate wiring 110 and the data wiring 120 crossing each other. A TFT 105 is provided at the intersection of the gate wiring 110 and the data wiring 120. A part of the gate wiring 110 constitutes a gate electrode 160 of the TFT 105, and data A portion of the wiring 120 constitutes a source electrode 130 of the TFT 105. When the TFT 105 is turned on by the gate voltage applied to the gate electrode 160 of the gate wiring 110, the data voltage applied to the source electrode 130 of the data wiring 120 is drained. It is delivered to the electrode 140 to apply a voltage to the pixel electrode 120.

The TFT 105 is provided with a semiconductor layer 150 to form a channel of the TFT 105. The semiconductor layer 150 is formed under the data line 115, which reduces the step difference between the gate line 110 and the data line 115 so that the data line 115 is smoothly formed.

In the pixel region, the storage capacitor electrode 125 for maintaining the pixel voltage is provided in parallel with the gate wiring 110. Recently, a method in which the storage capacitor electrode is formed on the gate wiring 110 may be used.

However, in the conventional LCD, the pixel electrode 120 is formed after the data line 115 is formed. However, due to a process error, the distance between the data line 115 and the pixel electrode 120 is not constant for all pixels. There was no problem. That is, the distance between the data line 115 and the pixel electrode 120 in two adjacent pixels may not coincide with d1 and d2 as shown in the drawing.

Parasitic capacitance occurs between the data wiring 115 and the pixel electrode 120, and the parasitic capacitance is inversely proportional to the distance between the pixel electrode 120 and the data wiring 115. Accordingly, a difference in parasitic capacitance occurs for each pixel, and thus, a load on each pixel is changed and a voltage difference occurs, thereby degrading display quality of the screen.

In addition, when the process of forming the semiconductor layer 150 and the process of forming the pixel electrode 120, the semiconductor layer 150 is in contact with the pixel electrode 120 by a misalignment of a mask. The phenomenon occurred. When the data line 115 and the pixel electrode 120 are in contact with each other, even if the TFT 105 is turned off, the data voltage is applied to the pixel electrode 120 through the semiconductor layer 150 to control the liquid crystal with the correct pixel voltage. There will be no. Therefore, such a pixel has a problem in that data of wrong luminance is continuously displayed while the liquid crystal display is being driven.

In order to solve the above problems, an object of the present invention is to provide a liquid crystal display device having the same parasitic capacitance for all pixels and a manufacturing method thereof.

Another object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, in which the semiconductor layer and the pixel electrode minimize contact risk.

Other features and objects of the present invention will be described in detail in the configuration and claims of the invention below.

1 is a plan view showing a part of a TFT substrate of a conventional liquid crystal display device;

Fig. 2 is a plan view showing a part of the TFT substrate constituting the liquid crystal display device according to the embodiment of the present invention.

3 is a cross-sectional view taken along the line III-III of FIG. 2;

4 is a cross-sectional view taken along the line IV-IV of FIG. 2.

5A through 5D are plan views illustrating a method of manufacturing a liquid crystal display device according to an exemplary embodiment of the present invention.

*** Explanation of symbols for the main parts of the drawing ***

105.205: Thin film transistors 110, 210: Gate wiring

115, 215: data wiring 120, 220: pixel electrode

125, 225: storage capacitor electrode 130, 230: source electrode

140 and 240: drain electrodes 150 and 250: semiconductor layers

160 and 260: gate electrode 270: dummy wiring

300: transparent substrate 310: repair wiring

320: gate insulating film 330: protective film

In order to achieve the above object, the present invention provides a semiconductor device comprising: data and gate wiring arranged vertically and horizontally on a transparent substrate to form a plurality of pixel regions; A thin film transistor formed at an intersection point of the data line and the gate line; A dummy line formed in parallel with a portion of the data line and electrically connected to the thin film transistor; A semiconductor layer formed at an intersection point of the data line and the gate line to form a channel of the thin film transistor; And a pixel electrode formed to overlap a portion of the dummy wiring in the pixel area and electrically connected to the thin film transistor.

The thin film transistor may include a gate electrode formed as part of the gate wiring; A gate insulating film on the gate electrode; A semiconductor layer on the gate insulating layer; And a source electrode formed as a part of the data wiring on the semiconductor layer and a drain electrode spaced apart from the source electrode by a predetermined distance, wherein the dummy wiring preferably includes a drain electrode of the thin film transistor.

The storage device may further include a storage capacitor electrode parallel to the gate wiring, and the dummy wiring extends above the storage capacitor electrode to form a storage capacitor.

It is preferable that the semiconductor layer is not formed in a region other than the region in which the thin film transistor is formed.

It is preferable to further include a repair wiring formed under a portion of the data wiring.

In addition, the present invention comprises the steps of forming a plurality of gate wiring including a gate electrode on a transparent substrate to achieve the above object; Forming a gate insulating film on the transparent substrate on which the gate wiring is formed; Forming a semiconductor layer on the gate insulating layer to overlap the gate electrode; Forming a plurality of data wires including a source electrode, a drain electrode, and a drain wire parallel to a portion of the data wires so as to be orthogonal to the gate wires; Forming a protective film on the transparent substrate on which the data wiring is formed; And forming a pixel electrode in the pixel region formed by the gate wiring and the data wiring.

It is preferable to form a repair wiring located under a portion of the data wiring while forming the gate wiring.

It is preferable to form the plurality of storage capacitor electrodes parallel to the gate wiring while forming the gate wiring.

It is preferable to form the storage capacitor by extending the dummy wiring over the storage capacitor electrode.

Preferably, a contact hole is formed in the passivation layer formed on the drain electrode, and the pixel electrode is electrically connected to the drain electrode through the contact hole.

According to the exemplary embodiment of the present invention, all the pixels have the same parasitic capacitance, so that the screen display quality is improved, and the dummy wiring and the semiconductor layer are short-circuited so that there is no fear of occurrence of spot defects.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view showing a part of the TFT substrate constituting the liquid crystal display device according to the embodiment of the present invention.

The data line 215 and the gate line 210 are arranged on the transparent substrate vertically and horizontally to form a plurality of pixel regions. In addition, the storage capacitor electrode 280 is formed in parallel with the gate wiring 210.

The TFT 205 is formed at the intersection of the data line 215 and the gate line 210. A portion of the gate wiring 210 forms a gate electrode 260 of the TFT 205, and a portion of the data wiring 215 forms a source electrode 230 of the TFT 205. In addition, the drain electrode 240 is formed at a predetermined distance from the source electrode 230. The semiconductor layer 250 is formed under the source electrode 230 and the drain electrode 240 to form a channel when the TFT 205 is turned on.

As shown in the drawing, the drain electrode 240 extends along the periphery of the pixel region to form the dummy wiring 270. The dummy wiring 270 is formed in parallel with a portion of the data wiring 215. A portion of the dummy wiring 270 overlaps with the storage capacitor electrode 280 and the insulating film therebetween to form the storage capacitor.

The dummy wiring 270 is simultaneously formed when the data wiring 215 is formed. That is, since it is formed by patterning using the same mask, the distance between the data line 215 and the dummy line 270 parallel thereto is always constant. That is, as shown in the figure, the distance between the dummy wiring 270 on the left and the data wiring 215 is constant at d4 for one pixel, and the distance between the dummy wiring 270 and the data wiring 215 on the right is constant. The interval is constant at d3. Accordingly, the same parasitic capacitance is formed for all the pixels without fear of changing the parasitic capacitance for each pixel due to misalignment of the mask.

The semiconductor layer 250 constituting the TFT 205 is formed only near the intersection of the data line 215 and the gate line 210, and is not formed below the entire data line 215 as in the prior art. According to the exemplary embodiment of the present invention, since the dummy wiring 250 is formed in parallel with the data wiring 215, the semiconductor layer 250 may be dummy wiring due to misalignment of the mask during the formation process of the semiconductor layer 250. This is because there is a risk that the data line 215 and the dummy line 270 are shorted because they are formed under the 270. When the data line 215 and the dummy line 270 are short-circuited, even if the TFT 205 is turned off, a data voltage is applied to the pixel electrode 220, so that the liquid crystal cannot be controlled with the correct pixel voltage. Since the semiconductor layer 250 extends to the intersection of the data line 215 and the gate line 210, a sudden step between the data line 215 and the gate line 210 can be prevented. Therefore, the data line 215 can be formed smoothly on the gate line 210.

3 is a cross-sectional view taken along line III-III of FIG. 2.

The cross section of the area | region which does not contain TFT is shown.

The repair wiring 310 is formed on the transparent substrate 300, and the gate insulating layer 320 is formed on the transparent substrate 300 to cover the entire surface of the transparent substrate 300. A dummy line 270 is formed on both sides of the data line 250 and the data line 250, and a passivation layer 330 is formed on the gate insulating layer 320. A transparent electrode is formed on a portion of the passivation layer 330 to form the pixel electrode 225.

The pixel electrode 225 may be formed to overlap a portion of the dummy wiring 270. Since the pixel electrode 225 and the dummy wiring 270 are electrically connected to each other through a contact hole formed in the TFT, they have the same potential. When the pixel electrode 225 is formed to overlap with the entire dummy wiring 270, the pixel electrode ( This is because the parasitic capacitance of each pixel is formed differently according to the formation position of 225. That is, the distance of d3 or d4 in the drawing is reduced. Therefore, in order to secure the maximum aperture ratio, the pixel electrode 225 must be formed to overlap a part of the dummy wiring 270.

The repair wiring 310 is a wiring for recovering a damaged portion when the data wiring 250 is damaged, and is formed under a portion of the data wiring 250. When the data wiring 250 above the repair wiring 310 is damaged and disconnected, the data voltage is repaired by shorting the data wiring 250 and the repair wiring 310 of the damaged portion by laser welding technology. It may be applied through the wiring 310.

4 is a cross-sectional view taken along line IV-IV of FIG. 2.

4 is a cross-sectional view of a region including a TFT, and the same reference numerals are used for the same parts as in FIG. 3, and description thereof will be omitted.

The gate wiring protrudes on the transparent substrate 300 to form the gate electrode 260, and the semiconductor layer 250 is formed with the gate insulating layer 320 interposed therebetween. The source electrode 230 and the drain electrode 240 are formed on both sides of the semiconductor layer 250. Although not shown, a high concentration n ⁺ doped ohmic contact layer is formed between the source electrode 230 and the drain electrode 240 and the semiconductor layer 250.

A contact hole 400 is formed in the passivation layer 330 on the drain electrode 240, and the pixel electrode 225 is connected to the TFT through the contact hole 400.

After the gate pulse is applied to the gate electrode 260 to activate the semiconductor layer 250 to form a channel, when the data voltage is applied to the source electrode 230 through the data wiring, the data voltage is applied to the drain electrode 240 through the channel. Is passed).

The manufacturing method of the liquid crystal display device having the above configuration is as follows.

5A through 5D are plan views illustrating a method of manufacturing a liquid crystal display device according to an exemplary embodiment of the present invention.

First, as shown in FIG. 5A, a gate wiring 210, a storage capacitor electrode 280, and a repair wiring 310 are formed on a transparent substrate. Chromium (Cr) may be used as the material of the wirings 210 and 310 and the electrode 280, and after deposition by sputtering, is patterned by a photolithography process. 5A shows the state after patterning.

Thereafter, as shown in FIG. 5B, a gate insulating layer, a semiconductor layer 250, and an ohmic contact layer are formed. The gate insulating layer is formed by continuously depositing SiNx, the semiconductor layer is amorphous silicon, and the ohmic contact layer is a high concentration n ⁺ doped amorphous silicon by PECVD (Plasma Enhanced Chemical Vapor Deposition) method. After forming three thin films as described above, a pattern of the semiconductor layer 250 is formed by a photolithography process using a mask on which a pattern of the semiconductor layer is formed. As shown in the figure, the semiconductor layer 250 is formed only in the region where the TFT is to be formed and in the vicinity thereof. Other portions are removed by dry etching using SF ₆ or the like.

Next, as illustrated in FIG. 5C, the data wiring 215, the source electrode 230, the drain electrode 240, and the dummy wiring 270 are formed. The wirings 215 and 270 and the electrodes 230 and 240 are formed by depositing and patterning chromium by the same sputtering method as when the gate wiring 210 is formed. Since the data wires 215 and the dummy wires 270 are patterned by the same mask, the distance between the two wires 215 and 270 is always constant even if the mask is misaligned. Therefore, it is possible to secure a constant parasitic capacity.

After the protective film is formed to protect the TFT, the pixel electrode 220 is formed in each pixel region as shown in FIG. 5D. The protective film prevents the channel of the TFT from being contaminated from moisture and ionic material. SiNx is mainly used as a protective film and is deposited by PECVD. The pixel electrode 220 is formed by depositing and patterning a transparent electrode such as indium tin oxide (ITO) by a sputtering method. The pixel electrode 220 is formed to overlap a portion of the dummy wiring 270 as described above. This is because when the dummy wiring 270 approaches the data wiring 215 beyond the region where the dummy wiring 270 is formed, a gap between the data wiring 215 and the pixel electrode 220 may occur for each pixel to maintain the same parasitic capacitance. Therefore, in order to maintain the same parasitic capacitance and to secure the maximum aperture ratio, the pixel electrode 220 may be formed to overlap a part of the dummy wiring 270.

When the TFT substrate formed as described above and the color filter substrate on which the color filter is formed are bonded together with the liquid crystal layer interposed therebetween, the liquid crystal display device according to the embodiment of the present invention is completed.

While many details are set forth in the foregoing description, it should be construed as an illustration of preferred embodiments rather than to limit the scope of the invention. Therefore, the scope of the invention should not be defined by the described embodiments, but should be defined by the claims and the equivalents of the claims.

According to the present invention has the following effects.

First, the dummy wiring is formed adjacent to the data wiring and the pixel electrode is overlapped with a part of the dummy wiring so that all the pixels have the same parasitic capacitance, thereby improving the screen display quality.

Second, since the semiconductor layer is formed only in and around the region where the TFT is formed, there is no fear that the dummy wiring and the semiconductor layer are short-circuited to display wrong image data.

Claims (10)

Data and gate wirings arranged vertically and horizontally on a transparent substrate to form a plurality of pixel regions; A thin film transistor formed at an intersection point of the data line and the gate line; A dummy line formed in parallel with a portion of the data line and electrically connected to the thin film transistor; A semiconductor layer formed at an intersection point of the data line and the gate line to form a channel of the thin film transistor; And And a pixel electrode formed to overlap a portion of the dummy wiring in the pixel region, the pixel electrode being electrically connected to the thin film transistor. The thin film transistor of claim 1, wherein the thin film transistor comprises: a gate electrode formed as part of the gate wiring; A gate insulating film on the gate electrode; A semiconductor layer on the gate insulating layer; And a source electrode formed as a part of data wiring on the semiconductor layer and a drain electrode formed to be spaced apart from the source electrode at a predetermined interval. The dummy wiring line is a liquid crystal display device to prevent the dot defect, characterized in that the drain electrode of the thin film transistor is extended. The method of claim 1, further comprising a storage capacitor electrode parallel to the gate wiring, And the dummy wiring extends above the storage capacitor electrode to form a storage capacitor. 2. The liquid crystal display of claim 1, wherein the semiconductor layer is not formed in an area except for a region where a thin film transistor is formed. The liquid crystal display of claim 1, further comprising a repair wiring formed under a portion of the data wiring. Forming a plurality of gate wirings including a gate electrode on the transparent substrate; Forming a gate insulating film on the transparent substrate on which the gate wiring is formed; Forming a semiconductor layer on the gate insulating layer to overlap the gate electrode; Forming a plurality of data wires including a source electrode, a drain electrode, and a drain wire parallel to a portion of the data wires so as to be orthogonal to the gate wires; Forming a protective film on the transparent substrate on which the data wiring is formed; And And forming a pixel electrode in the pixel region formed by the gate wiring and the data wiring. 7. The method of claim 6, wherein a repair wiring formed under a portion of the data wiring is formed at the same time as the gate wiring is formed. 7. The method of claim 6, wherein the gate wiring is formed and a plurality of storage capacitor electrodes parallel to the gate wiring are formed. 10. The method of claim 8, wherein the dummy wiring extends over the storage capacitor electrode to form a storage capacitor. The method of claim 6, wherein a contact hole is formed in the passivation layer formed on the drain electrode, and the pixel electrode is electrically connected to the drain electrode through the contact hole.