KR20040052409A - Method of improving data retention for MLC flash memory - Google Patents

Abstract

The present invention provides sufficient margin between the states by moving the erase Vt to a negative region in order to improve data retention performance of a flash memory, in particular, a MLC flash memory device. The present invention relates to a method for improving data retention of a multilayer cell flash memory, which is configured to automatically refresh as necessary in order to avoid degradation of data retention.

Description

{Method of improving data retention for MLC flash memory}

The present invention provides sufficient margin between the states by moving the erase Vt to a negative region in order to improve data retention performance of a flash memory, in particular, a MLC flash memory device. The present invention relates to a method for improving data retention of a multilayer cell flash memory, which is configured to automatically refresh as necessary in order to avoid degradation of data retention.

In the MLC type (multi-level) flash memory, the "read" margin is narrow, there is a disadvantage that the data retention (vulnerability) is weak. In other words, the conventional SLC type flash memory that stores 1 bit per cell has only two data states of '1' and '0', so the Vt margin of each state is relatively large. In the case of an MLC type flash memory that stores two bits per cell (see FIG. 1A), four data states of '11' '10' '01' '00' (the intervals between these states are determined. Since the window must be within a limited Vt region, it is necessary to read the state of the cell with a narrow Vt margin of about half that of SLC (see FIG. 1B). The reading method of MLC detects each level ('11' '10' '01' '00') compared to the main cell with a read reference cell having Vt of about 3V, 4V, and 5V (one example value). (sensing)

In summary, the conventional MLC flash memory has a great advantage of storing two bits or more in one cell (see FIG. 1B) compared to the SLC (FIG. 1A), which stores only one bit of information in one cell. There is a problem of "read disturb or stress" and "write disturb or stress" due to margins between states, and thus deterioration of data retention.

In order to solve this problem, the present invention provides a sufficient margin (window) between the states by moving the erase Vt to a negative area in the MLC type flash memory, but in order to avoid the deterioration of data retention caused at this time. Accordingly, an object of the present invention is to provide a method for improving data storage of a multilayer cell flash memory, which is configured to be automatically refreshed accordingly.

1A is a Vt distribution diagram of an SLC flash memory.

1B is a Vt distribution diagram of a conventional MLC flash memory.

2 is a Vt distribution diagram of an MLC flash memory according to the present invention;

3 is a Vt distribution diagram for explaining the meaning of "stress".

4a, b, c, d are hardware block diagrams for implementing the method according to the present invention.

5 is a Vt sensing method of an erase reference cell.

6 is a Vt detection method diagram of a write reference cell.

Basic principles of the invention

In the conventional MLC cell (FIG. 1B), Vt is set to about 3 V at the time of erasing because the distortion due to the current leakage component can be eliminated in the write or read operation. However, in this case, the above-described problem (the inter-state spacing (i.e., the window size) becomes narrow) occurs, so that if Vt at the time of cell erasing is brought to the negative region (for example, -2V) (see Fig. 2). The distance from the highest Vt (e.g. 6V) for writing to the cell is close to the spacing in the SLC device (e.g., Vt at cell erase is 2V, Vt at write is 4V) (see Figure 1a). Will be done. Therefore, even in the case of the MLC device will have a read margin and data retention performance equivalent to the characteristics of the SLC device.

However, this can cause another problem. As in the above assumption, the MLC erased by the negative Vt takes a relatively higher gate voltage than the SLC or the conventional MLC. That is, in case of SLC, a gate bias of about 4V is required at the time of “reading”, so when the cell erase Vt is 2V, there is a difference of about 2V between the gate bias and Vt, and in the conventional MLC, when the cell erase Vt is 3V. The gate bias at "read" is about 5.5V, which is a difference of about 2.5V. However, in the case of MLC having a negative erase Vt as in the present invention, -2V, which is Vt at the time of cell erasing, and "read" are There is a 7.5V difference between the gate bias of 5.5V. For this reason, data retention may be relatively weak due to "read gate stress" or "program gate stress". (Bias voltages described above are exemplary and may differ slightly in practical applications.)

Here, the stress is a force ("read gate stress" or "data gain") that the state of '11', which is negative Vt (in response to the action to return to the UV state), transitions in the positive direction as shown in FIG. And the state of '00', which is the maximum Vt, means the force ("write gate stress" or "data loss") to transition in the negative direction (in response to the action of returning to the UV state). Well known theory in the field).

Problems that may occur in the above-mentioned concept for solving the basic problem of the present invention (ie, extending the erase Vt to a negative area to secure a margin (window size) between levels), that is, "read gate stress" or " In order to eliminate the write gate stress, a refresh is automatically performed. Originally, since the flash memory is a nonvolatile memory, refreshing is unnecessary. Refresh was a necessary feature for traditional volatile memory because the data is lost when power is removed. However, in the present invention, this refresh function is actively adopted in the flash memory to solve the "read gate stress" or "write gate stress" inevitably accompanied by the present invention.

The automatic refresh function used in the present invention monitors a reference cell (described in detail later) and detects degradation of data retention such as "read gate stress" and "write gate stress" of the main cell. This function informs the user that a refresh is necessary and allows the user to refresh the flash memory device as needed (depending on the circuit design configuration).

In summary, in the present invention, the conventional MLC uses the erase Vt of about 3V as the negative Vt of about -2V to obtain a wide window size (margin between levels) to secure cell margin. (See Figure 2). On the other hand, despite the great advantage of widening the window of the MLC flash memory to secure the margin between levels, the data caused by the increase of the "read gate stress" and "write gate stress" of the cell erased by the negative Vt. The problem of deterioration in storage is solved by the automatic refresh function.

See specifically. As shown in Fig. 3, the cell most vulnerable to read gate stress in the present invention is an erased cell. The Vt of this cell can be set to about -2V in accordance with the present invention. In this case, the selected word line is subjected to a read gate stress of 6 V, which is a significant stress compared to that of a 6 V read gate stress in an erased cell having Vt = 3 V in the conventional MLC (FIG. 1B). For the same reason, erased cells are most vulnerable to write stress. That is, a cell erased with negative Vt on the same word line is subjected to gate stress of about 8V or more. Also, the erased cell is vulnerable in terms of data retention (see FIG. 3).

Representing a main cell, an erase reference cell and a write reference cell are added to determine how much the Vt level has moved due to the read gate stress, the write gate stress, and the data storage effect. The erase reference cell represents the weakest erase main cell and the write reference cell represents a cell written at a high Vt ('00' level). In addition, the Vt of the erase reference cell and the write reference cell are respectively a predetermined value (for example, , + 0.1V, -0.1V) adds a base cell to determine the change. The base cell must maintain the most stable cell state in terms of stress and data retention. Therefore, the base cell should not be subjected to read gate stress and write gate stress as much as possible, and it is preferable to have a stable UV cell Vt in terms of data retention.

As the reference cell, a cell having an erasable level of Vt (ert level Vt) is used. For example, if the erase verify Vt of the main cell is -2V, the reference cell uses a slightly lower -3V cell. That is, it is used to make it more vulnerable than the erase cell applied to the main cell. When the Vt of the erasing reference cell changes by a certain amount due to read gate stress, write gate stress, and data retention problems (for example, when the voltage rises 0.1V), the user is informed via a status bit. That is, by informing the user in advance that a problem may occur in the reliability of the cell, the user may block the reliability problem of the cell in advance through a refresh operation.

Alternatively, it is possible to have more read gate stresses than the main cell receives. For example, a read gate stress is applied to the erase reference cell for each read operation of the main cell. As a result, when a main cell of several addresses is read, a specific cell of one address of the main cell receives one read gate stress, but the erase reference cell receives several read gate stresses.

In addition, if the maximum read operation voltage is about 5.5V in the case of the main cell, the gate bias of the erase reference cell may be applied to 7V. In this case, the drain cell is set slightly higher than the main bias cell so that the reference cell is placed in a severe stress condition than the main cell. These methods are intended to induce a refresh operation stably by bringing the Vt change of the erase reference cell before the main cell fails by making the erase reference cell weaker than the main cell.

On the other hand, the erased cells are the most vulnerable to data retention and read gate stress, but the cells written at high Vt ('00' level) are not negligible. The unselected wordline takes about -3V when reading the MLC (wide window) according to the present invention. Therefore, if Vt of the written cell is 6V, the gate of the unselected cell takes about -3V, which is a significant amount of stress condition. Therefore, by adding a write reference cell, when the Vt of the write reference cell changes by -0.1V, the user is informed of the status bit information. Of course, if Vt of the cell written as high Vt is about 6V, Vt of the write reference cell is used as about 7V.

Alternatively, the read gate stress can be greater than the main cell receives. This applies in the same way as the principle applied to the erase reference cell. For example, each read operation of the main cell applies a read gate stress of -3V or less to the write reference cell. All of these methods make the write reference cell more vulnerable than the main cell so that the Vt of the reference cell changes before the main cell fails, thereby stably inducing the refresh operation.

<The realization apparatus and operation of this invention>

Now, an apparatus for realizing the basic principle of the present invention described above will be described and the operation thereof will be described. Each block is configured as shown in FIG. The number of erase reference cells (erasure reference cells) 41, write reference cells (program reference cells) 42, and base cells 43 are characteristics of the sense amplifiers (S / A) 44a and 44b. And one or an array structure according to cell characteristics and device characteristics. It is preferable that the characteristics of the S / As 44a and 44b are excellent, and it is sometimes helpful to adjust the number of the aforementioned reference cells.

The analog block 45 is connected because an analog bias for erasing, programming, and sensing of the reference cells is required. There is also a control block 46 which performs write, erase and sense functions. Of course, the logic unit for outputting the status bit 47 according to the detected result is also included in the excitation 46.

With this configuration, each reference cell is initially set to an appropriate Vt. Thereafter, the base cell and the erase reference cell are compared to check whether the Vt of the erase reference cell is shifted by 0.1V. If the shift is more than + 0.1V, the status bit 47 is sent to the output pin through the control block 46. 5 schematically illustrates a method of detecting a change of + 0.1V. -0.9V is applied to the gate of the erasing reference cell and 6V is applied to the gate of the base cell to detect that the Vt of the erasing reference cell is shifted to -2.9V due to stress and data retention. The user only needs to check the status bit 47 and refresh the main cell when the signal comes out for refresh. Similarly, the refresh status bit is emitted even when the Vt of the write reference cell is shifted by -0.1V. Of course, in this case, the user performs the refresh operation of the main cell.

Fig. 6 shows an example of sensing a -0.1 V shift of the write reference cell. In Fig. 6, 6V is applied to the gate of the base cell and 8.9V is applied to the gate of the write reference cell. The number of operations of such refresh is determined according to the conditions of the base cell, erase reference cell, and write reference cell.

4B shows a specific embodiment of the erasing reference cell sense amplifier 44a, and FIG. 4C shows a specific embodiment of the write reference cell sense amplifier 44b. 4D shows an array structure of the erase reference cell 41, the write reference cell 42, and the base cell 43. 4b to c show only one example of concrete implementation of each part of FIG. 4a.

While the present invention has been described with reference to the drawings as an embodiment, the technical scope of the present invention is not limited to the above-described embodiments. For example, the technical scope of the present invention applies not only to 2-bit MLC but also to more MLCs (eg, 4-bit per cell, 8-bit per cell, etc.) or the existing 1-bit per cell format. Therefore, the technical scope of the present invention is not limited by the description of the above embodiments, but is determined by the equivalent interpretation of the appended claims.

As described above, according to the present invention, in order to solve various stresses and degradation of data retention caused by the narrow margin between the levels of the existing MLC, the erase Vt is extended to the negative region to secure the margin between levels and introduce the automatic refresh function. As a result, failure of the flash memory due to various stresses and data preservation can be prevented in advance, thereby greatly improving data reliability.

The basic purpose of the present invention is to secure the data reliability of the main cell from various stresses and data storage properties such as the read gate stress and the write gate stress of the main cell, and in advance to solve the problem of deterioration of data retention which is guaranteed for at least 10 years. I want to block. For example, assuming that an existing MLC product has 10 years of data retention, if the method of the present invention is applied, an additional 10 years of data retention is guaranteed by performing one refresh within 10 years, and then again after 10 years. Refreshing ensures additional reliable use. Of course, due to various cycling effects, the initial guaranteed 10 years is not completely reclaimed after one refresh, but the breakthrough guarantee of reliability is ensured by informing the user to refresh automatically before the problem with the reliability of the main data occurs. Will receive. The present invention can dramatically improve the characteristics of a flash memory whose data reliability is life.

Claims (5)

A method of improving data retention of a multilayer cell flash memory, characterized in that the window size between Vt levels is increased by moving the main cell erase voltage Vt of the MLC flash memory to a negative region. The method according to claim 1, wherein the main cell is refreshed when the shift amount of Vt is monitored and shifted by a predetermined value or more. In MLC flash memory, Extending the erase voltage Vt of the main cell to a negative region; In addition to the main cell, an erase reference cell and a write reference cell for determining how much the Vt level has moved on behalf of the main cell, and a base cell for determining that the Vt of the erase reference cell and the write reference cell have changed by predetermined values, respectively, are provided. step, Setting Vt appropriate for the functions of the erase reference cell, write reference cell, and base cell; Checking whether the Vt of the erasing reference cell has shifted from the set value, and if it has shifted more than a predetermined value, outputting a status bit; Checking whether the Vt of the write reference cell has shifted from the set value, and if it shifts more than a predetermined value, outputting a status bit; And refreshing the main cell when the status bit is sensed. 4. The method of claim 3, wherein the Vt of the erase reference cell is lower than the erase Vt of the main cell to make the stress condition worse than that of the main cell. The method according to claim 3, wherein the Vt of the write reference cell is made higher than the write Vt of the main cell to make the stress condition worse than that of the main cell.