KR20040041264A - Pixel array for Infrared Ray Detector with thin film transistor and method for fabrication of the same - Google Patents

Abstract

The present invention is to provide an infrared sensor pixel and a manufacturing method thereof suitable for preventing the sensed infrared information is attenuated within a short time due to heat conduction, the infrared sensor pixel of the present invention includes an electrode for the infrared readout circuit A semiconductor substrate including an infrared reading integrated circuit, an infrared sensing unit spaced with an air gap on the semiconductor substrate, and a conductive connection electrode connecting the infrared sensing unit and the electrode for the infrared reading circuit, the gas or infrared Since the TFT structure in which the transistor drain current is changed by the gate for detecting the light is separated from the semiconductor substrate by the vacuum or the air gap, the sensed information is prevented from being attenuated by the heat conduction in a short time. Can be.

Description

Pixel array for Infrared Ray Detector with thin film transistor and method for fabrication of the same}

The present invention relates to an infrared thermal imaging apparatus, and more particularly to an infrared sensor pixel.

The operation of a general infrared thermal imaging apparatus detects an image according to a heat from an object to be imaged by an infrared sensor, and applies the detection unit to convert the thermal image into an electrical analog signal by horizontally scanning the thermal image with a vertical scan. The electrical analog signal detected by the detection unit is converted into a digital signal, processed into a signal for image output, and then processed into an analog signal and outputted as an image.

1 is a view showing a pixel for an infrared sensor according to the prior art. 1 is according to the Republic of Korea Patent Publication No. 91-7142.

Referring to FIG. 1, a gate electrode 12 is positioned on a glass substrate 11, a gate insulating film 13 and a semiconductor layer 14 are positioned on a gate electrode 12, and a semiconductor layer 14 is disposed on a semiconductor substrate 14. The source electrode 16 and the drain electrode 17 are positioned with the insulating film 15 interposed therebetween. Incident light 18 is incident on the gate electrode 12 side.

However, in the infrared detector of FIG. 1, when the amount of light changes rapidly with time, it is difficult to implement the detector array because a drain current for detecting the amount of light exists only within a short time.

2 is a view showing a pixel for an infrared sensor according to the prior art. 2 is from the Republic of Korea Patent Publication No. 2001-26737.

Referring to FIG. 2, in the infrared sensor pixel, the ferroelectric 22 is positioned on the infrared absorber 20 with the partition wall 21 interposed therebetween, and the semiconductor thin film is provided on the ferroelectric 22, and the dopant is doped in the semiconductor thin film. Doping is performed to form the source region 23a, the drain region 23b, and the channel region 23c. The conductor pads 24a and 24b are formed on the outer surfaces of the source region 23a and the drain region 23b, respectively, and the insulating film 25 is formed on the conductor pads 24a and 24b and the channel region 23c. A metal contact 26 is formed to be connected through.

On the other hand, the pixels should be connected to a substrate 27 on which an infrared read-out integrated circuit (ROIC) is formed. In order to block heat transfer to each pixel, a mesa structure 28 is manufactured. do. That is, the mesa structure 28 is fabricated on the substrate 27, and metal pads 29 for connecting to the metal contacts 26 of the cells are fabricated on the upper surface of the mesa structure 28. Once the mesa structure 28 and the metal pads 29 are completed on the substrate 27, they are bonded or soldered to the aforementioned pixels.

However, since the infrared sensing TFT structure and the readout circuit board are electrically and physically connected by bonding or soldering formed between the two structures, the TFT structure and the readout circuit board are separately manufactured and hybrid assembled. This is complicated.

The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide an infrared sensor pixel and a method for manufacturing the same, which are suitable for preventing the sensed infrared information from being attenuated in a short time due to heat conduction.

1 is a vertical cross-sectional view showing a conventional TFT type light sensor,

Figure 2 is a vertical cross-sectional view showing a conventional ferroelectric infrared sensor,

3 is a vertical cross-sectional view of a unit pixel for an infrared sensor having a TFT type structure according to an embodiment of the present invention;

4 is a plan view of a pixel array for an infrared sensor of the TFT type structure of FIG.

5A to 5J are cross-sectional views taken along line AA ′ of FIG. 4;

6 is a vertical sectional view of a unit pixel for an infrared sensor having a TFT type structure according to another embodiment of the present invention;

7 is a plan view of a pixel array for an infrared sensor of the TFT structure of FIG.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 electrode for infrared reading circuit

33a, 33c: silicon nitride film 33b: silicon oxide film

36: insulating side wall 37a: connecting electrode

39: gate insulating film 40: infrared sensing layer

41: infrared absorption layer 42a: source region

43a: drain region 45: channel region

46: third insulating film 47: isolation groove

48: air gap

The infrared sensor pixel of the present invention for achieving the above object is a semiconductor substrate formed with an integrated infrared readout circuit including an electrode for the infrared readout circuit, an infrared detector spaced apart with an air gap on the semiconductor substrate, and the infrared And a conductive connection electrode connecting the sensing unit and the electrode for the infrared readout circuit, wherein the infrared sensing unit includes a silicon semiconductor layer, a gate insulating film on the silicon semiconductor layer, and an infrared sensing layer and an infrared light on the gate insulating film. A TFT including a gate in which an absorption layer is stacked, a channel region in the silicon semiconductor layer below the gate, and a source region and a drain region overlapping at one end of the gate and provided in the silicon semiconductor layer between the channel regions. Characterized in that, the infrared detection unit, a silicon semiconductor layer, A gate insulating film on the silicon semiconductor layer, a gate in which the infrared sensing layer and an infrared absorption layer are stacked on the gate insulating film, a channel region in the silicon semiconductor layer below the gate, and one end of the gate overlaps the end of the gate The TFT may include a source region and a drain region provided in the silicon semiconductor layer between regions, and the infrared sensing unit may include an array of one or more sensing layers.

In addition, the method of manufacturing an infrared detector pixel according to the present invention comprises the steps of forming an integrated infrared readout circuit including an infrared readout circuit electrode on a semiconductor substrate, a layer that is relatively etched on the semiconductor substrate as compared to upper and lower layers. Forming a stacked insulating film interposed therebetween, forming a hole for exposing the electrode for the infrared reading circuit by etching the laminated insulating film, forming an insulating side wall in the inner wall of the hole, and forming the insulating side wall in the hole. Forming a connecting electrode surrounded by the insulating layer, forming an infrared sensing unit connected to the connecting electrode on the laminated insulating film, forming a protective film surrounding the infrared sensing unit, and forming an upper layer of the protective layer and the laminated insulating film. Etching to form a passage of the etching solution on the edge of the infrared sensing unit And forming an air gap under the infrared sensing unit by etching the intermediate layer of the multilayer insulating layer by introducing an etching solution through the passage. The upper and lower layers of the multilayer insulating layer, the protective layer and The insulating side wall is a silicon nitride film, and the intermediate layer of the laminated insulating film is a silicon oxide film.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a vertical cross-sectional view of a unit pixel for an infrared sensor having a TFT type structure according to an embodiment of the present invention.

As shown in FIG. 3, the unit pixel for infrared detector having a TFT type structure includes a semiconductor substrate 31 on which an infrared reading integrated circuit including an infrared reading circuit electrode 32 is formed, and a semiconductor substrate 31. It consists of an infrared sensing unit spaced apart from the air gap 48 and connected to the electrode 32 for infrared reading circuit through the connecting electrode 37a, and the infrared sensing unit is a source region 42a, a drain region 43a and a channel region ( 45 is formed of a silicon layer and a gate of a TFT including at least an infrared ray sensing layer 40 on the silicon layer.

In detail, the infrared sensing unit has a gate insulating film 39 formed on a silicon layer, a gate in which an infrared sensing layer 40 and an infrared absorbing layer 41 are stacked on the gate insulating film 39, and in the silicon layer under the gate. A channel region 45 is formed, and an end thereof overlaps with one end of the gate, and a source region 42a and a drain region 43a are formed through ion implantation of a dopant in the silicon layer between the channel regions 45. As a result, the infrared sensing unit forms a TFT having a gate, a source region 42a and a drain region 43a, and the gate is formed of an infrared sensing layer 40 and an infrared absorbing layer 41. It converts directly into the amount of current of the TFT and reads the intensity of the incident infrared rays through the amount of current.

In Fig. 3, the infrared sensing unit is surrounded by the third insulating film 46, and the connecting electrode 37a connecting the infrared sensing unit and the electrode 32 for the infrared reading circuit is in the form of a column and the outer side thereof has an insulating side wall 36. Surrounded by).

As a result, the infrared detector and the connection electrode 37a are surrounded by the third insulating film 46 and the insulating side wall 36, and the third insulating film 46 and the insulating side wall 36 are silicon nitride films.

In the unit pixel for the infrared sensor of FIG. 3, the infrared sensing is performed by the change of the drain current by the infrared sensing layer 40 of the TFT, and the current of the TFT is connected to the infrared reading circuit electrode 32 by the connecting electrode 37a. Is passed on. The semiconductor substrate 31 having the TFT and the infrared reading integrated circuit formed thereon is thermally isolated because of being spaced apart by the air gap 48, and accordingly, a scan type sensor which changes rapidly because the drain current is maintained for a predetermined time. Suitable for

The unit pixel for the infrared sensor of the present invention is thermally stable for a shorter time than the structure of FIG. 2 since the TFT and the semiconductor substrate are thermally isolated, thereby implementing a scanning sensor array.

On the other hand, the infrared sensing unit may use a thermocouple or a bolometer in addition to the TFT. In this case, the infrared sensing layer 40 and the infrared absorbing layer 41 are stacked on the thermocouple or the bolometer, and since the silicon layer and the gate insulating film are not necessary, the TFT structure is used. It does not have to be provided.

FIG. 4 is a plan view of the pixel array for the infrared sensor of the TFT type structure of FIG. Fig. 4 shows one of the pixel arrays for infrared detectors in which a plurality of infrared sensor pixels are arranged in a single gate having a large area of a TFT into which infrared rays are incident.

Referring to FIG. 4, the TFT gate including the infrared sensing layer 40 has a width smaller than that of the silicon layer Si in which the channel region, the source region 42a, and the drain region 43a are formed in each pixel of the infrared detector. The source region 42a and the drain region 43a in the silicon layer Si have overlapping ends and ends of the TFT gates, respectively, and the upper and lower portions of the source region 42a and the drain region 43a, respectively. The connecting electrode 37a is connected to both edge portions.

The connection electrode 37a is connected to the electrode 32 for the infrared readout circuit, as shown in FIG.

In addition, the infrared detector pixel is insulated from neighboring pixels by the third insulating layer 46, and the third insulating layer 46 protects the infrared sensing unit during the etching process to form the air gap 48, which will be described later. Do this.

5A through 5J are cross-sectional views illustrating a method of manufacturing a unit pixel for an infrared sensor along line AA ′ of FIG. 4.

As illustrated in FIG. 5A, a first insulating layer 33 having a stacked structure is deposited on a semiconductor substrate 31 on which an infrared readout integrated circuit including an infrared readout electrode 32 is formed. do.

Herein, the infrared readout circuit electrode 32 is a semiconductor layer or a metal electrode to which conductivity is imparted by implanting a high concentration of dopant, and the first insulating film 33 is a multilayer insulating film having a triple structure between the silicon nitride films 33a and 33c. The silicon oxide film 33b is inserted. In the first insulating film 33, the silicon nitride films 33a and 33c are deposited to a thickness of 0.2 to 0.5 μm by a method such as chemical vapor deposition (CVD), and the silicon nitride film 33a is a subsequent silicon oxide film 33b. ) Is a material with high etching selectivity that is not damaged in the process of etching by hydrofluoric acid (HF) solution. The silicon oxide film 33b is a Phospho-Silica-Glass (PSG) or Boro-Phospho-Silica-Glass (PSG) having a thickness of 1 to 3 µm deposited by a chemical vapor deposition (CVD) method. Since the silicon oxide film 33b is etched well in hydrofluoric acid, it is useful for creating an air gap in the future.

Next, a hole 34 for exposing a part of the electrode 32 for the infrared read circuit by etching the first insulating layer 33 by using reactive ion etching (RIE) by performing photolithography operation. Form. At this time, the width | variety of the hole 34 is 1 micrometer-3 micrometers.

As shown in FIG. 5B, a silicon nitride film is formed on the first insulating film 33 including the hole 34 as the second insulating film 35 to a thickness of 0.2 to 0.5 mu m. At this time, the second insulating film 35 is formed to be thin enough not to fill the hole.

As illustrated in FIG. 5C, the second insulating layer 35 is etched by reactive ion etching (RIE) to form an insulating sidewall 36 on the inner wall of the hole 34. The above etching process is commonly referred to as an etch back, and the insulating side wall 36 made of a silicon nitride film is not etched during etching using the hydrofluoric acid solution of the silicon oxide film 33b in the first insulating film 33. Will remain.

As shown in FIG. 5D, the first silicon layer 37 is deposited by using low pressure chemical vapor deposition (LPCVD) until the hole 34 is completely filled. In this case, the first silicon layer 37 may be deposited to a thickness thicker than 0.3 μm to 1.0 μm, and the first silicon layer 37 may be recrystallized by heat to form a silicon on insulator (SOI) structure. .

As shown in FIG. 5E, the first silicon layer 37 is etched to form a connection electrode 37a formed of the first silicon layer 37 in the hole 34. In this case, since the connection electrode 37a is an electrode for connecting the infrared reading circuit electrode 32 and the infrared detector, the first silicon layer 37 is a conductor doped at high concentration through ion implantation and thermal diffusion.

As illustrated in FIG. 5F, the second silicon layer 38 may be 0.2-deposited on the structure planarized by etching the first silicon layer 37, that is, by LPCVD or the like on the silicon nitride film 33c and the connection electrode 37a. It is formed in a thickness of 탆 to 0.4 탆.

Next, on the second silicon semiconductor layer 38, a gate insulating film 39 composed of one of a silicon oxide film or a reoxidized silicon nitride film film is formed by a thermal oxidation method in a range of 5 to 20 nm thick.

Then, an infrared ray sensing layer 40 sensitive to infrared rays is formed on the gate insulating film 39. Here, the infrared sensing layer 40 is formed of a pyroelectric having a thickness of 0.2 to 0.4 µm by a spin coat method or the like, and the infrared sensing layer 40 responding to infrared rays Thermocouples or bolometers may be used. In particular, when the thermocouple or the bolometer is formed, the second silicon semiconductor layer 38 and the gate insulating layer 39 do not need to be formed to directly connect the infrared sensing layer 40 and the connection electrode 37a.

Next, an infrared absorption or gate electrode metal layer 41 is formed on the infrared sensing layer 40 by a method such as sputtering to a thickness of 0.05 to 0.2 mu m. In this case, the metal layer 41 uses gold (Au) or nickel-chromium (Ni-Cr) alloy.

Next, using the photolithography operation, the metal layer 41, the infrared ray sensing layer 40, and the gate insulating film 39 are sequentially etched to define the gate of the TFT. In this photolithography operation, the surface of the second silicon layer 38 is exposed.

As shown in FIG. 5G, the doping region 42 to be a source region and the drain region to be a source region are formed in the second silicon layer 38 exposed through ion implantation and thermal diffusion of a dopant using a gate of a defined TFT as a mask. Area 43 is formed.

As shown in Fig. 5H, photolithography is performed to partially etch the edges of the doped regions 42 and 43, respectively, to complete the source region 42a and the drain region 43a of the TFT, An isolation space 44 is opened for isolation between TFT elements. At this time, the second silicon layer under the gate of the TFT, that is, between the source region 42a and the drain region 43a becomes the channel region 45.

In this manner, the infrared detector TFT is formed by forming the source region 42a, the drain region 43a, and the channel region 45 through ion implantation and thermal diffusion of the dopant.

As illustrated in FIG. 5I, a chemical vapor deposition method is performed on the third insulating film 46 of the silicon nitride film on the entire surface including the TFT element and the isolation space 44 of the infrared detector in which the source region 42a and the drain region 43a are formed. CVD) or the like to be deposited in a thickness of 0.2 µm to 0.5 µm.

Next, a part of the third insulating film 46 is etched by performing a photolithography operation, and the silicon nitride film 33c in the first insulating film 33 is subsequently etched to form the isolation grooves 47 between adjacent TFT elements. . Here, the isolation groove 47 is used as a passage through which the hydrofluoric acid solution passes in and out to etch the silicon oxide film 33b in the subsequent first insulating film 33.

As shown in FIG. 5J, the hydrofluoric acid solution enters and exits through the isolation groove 47 to etch the silicon oxide film 33b in the first insulating film 33 to form an air gap 48 under the gate of the TFT. As such, the third insulating film 46, the insulating side wall 36, and the silicon nitride films 33a and 33c of the first insulating film 33 of the silicon nitride film are etched with respect to the silicon oxide film 33b during the etching process using the hydrofluoric acid solution. Since it has a selectivity, it is hardly damaged.

As a result, the TFT structure having the gate, the source region 42a and the drain region 43a is surrounded by insulating films made of silicon nitride film, except for the extremely narrow insulating sidewall 36, the TFT structure is formed with an infrared readout circuit. The semiconductor substrate 31 is spaced apart from the air gap 48 or a vacuum.

As described above, the present invention is simple because the semiconductor substrate on which the TFT and the infrared reading integrated circuit are formed by the coherent semiconductor process is assembled.

6 is a vertical cross-sectional view of an infrared sensor pixel according to another embodiment of the present invention, and FIG. 7 is a plan view of the pixel array for infrared sensor of FIG. 6.

Referring to FIG. 6, a semiconductor substrate 50 including an infrared reading integrated circuit including an infrared reading circuit electrode 51 and a plurality of infrared rays spaced apart from each other with an air gap 60 on the semiconductor substrate 50. The layers are connected to each other to form an array, an infrared sensing unit 70 and a conductive connecting electrode 80 connecting the infrared sensing unit 70 and the electrode 51 for the infrared reading circuit.

The infrared detecting unit 70 detects infrared rays on the silicon layer having the source region 71, the drain region 72, and the channel region 73, the gate insulating film 74 on the silicon layer, and the gate insulating film 74. It is a TFT which consists of a gate in which the layer 75 and the infrared absorption layer 76 were laminated | stacked. Accordingly, the channel region 73 is positioned in the silicon layer under the gate, and the end thereof overlaps with one end of the gate, and the source region 71 and the drain region 72 are provided in the silicon layer between the channel regions 73.

In Fig. 6, a plurality of TFTs are arranged in series and gates of the plurality of TFTs are connected to each other. Therefore, the drain region 72 of one TFT and the source region 71 of the adjacent TFT are in contact with each other, and the source region 71a of the first TFT and the drain region 72a of the last TFT in the TFT array respectively connect the connecting electrode. It is connected to the electrode 51 for infrared reading circuit through.

The connection electrode 80 is connected over a portion of the source region 71, a portion of the channel region 73, a portion of the drain region 72, and a portion of the channel region 73.

In FIG. 6, the infrared ray sensing unit 70 is surrounded by the protective film 77, and the bottom of the infrared ray sensing unit 70 and the upper portion of the semiconductor substrate 50 are respectively covered by silicon nitride films 78a and 78b. The connecting electrode 80 for connecting the infrared detecting unit 70 and the electrode 51 for the infrared reading circuit is in the form of a column and the outer side thereof is surrounded by the insulating side wall 81. Here, the protective film 77 and the insulating side wall 81 are silicon nitride films.

The unit pixel for the infrared sensor of FIG. 6 uses a TFT to convert the incident infrared rays into transistor current, but the semiconductor substrate 50 having the TFT and the infrared reading integrated circuit is formed in a vacuum or atmosphere according to the air gap 60. By isolation, the detected infrared information is prevented from being attenuated in a short time by heat conduction.

Meanwhile, the infrared detecting unit 70 may use a thermocouple or a bolometer in addition to the TFT. In this case, the infrared sensing layer and the infrared absorbing layer are stacked on the thermocouple or the bolometer, and the semiconductor layer and the gate insulating film are not necessary, and thus the TFT structure is not provided. You don't have to.

Referring to FIG. 7, the gates G1 to Gm of the plurality of TFTs constituting the infrared sensing unit form one group by connecting one end of each other while the gates of neighboring TFTs are symmetric with each other at a predetermined interval. As one group is connected to another group, gates G1 to Gm of the plurality of TFTs are connected to each other. That is, the gates G1 to Gm of the TFTs are continuously connected while being bent at one unit pixel.

The area of the TFT gates G1 to Gm including the infrared sensing layer in each pixel of the infrared detector is smaller than that of the silicon layer 90 in which the channel region, the source region and the drain region are formed, and in the silicon layer 90. The source region S and the drain region D partially overlap the ends of the TFT gates G1 to Gm and the ends thereof, and the connection electrode 80 is connected to the first gate G1 and the last gate Gm. The source region S and the drain region D are simultaneously overlapped.

The connection electrode 80 is connected to the electrode 51 for the infrared readout circuit, as shown in FIG.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above prevents attenuation of the sensed information in a short time due to thermal conduction because the TFT structure in which the transistor drain current is changed by the gate sensing gas or infrared rays is spaced apart from the semiconductor substrate by vacuum or air gap. Therefore, there is an effect that can implement a scanning detector array.

Claims (12)

A semiconductor substrate having an infrared readout integrated circuit including an infrared readout circuit electrode; Infrared detectors spaced apart from each other with an air gap on the semiconductor substrate; And Conductive connecting electrode connecting the infrared sensing unit and the electrode for the infrared reading circuit Infrared detector pixel, characterized in that it comprises a. According to claim 1, The infrared detection unit, Infrared detector pixel, characterized in that the array of one or more infrared sensing layers. The method of claim 2, The infrared detection unit, Silicon semiconductor layer; A gate insulating film on the silicon semiconductor layer; A gate in which the infrared sensing layer and the infrared absorption layer are stacked on the gate insulating layer; A channel region in the silicon semiconductor layer below the gate; And One end of the gate overlaps one end thereof, and forms a TFT including a source region and a drain region provided in the silicon semiconductor layer between the channel regions. And a plurality of the TFTs are arranged, and the gates of the plurality of TFTs are connected to each other. The method of claim 3, wherein Gates of the plurality of TFTs, The gates of the neighboring TFTs are symmetrical with each other at a predetermined interval so that one ends thereof are connected to each other to form a single group, and the gates of the plurality of TFTs are connected to each other while the one group is connected to the other one group. Infrared detector pixel, characterized in that. The method according to claim 1 or 2, The infrared detection unit Thermocouple or bolometer; An infrared sensing layer on the thermocouple or bolometer; An infrared absorption layer on the infrared sensing layer Infrared detector pixel, characterized in that it comprises a. The method according to claim 1 or 2, The connecting electrode has a pillar shape, the outside of which is surrounded by an insulating side wall pixel for infrared sensors. The method according to claim 1 or 2, And the infrared detecting unit and the connection electrode are surrounded by an insulating film. Forming an infrared reading integrated circuit including an infrared reading circuit electrode on a semiconductor substrate; Forming a stacked insulating layer on the semiconductor substrate, in which a layer etched better than the upper and lower layers is inserted in the middle; Etching the stacked insulating layer to form a hole exposing the electrode for the infrared read circuit; Forming an insulating side wall on an inner wall of the hole; Forming a connection electrode surrounded by the insulating side wall in the hole; Forming an infrared detector connected to the connection electrode on the laminated insulating film; Forming a protective film surrounding the infrared sensing unit; Etching the passivation layer and the upper layer of the insulating layer to form a passage of an etching solution on an edge of the infrared sensing unit; And Forming an air gap under the infrared sensing unit by etching the intermediate layer of the multilayer insulating layer by introducing an etching solution through the passage; Method of manufacturing a pixel for an infrared sensor, characterized in that it comprises a. The method of claim 8, The upper and lower layers, the passivation layer and the insulating side wall of the laminated insulating film have a high etching selectivity with respect to the intermediate layer of the laminated insulating film when the etching solution flows. The method of claim 8, The upper and lower layers of the laminated insulating film, the protective film and the insulating side wall are silicon nitride films, and the intermediate layer of the laminated insulating film is a silicon oxide film. The method of claim 8, The etching solution is a method of manufacturing an infrared sensor pixel, characterized in that the hydrofluoric acid solution. The method of claim 8, Forming the infrared detection unit, And a TFT having a source region and a drain region connected to the connection electrode, and a gate for detecting infrared rays, on the laminated insulating layer.