KR20040040686A - Method for forming the contact of semiconductor device - Google Patents
Method for forming the contact of semiconductor device Download PDFInfo
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- KR20040040686A KR20040040686A KR1020020068881A KR20020068881A KR20040040686A KR 20040040686 A KR20040040686 A KR 20040040686A KR 1020020068881 A KR1020020068881 A KR 1020020068881A KR 20020068881 A KR20020068881 A KR 20020068881A KR 20040040686 A KR20040040686 A KR 20040040686A
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 39
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 10
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 9
- 239000011737 fluorine Substances 0.000 claims abstract description 9
- 229910052724 xenon Inorganic materials 0.000 claims abstract description 9
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 150000001875 compounds Chemical class 0.000 claims abstract description 7
- 239000007789 gas Substances 0.000 abstract description 35
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 26
- 239000000758 substrate Substances 0.000 abstract description 20
- 229910052786 argon Inorganic materials 0.000 abstract description 13
- 230000000694 effects Effects 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000010494 dissociation reaction Methods 0.000 description 10
- 230000005593 dissociations Effects 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 239000012535 impurity Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052743 krypton Inorganic materials 0.000 description 1
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 메모리 소자 제조 공정 중 콘택홀 형성방법에 관한 것으로, 콘택홀 형성을 위한 식각공정 시, 탄소(C)와 불소(F)를 주성분으로 하는 화합물 및 제논(Xe)의 혼합 기체를 식각기체로 사용하여 식각공정을 진행함으로써, 기존의 아르곤이 포함된 식각기체의 사용으로 높은 에너지의 사용으로 발생되던 고온의 전자에 의한 기판 데미지를 제거하고 마이크로-로딩(Micro-loading) 효과를 개선하도록 하는 반도체소자의 콘택홀 형성방법에 관한 것이다.The present invention relates to a method of forming a contact hole during a semiconductor memory device manufacturing process, wherein during the etching process for forming a contact hole, a mixed gas of a compound containing carbon (C) and fluorine (F) as a main component and xenon (Xe) is etched. By using the gas as an etching process, it is possible to remove substrate damage caused by high-temperature electrons and improve the micro-loading effect caused by the use of an etch gas containing argon. A contact hole forming method of a semiconductor device.
Description
본 발명은 반도체 메모리 소자 제조 공정 중 콘택홀 형성방법에 관한 것으로, 특히, 콘택홀 형성을 위한 식각공정 시, 탄소(C)와 불소(F)를 주성분으로 하는 화합물 및 제논(Xe)의 혼합 기체를 식각기체로 사용하여 식각공정을 진행함으로써, 기존의 아르곤이 포함된 식각기체의 사용으로 높은 에너지의 사용으로 발생되던 고온의 전자에 의한 기판 데미지를 제거하고 마이크로-로딩(Micro-loading) 효과를 개선하도록 하는 반도체소자의 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact hole in a semiconductor memory device manufacturing process. In particular, in an etching process for forming a contact hole, a mixed gas of a compound containing carbon (C) and fluorine (F) as a main component and xenon (Xe) Process using the etching gas to remove the substrate damage caused by the use of high energy by the use of the conventional etching gas containing argon and the high-energy to reduce the micro-loading effect The present invention relates to a method for forming a contact hole in a semiconductor device for improvement.
최근 반도체소자의 집적도가 증가함에 따라 소자 형성을 위한 이온주입 시 그 깊이 또한 얕아지고 있는 추세이고, 디자인 룰(design rule)도 감소하고 있는 추세이다.Recently, as the degree of integration of semiconductor devices increases, the depth of ion implantation for forming devices is also becoming shallower, and the design rules are also decreasing.
따라서 소자 형성 공정 중에 기판이 데미지(demage)를 입을 수 있는 조건들이 많으며 그 중에서도 콘택홀 형성에 따른 기판의 데미지 방지는 아주 중요한 요소로 대두되고 있다.Therefore, there are many conditions in which the substrate may be damaged during the device formation process, and damage prevention of the substrate due to contact hole formation is emerging as an important factor.
그런데, 종래에는 반도체소자의 콘택홀을 형성하기 위해 탄소와 불소를 주성분으로 하는 화합물 및 아르곤(Ar)의 혼합 기체를 식각기체로 사용하여 절연층을 식각하여 절연층 내에 콘택홀을 형성하였다.In the related art, in order to form contact holes in a semiconductor device, an insulating layer is etched using a mixture gas of carbon and fluorine as a main component and argon (Ar) as an etching gas to form a contact hole in the insulating layer.
그러나, 상기 종래 기술에 의한 콘택홀 형성방법에 따르면, 콘택홀 식각공정 시, 탄소와 불소를 주성분으로 이루어진 화합물 및 아르곤의 혼합기체로 이루어진 저압의 고밀도 플라즈마를 식각기체를 사용함으로써, 이온화에너지가 높은 아르곤의 이온화를 위한 높은 에너지에 의해 전자의 온도가 높아 식각기체의 해리가 지나치게 진행되며, 상기 지나친 해리, 즉, 과잉 해리에 의하여 발생된 하전입자들에 의해 식각 종말점 근처에서 노출되는 실리콘기판에 데미지를 발생시키는 문제점이있다.However, according to the conventional method of forming a contact hole, in the contact hole etching process, a high pressure of ionization energy is obtained by using a low pressure high-density plasma composed of a mixture of carbon and fluorine as a main component and argon. Due to the high energy for the ionization of argon, the electron temperature is high and dissociation of the etching gas proceeds excessively, and damage to the silicon substrate exposed near the etching end point by the charged particles generated by the excessive dissociation, ie, excessive dissociation. There is a problem that causes it.
이하, 첨부한 도면을 참고로 하여, 상기와 같은 종래 기술의 문제점을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings, it will be described in detail the problems of the prior art as described above.
도 1a 내지 도 1c는 종래기술에 따른 반도체소자의 콘택홀 형성방법을 순차적으로 나타내는 공정 단면도이다.1A to 1C are cross-sectional views sequentially illustrating a method for forming a contact hole in a semiconductor device according to the prior art.
상기 종래 기술에 의한 콘택홀 형성방법에 따르면, 우선, 도 1a에 도시된 바와 같이, 게이트 전극 및 불순물 확산영역에 의해 트랜지스터(미도시함)가 형성된 실리콘기판(11) 상에 절연층(12)을 형성한다. 상기 절연층(12)은 실리콘산화막(SiO2)이거나 또는 실리콘 질화막(Si3N4)중 어느 하나를 이용한다.According to the conventional method for forming a contact hole, first, as shown in FIG. 1A, an insulating layer 12 is formed on a silicon substrate 11 on which a transistor (not shown) is formed by a gate electrode and an impurity diffusion region. To form. The insulating layer 12 is either a silicon oxide film (SiO 2 ) or a silicon nitride film (Si 3 N 4 ).
그 다음, 상기 절연층(12) 상에 포토레지스트(13)를 도포한 후, 노광 및 현상공정으로 패터닝하여 도 1b에 도시된 바와 같이, 절연층(12) 상에 포토 마스크(13a)를 형성한다.Then, after applying the photoresist 13 on the insulating layer 12, and patterned by the exposure and development process to form a photo mask (13a) on the insulating layer 12, as shown in Figure 1b do.
이어서, 도 1c에 도시된 바와 같이, 상기 포토 마스크(13a)를 이용한 식각 공정으로 절연층(12)을 C4F8, C5F8, C4F6, CH2F2및 CH3F 등과 같이 C/F의 비율이 높은 플로로카본(C-F)계열의 플라즈마와 아르곤(Ar)이 혼합된 혼합기체를 식각기체로 건식식각하여 불순물 확산영역에 상응하는 기판(11)의 표면이 노출되도록 콘택홀(14)을 형성한다. 그러나, 상기 C/F의 비율이 높은 플로로카본(C-F)계열의 플라즈마와 이온화에너지가 높은 아르곤이 혼합된 혼합기체를 식각기체로 사용하게 되면, 이온화에너지가 높은 아르곤으로 인하여 높은 에너지를 가해야 하며, 이로 인하여, 식각기체의 해리가 지나치게 진행되어 실리콘기판의 식각선택비가 낮아진다. 즉, "A"와 같이, 실리콘기판의 식각선택비가 절연층에 비해 낮아져 실리콘기판이 식각된다. 또한, 상기 식각기체의 지나친 해리에 의해 발생된 하전입자들로 인하여 콘택홀 식각 종말점 근처에서 노출되는 실리콘기판에 고온 전자 플라즈마의 충격에 의한 데미지를 유발하여 데미지층(15)을 형성한다.Subsequently, as shown in FIG. 1C, the insulating layer 12 is etched using the photomask 13a to C 4 F 8 , C 5 F 8 , C 4 F 6 , CH 2 F 2, and CH 3 F. As a result, a dry gas of a mixture of plasma and argon (Ar) having a high C / F ratio is etched with an etching gas to expose the surface of the substrate 11 corresponding to the impurity diffusion region. The contact hole 14 is formed. However, when using a mixture gas in which the plasma of the C / F ratio having a high ratio of CF and argon having high ionization energy is used as an etching gas, high energy due to argon having high ionization energy must be applied. As a result, dissociation of the etching gas proceeds excessively, thereby lowering the etching selectivity of the silicon substrate. That is, as in " A ", the etching selectivity of the silicon substrate is lower than that of the insulating layer, thereby etching the silicon substrate. In addition, due to the charged particles generated by excessive dissociation of the etching gas, a damage layer 15 is formed by causing damage due to the impact of a high temperature electron plasma on the silicon substrate exposed near the contact hole etching end point.
즉, 상기와 같은 종래 기술에 의한 반도체소자의 콘택홀 형성방법을 이용하게 되면, 상기 절연층을 건식식각 할 경우에는 절연층의 균일도, 식각 균일도, 식각 마이크로-로딩(Micro-loading)등을 고려하여 언더 에치(under etch)를 방지하기 위해 충분한 오버 에치(over etch)를 하게 되는데, 오버 에치 시에 기판의 손실(loss)가 발생하게 되며, 또한, 상기 기판의 손실된 부분에는 도 1c에서와 같이 데미지층 즉, 에천트(etchant)들의 물리적 충돌에 의해 기판의 격자들의 결합이 파괴되거나 또한 불순물 확산영역의 불순물 이온들이 치환되어 존재하게 되거나 에치되고 남은 폴리머(polymer)등의 데미지층이 존재하게 되는 문제점이 있다.That is, when the contact hole forming method of the semiconductor device according to the related art is used, in the case of dry etching the insulating layer, the uniformity of the insulating layer, the etching uniformity, the etching micro-loading (Micro-loading), etc. are considered. In order to prevent under etch, a sufficient over etch is performed. In the case of over etch, a loss of the substrate occurs, and the lost portion of the substrate is shown in FIG. Likewise, the damage layer, that is, the bond of the lattice of the substrate is broken by the physical collision of etchant, or the impurity ions in the impurity diffusion region are replaced or existed, or the damage layer such as polymer remaining after being etched is present. There is a problem.
상기와 같은 문제점으로 인하여 리프레쉬(refresh)특성, 누설전류(leakage current), 콘택 저항(contact resistant)등이 불량해져 소자의 신뢰성이 저하된다.Due to the above problems, the refresh characteristics, the leakage current, the contact resistance, and the like are poor, thereby reducing the reliability of the device.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 기존의 콘택홀 형성을 위한 식각기체에 이온화에너지가 낮은 제논(Xe)를 첨가하여 식각공정을 진행함으로써, 고밀도 플라즈마는 유지하되 생성되는 전자의 온도가 낮아지게 되며, 이에 따라 식각기체의 과잉 해리(Dissociation)가 감소되어 실리콘기판 데미지를 제거하고 마이크로-로딩(Micro-loading) 효과를 개선하도록 하는 반도체소자의 콘택홀 형성방법을 제공하는데 있다.The present invention has been made to solve the above problems, an object of the present invention is to add a low ionization energy xenon (Xe) to the etching gas for forming a conventional contact hole to proceed the etching process, the high-density plasma is While maintaining the temperature of the generated electrons is lowered, accordingly the dissociation of the etching gas is reduced to remove the silicon substrate damage and to improve the micro-loading effect to form a contact hole of the semiconductor device To provide a method.
도 1a 내지 도 1c는 종래 반도체소자의 콘택홀 형성방법을 설명하기 위해 순차적으로 나타낸 공정 단면도이다.1A through 1C are cross-sectional views sequentially illustrating a method of forming a contact hole in a conventional semiconductor device.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 콘택홀 형성방법을 설명하기 위해 순차적으로 나타낸 공정 단면도이다.2A through 2C are cross-sectional views sequentially illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.
-- 도면의 주요부분에 대한 부호의 설명 ---Explanation of symbols for the main parts of the drawing-
100 : 실리콘기판 110 : 절연층100: silicon substrate 110: insulating layer
130 : 포토레지스트 130a : 포토 마스크130: photoresist 130a: photo mask
140 : 콘택홀140: contact hole
상기 목적을 달성하기 위하여, 본 발명은 반도체소자의 콘택홀 형성을 위한 식각 공정에 있어서, 탄소(C)와 불소(F)를 주성분으로 하는 화합물 및 제논(Xe)의 혼합 기체를 식각기체로 사용함을 특징으로 하는 반도체 소자의 콘택홀 형성방법을 제공한다.In order to achieve the above object, the present invention, in the etching process for forming the contact hole of the semiconductor device, using a mixed gas of a compound consisting of carbon (C) and fluorine (F) and xenon (Xe) as an etching gas A contact hole forming method of a semiconductor device is provided.
상기, 본 발명의 반도체소자의 콘택홀 형성방법에 있어서, 상기 탄소와 불소를 주성분으로 하는 화합물은 C4F8, C5F8, C4F6, CH2F2및 CH3F 중 적어도 어느 하나 이상을 사용하는 것이 바람직하다.In the method for forming a contact hole in a semiconductor device of the present invention, the compound containing carbon and fluorine as a main component is C 4 F 8 , C 5 F 8 , C 4 F 6 , CH 2 F 2, and CH 3 F It is preferable to use any one or more.
즉, 상기 본 발명에 의한 콘택홀 형성방법에 의하면, 상기 콘택홀을 형성하기 위한 식각기체로 이온화에너지가 높은 아르곤 대신에 이온화에너지가 낮은 제논을 함유한 혼합기체를 사용하여 식각공정을 진행함으로써, 기존의 아르곤(Ar)이 함유된 식각기체에 의해 발생되던 식각기체의 과잉 해리를 억제하며, 그로 인하여 플라즈마 내의 가벼운 원자의 발생을 줄이게 되고, 상대적으로 무거운 라디칼(radical)들의 운동을 활성화시켜 콘택홀 하부까지 라디칼들이 이동할 수 있어 콘택홀이 깊어짐에 따른 식각률의 저하 현상, 즉 마이크로 로딩 효과를 개선할 수 있게 되는 것이다.That is, according to the method for forming a contact hole according to the present invention, by performing an etching process using a mixed gas containing xenon having a low ionization energy instead of argon having a high ionization energy as an etching gas for forming the contact hole, It suppresses excessive dissociation of the etching gas caused by the conventional etching gas containing argon (Ar), thereby reducing the generation of light atoms in the plasma and activating the contact hole by activating the movement of relatively heavy radicals The radicals can move to the lower side, thereby reducing the etching rate as the contact hole deepens, that is, to improve the micro loading effect.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 콘택홀 형성방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2C are cross-sectional views sequentially illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.
우선, 도 2a에 도시된 바와 같이, 상기 게이트 전극 및 불순물 확산영역에 의해 트랜지스터(미도시함)가 형성된 실리콘기판(100) 상에 절연층(110)을 형성한다. 이때, 상기 절연층(110)은 실리콘산화막(SiO2)이거나 또는 실리콘 질화막(Si3N4)중 어느 하나를 이용한다.First, as shown in FIG. 2A, an insulating layer 110 is formed on a silicon substrate 100 on which a transistor (not shown) is formed by the gate electrode and an impurity diffusion region. In this case, the insulating layer 110 may be one of a silicon oxide film (SiO 2 ) or a silicon nitride film (Si 3 N 4 ).
그 다음, 상기 절연층(110) 상에 포토레지스트(130)를 도포한 후, 노광 및 현상공정으로 패터닝하여 도 2b에 도시된 바와 같이, 절연층(110) 상에 포토 마스크(130a)를 형성한다.Next, the photoresist 130 is coated on the insulating layer 110, and then patterned by an exposure and development process to form a photomask 130a on the insulating layer 110, as shown in FIG. 2B. do.
이어서, 도 2c에 도시된 바와 같이, 상기 포토 마스크(130a)를 이용한 식각 공정으로 절연층(110)을 C4F8, C5F8, C4F6, CH2F2및 CH3F 등과 같이 C/F의 비율이 높은 플로로카본(C-F)계열의 기체를 주성분으로 하는 화합물 및 제논(Xe)의 혼합 기체를 식각기체로 플라즈마 식각하여 불순물 확산영역에 상응하는 기판(100)의 표면이 노출되도록 콘택홀(140)을 형성한다. 이때, 상기 제논(Xe)은 표 1에 나타낸 바와 같이, 원자 하나에서 가장 약한 전자 하나를 떼어내는데 필요한 최소 에너지인 이온화 에너지(Ionization Energy)가 12.9 eV로 기존에 식각기체에 포함되었던 아르곤(Ar)과 크립톤(Kr)보다 작은 에너지를 가지고도 이온화가 가능하여 플라즈마의 유지에도 유리한 특성을 보인다.Subsequently, as shown in FIG. 2C, the insulating layer 110 is etched using the photomask 130a to form C 4 F 8 , C 5 F 8 , C 4 F 6 , CH 2 F 2, and CH 3 F. The surface of the substrate 100 corresponding to the impurity diffusion region is plasma-etched with an etching gas by using a mixture gas of a compound having a fluorocarbon (CF) -based gas having a high C / F ratio and a xenon (Xe) as an etching gas. The contact hole 140 is formed to expose the contact hole 140. In this case, as shown in Table 1, Xen has an ionization energy of 12.9 eV, which is the minimum energy required to remove one of the weakest electrons from an atom, and argon (Ar). It can be ionized even with less energy than and krypton (Kr), which shows advantageous properties in maintaining plasma.
따라서, 상기 제논을 함유한 식각기체는 고밀도 특성을 유지하면서도 저온 전자 플라즈마를 발생시킬 수 있는 효율이 가장 높기 때문에 콘택홀 식각공정 시, 식각기체의 과잉 해리를 억제하여, C/F의 비율이 높은 즉, 탄소를 다량 함유한(Carbon-rich) 폴리머(미도시함)를 형성하여 콘택홀 하부를 형성하게 됨으로써, 이온의 충돌에 의한 기판(100) 데미지를 방지한다. 또한, 상기 억제된 과잉 해리로 인하여 플라즈마 내의 가벼운 원자의 발생을 줄이게 되며, 상대적으로 무거운 라디칼(radical)들의 운동을 활성화시켜 콘택홀 하부까지 라디칼들이 이동할 수 있어 콘택홀이 깊어짐에 따른 식각률의 저하 현상을 개선시킨다.Therefore, the etch gas containing xenon has the highest efficiency to generate low-temperature electron plasma while maintaining high density characteristics, thereby suppressing excessive dissociation of the etch gas during the contact hole etching process, and thus has a high C / F ratio. That is, a carbon-rich polymer (not shown) is formed to form a lower contact hole, thereby preventing damage to the substrate 100 due to the collision of ions. In addition, the suppressed excessive dissociation reduces the generation of light atoms in the plasma, and activates the movement of relatively radical radicals, thereby allowing radicals to move to the bottom of the contact hole, thereby reducing the etching rate as the contact hole deepens. Improves.
따라서, 상기한 바와 같이, 본 발명에 따른 반도체소자의 콘택홀 형성방법을 이용하게 되면, 콘택홀을 형성하기 위한 식각기체로 이온화에너지가 높은 아르곤(Ar)가스 대신에 이온화에너지가 낮은 제논(Xe)가스가 혼합된 혼합기체를 사용하여 식각공정을 진행함으로써, 기존의 탄소와 불소 및 아르곤이 주로 이루어진 식각기체의 사용으로 인해 발생되던 고온의 전자에 의한 기판 데미지를 제거하고, 고밀도 플라즈마는 유지하되 생성되는 전자의 온도는 낮추어 식각기체의 과잉 해리(Dissociation)를 감소시키며, 그로 인해 마이크로-로딩(Micro-loading) 효과를 개선할 수 있게 된다.Therefore, as described above, when the method for forming a contact hole of a semiconductor device according to the present invention is used, xenon having low ionization energy instead of argon (Ar) gas having high ionization energy as an etching gas for forming contact holes is formed. The etching process is performed using a mixed gas mixed with gas to remove substrate damage caused by high temperature electrons caused by the use of an etching gas mainly composed of carbon, fluorine, and argon, and to maintain a high density plasma. The temperature of the generated electrons is lowered to reduce excessive dissociation of the etching gas, thereby improving the micro-loading effect.
그 결과, 반도체소자의 리프레쉬(refresh)특성, 누설전류(leakage current), 콘택 저항(contact resistant)등의 불량이 방지되어 소자의 신뢰성을 향상시키는 효과가 있다.As a result, defects such as refresh characteristics, leakage current, contact resistance, and the like of the semiconductor device are prevented, thereby improving the reliability of the device.
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