KR20040037900A - Apparatus for driving liquid crystal display using spread spectrum and method for driving the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof capable of maintaining a constant pulse width of a control signal by synchronizing a spreading period of a frequency using a spread spectrum with a horizontal synchronizing signal.

The liquid crystal display device of the present invention comprises: a liquid crystal panel having a pixel matrix; A spread spectrum circuit for spreading the frequency of the input clock signal in a period synchronous with the input horizontal synchronization signal to output a spread clock signal; A timing controller for generating a plurality of control signals having a pulse width determined using the spread clock signal; And a liquid crystal panel driver for driving the liquid crystal panel using control signals from a timing controller.

Description

A liquid crystal display using a spread spectrum and a driving method thereof {APPARATUS FOR DRIVING LIQUID CRYSTAL DISPLAY USING SPREAD SPECTRUM AND METHOD FOR DRIVING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device using a spread spectrum and a driving method thereof which can maintain a constant frequency of a control signal using a spread spectrum.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal panel having a pixel matrix and a driver for driving the liquid crystal panel.

Specifically, the liquid crystal display includes a liquid crystal panel 2 having a pixel matrix, a gate driver 4 for driving gate lines GL1 to GLm of the liquid crystal panel 2, as shown in FIG. A data driver 6 for driving the data lines DL1 to DLn of the liquid crystal panel 2, and a timing controller 8 for controlling the driving timing of the gate driver 4 and the data driver 6. do.

The liquid crystal panel 2 includes a pixel matrix composed of pixels formed at respective regions defined by intersections of the gate lines GL1 to GLm and the data lines DL1 to DLn. Each of the pixels includes a liquid crystal cell Clc for adjusting light transmittance according to a pixel signal, and thin film transistors TFT for driving the liquid crystal cell Clc.

The thin film transistor TFT is turned on when the scan signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the pixel signal from the data line DL to the liquid crystal cell Clc. The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the pixel signal charged in the liquid crystal cell Clc.

The liquid crystal cell Clc is equivalently represented by a capacitor and includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT. In addition, the liquid crystal cell Clc further includes a storage capacitor (not shown) so that the charged pixel signal is stably maintained until the next pixel signal is charged. The liquid crystal cell Clc realizes gray by adjusting light transmittance by varying an arrangement state of liquid crystals having dielectric anisotropy according to pixel signals charged through the thin film transistor TFT.

The gate driver 4 shifts a gate start pulse (hereinafter, referred to as a GSP) from the timing controller 8 according to a gate shift clock (hereinafter, referred to as a GSC). Scan pulses having a gate high voltage (hereinafter referred to as VGH) are sequentially supplied to GL1 to GLm). The gate driver 4 supplies the gate low voltage (hereinafter referred to as VGL) in the remaining periods when VGH is not supplied to the gate lines GL1 to GLn. In addition, the gate driver 4 controls the pulse width of the scan pulse according to a gate output enable signal (hereinafter referred to as a GOE) signal from the timing controller 8.

The data driver 6 generates a sampling signal by shifting the source start pulse (hereinafter referred to as SSP) from the timing controller 8 according to the source shift clock (hereinafter referred to as SSC). do. The data driver 6 latches the pixel data RGB according to the SSC according to the sampling signal and then lines by line in response to a source output enable signal (SOE). Supply. Subsequently, the data driver 6 converts the gamma voltage from a gamma voltage part (not shown) into pixel signals RGB supplied in line units to analog pixel signals and supplies them to the data lines DL1 through DLn. Here, the data driver 6 determines the polarity of the pixel signal in response to the polarity control (hereinafter referred to as POL) signal from the timing controller 8 when converting the pixel data into the pixel signal. The data driver 6 determines a period in which the pixel signal is supplied to the data lines DL1 to DLn in response to the SOE.

The timing controller 8 generates GSP, GSC, GOE signals, etc. for controlling the gate driver 4, and generates SSP, SSC, SOE, POL signals, etc., for controlling the data driver 6. In this case, the timing controller 8 may include a data enable signal (DE), a horizontal sync signal (hereinafter referred to as Hsync), and a vertical sync signal (hereinafter referred to as “DE”) indicating a valid data section input from the outside. Control signals such as GSP, GSC, GOE, SSP, SSC, SOE, POL, etc. using a dot clock (hereinafter referred to as DCLK), which determines a transmission timing of pixel data RGB. Will be created. In particular, the timing controller 8 spreads the spread spectrum to reduce electromagnetic interference (hereinafter referred to as EMI) between various control signals and pixel data signals transmitted to the gate driver 4 and the data driver 6. According to the Spread Spectrum method, control signals such as the GSP, GSC, GOE, SSP, SSC, SOE, and POL are generated using DCLK (hereinafter, SDLCK) spread in a specific frequency range. Accordingly, the frequency of the control signals generated by the timing controller 8 is not kept constant, but has a form of shaking within a specific frequency range along the SDCLK. As a result, EMI between the control signals is caused by the shaking frequency. The offset and reduction effect can be obtained.

For this frequency spreading, the liquid crystal display shown in FIG. 1 further includes a spread spectrum IC 10 for frequency spreading the DCLK input from the outside to the timing controller 8. The spread spectrum IC 10 frequency modulates the input DCLK and adjusts the oscillation frequency using a phase-locked loop (hereinafter referred to as a PLL) circuit according to the modulated frequency, as shown in FIGS. 2A and 2B. As shown in the figure, the output of SDCLK varies with a certain period within a specific frequency range.

However, the frequency spreading period of the SDLCK changing within a specific frequency range is not synchronized with Hsync as shown in FIGS. 2A and 2B. Accordingly, a problem arises in that pulse widths of control signals, such as GSP, GOE, SSP, and SOE signals, which are generated by counting the SDCLK based on Hsync, vary with each horizontal period.

FIG. 2A shows the case where the frequency spreading period of the SDCLK is larger than the period of Hsync. The pulse width is shown as an example. Here, the first and second control signals CS1 and CS2 correspond to any one of the GSP, GOE, SSP, and SOE signals.

2A and 2B, it can be seen that the frequency bands of the SDCLK counted based on Hsync are different for each horizontal period in order to determine the pulse widths of the first and second control signals CS1 and CS2. As such, as the SDCLKs of different frequency bands are counted for each horizontal period, the pulse widths of the first and second control signals CS1 and CS2 are changed for each horizontal period.

For example, when the pulse width of the GOE signal that determines the pulse width of the scan pulse is varied for each horizontal period, the brightness difference occurs for each horizontal line since the chargers of the pixel signals vary for each horizontal line. In addition, when the pulse width of the SOE signal, which determines the period in which the pixel signal is supplied to the data line, is changed in each horizontal period, the charger of the pixel signal is changed for each horizontal line, thereby generating a luminance difference for each horizontal line.

Due to the luminance difference for each horizontal line, noise such as a wave pattern is generated on the screen of the liquid crystal panel, thereby causing a problem of deterioration of display quality.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of maintaining a constant pulse width of a control signal by synchronizing a diffusion period of a frequency using a spread spectrum with Hsync.

Another object of the present invention is to provide a liquid crystal display device and a driving method thereof which can improve display quality by preventing a luminance difference for each horizontal line.

1 illustrates a conventional liquid crystal display device.

2 is an input / output signal waveform diagram of the timing controller shown in FIG. 1;

3 is a diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

4 is an input / output signal waveform diagram of the timing controller shown in FIG. 3;

5 is a block diagram showing a detailed configuration of the spread spectrum IC shown in FIG.

<Brief description of symbols for the main parts of the drawings>

2, 12: liquid crystal panel 4, 14: gate driver

6, 16: data driver 8, 18: timing controller

10, 20: spread spectrum IC 21: first divider

22: second divider 23: modulator

24: Phase Comparator 25: Low Pass Filter (LPF)

26: voltage controlled oscillator (VCO)

In order to achieve the above objects, a liquid crystal display device according to the present invention comprises: a liquid crystal panel having a pixel matrix; A spread spectrum circuit for spreading the frequency of the input clock signal in a period synchronous with the input horizontal synchronization signal to output a spread clock signal; A timing controller for generating a plurality of control signals having a pulse width determined using the spread clock signal; And a liquid crystal panel driver for driving the liquid crystal panel using control signals from a timing controller.

The spread spectrum circuit comprises: a modulation frequency generator for generating a modulation frequency having a modulation period in synchronization with a horizontal synchronization signal; And a phase locked loop circuit for generating a spread clock signal having a modulation period and spreading frequency using a clock signal and a modulation frequency.

The timing controller may determine a pulse width of control signals by counting a spread clock signal based on a horizontal synchronization signal.

The timing controller generates control signals by using a vertical synchronization signal from the outside together with a spread clock signal and a data enable signal indicating an effective period of the pixel data.

Here, the control signals include a gate start pulse, a gate shift clock, and a gate enable signal required by the liquid crystal panel driver to drive the gate lines of the liquid crystal panel, and are required to drive the data lines of the liquid crystal panel. And a source start pulse, a source shift clock, a source enable signal, and a polarity control signal.

A method of driving a liquid crystal display according to the present invention includes the steps of: spreading a frequency of an input clock signal in a period in synchronization with an input horizontal synchronization signal to generate a spread clock signal; Generating a plurality of control signals having a pulse width determined using a spread clock signal; And driving the liquid crystal panel using the control signals.

Generating the spread clock signal comprises generating a modulation frequency having a modulation period in synchronization with a horizontal synchronization signal; And generating a spread clock signal having a modulation period and spreading frequency by using the clock signal and the modulation frequency.

The generating of the control signals may further include determining a pulse width of the control signals by counting a spread clock signal based on a horizontal synchronization signal.

The generating of the control signals may include generating the control signals using a vertical synchronization signal from the outside together with a spread clock signal and a data enable signal indicating an effective period of the pixel data. .

The control signals include a gate start pulse, a gate shift clock, and a gate enable signal required to drive gate lines of the liquid crystal panel, and source start pulses and source shift needed to drive data lines of the liquid crystal panel. And a clock, a source enable signal, and a polarity control signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 illustrates a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

The liquid crystal panel 12 having the liquid crystal display pixel matrix shown in FIG. 4, the gate driver 14 for driving the gate lines GL1 to GLm of the liquid crystal panel 12, and the liquid crystal panel 12 of the liquid crystal panel 12. A data driver 16 for driving the data lines DL1 to DLn, a timing controller 18 for controlling the driving timing of the gate driver 14 and the data driver 16, and Hsync using a spread spectrum And a spread spectrum IC 20 for generating and supplying SDCLK having a spread period in synchronization with the timing controller 18.

The liquid crystal panel 12 includes a pixel matrix composed of pixels formed at regions defined by intersections of the gate lines GL1 to GLm and the data lines DL1 to DLn. Each of the pixels includes a liquid crystal cell Clc for adjusting light transmittance according to a pixel signal, and thin film transistors TFT for driving the liquid crystal cell Clc.

The thin film transistor TFT is turned on when the scan signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the pixel signal from the data line DL to the liquid crystal cell Clc. The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the pixel signal charged in the liquid crystal cell Clc.

The liquid crystal cell Clc is equivalently represented by a capacitor and includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT. In addition, the liquid crystal cell Clc further includes a storage capacitor (not shown) so that the charged pixel signal is stably maintained until the next pixel signal is charged. The liquid crystal cell Clc realizes gray by adjusting light transmittance by varying an arrangement state of liquid crystals having dielectric anisotropy according to pixel signals charged through the thin film transistor TFT.

The gate driver 14 shifts the GSP from the timing controller 18 according to the GSC to sequentially supply the scan pulses having VGH to the gate lines GL1 to GLm. The gate driver 14 supplies the VGL in the remaining period in which the VGH is not supplied to the gate lines GL1 through GLn. The gate driver 14 also controls the pulse width of the scan pulse in accordance with the GOE signal from the timing controller 18.

The data driver 16 shifts the SSP from the timing controller 18 in accordance with the SSC to generate a sampling signal. The data driver 16 latches the pixel data RGB input according to the SSC according to the sampling signal and supplies the line data in response to the SOE signal. Subsequently, the data driver 16 converts the gamma voltage from a gamma voltage part (not shown) into the analog pixel signal by supplying the pixel data RGB supplied on a line basis to the data lines DL1 to DLn. Here, the data driver 16 determines the polarity of the pixel signal in response to the POL from the timing controller 18 when converting the pixel data RGB into the pixel signal. The data driver 16 determines a period in which the pixel signal is supplied to the data lines DL1 to DLn in response to the SOE signal.

The spread spectrum IC 20 spreads the DCLK input from the outside to have a period in synchronization with Hsync to generate SDCLK and supplies the generated SDCLK to the timing controller 18. Specifically, the spread spectrum IC 20 frequency modulates the input DCLK to have a modulation period synchronized with Hsync. The spread spectrum IC 20 then adjusts the oscillation frequency using a phase-locked loop (hereinafter referred to as a PLL) circuit according to its modulated frequency, and within a specific frequency range as shown in FIG. It will generate SDCLK that changes frequency with a period synchronized with Hsync. The detailed configuration of such a spread spectrum IC 20 will be described later.

The timing controller 18 generates GSP, GSC, GOE signals, etc. for controlling the gate driver 14, and generates SSP, SSC, SOE, POL signals, etc., for controlling the data driver 16. In this case, the timing controller 18 uses the DE signal, the Hsync, the Vsync, and the SDCLK from the spread spectrum IC 20 for the valid data section input from the outside, and the GSP, GSC, GOE, SSP, SSC, SOE, It generates control signals such as POL signal. Here, since the SDLCK has a frequency spread within a specific frequency range, the frequency of the control signals generated by the timing controller 18 is not kept constant, but has a form of shaking within a specific frequency range along the SDCLK. As a result, EMI between the control signals transmitted from the timing controller 18 is canceled by the shaking frequency, thereby reducing the effect. In particular, the frequency of the SDCLK output from the spread spectrum IC 20 has a spreading period synchronized with Hsync as shown in FIG. 4. Accordingly, the pulse widths of control signals, such as GSP, GSC, GOE, SSP, SSC, SOE, POL, etc., which count and determine SDCLK based on Hsync in the timing controller 18, may be the same for each horizontal period.

Referring to FIG. 4, it can be seen that the frequency of the SDCLK supplied from the spread spectrum IC 20 is changed with a spreading period synchronized with Hsync. Accordingly, the first and second control signals CS1 and CS2 having the pulse width determined by counting the SDCLK based on Hsync have the same pulse width every horizontal period. Here, the first and second control signals CS1 and CS2 correspond to any one of the GSP, GSC, GOE, SSP, SSC, SOE, and POL.

Even when the control signals are generated by using the spread spectrum type SDCLK in order to reduce the EMI in the timing controller 18, it is possible to prevent the luminance difference between the horizontal lines as the pulse width of the control signals is constant for each horizontal line. do. For example, since the pulse width of the GOE for determining the pulse width of the scan pulse and the pulse width of the SOE for determining the supply period of the pixel signal are the same for each horizontal period, the luminance difference does not occur for each horizontal line.

FIG. 5 is a block diagram showing the detailed configuration of the spread spectrum IC 20 shown in FIG.

The spread spectrum IC 20 shown in FIG. 5 inputs a first divider 21 for inputting DCLK from the outside, a second divider 22 for inputting the fed back SDCLK, and an Hsync input from the outside. And a phase difference comparator 24 for inputting output signals of the first and second dividers 21 and 22 and the modulation frequency generator 23, and the phase difference comparator 24. A low pass filter (hereinafter referred to as LPF) 25 and a voltage controlled oscillator (hereinafter referred to as VCO) 26. Here, the remaining components except for the modulator 23 constitute a PLL circuit.

The first divider 21 divides and outputs the frequency of DCLK input from the outside, and the second divider 22 divides and outputs the frequency of SDCLK fed back from the output line of the VCO 26. The modulator 23 generates an modulation frequency having a modulation period synchronized with the Hsync using Hsync input from the outside. The phase difference comparator 24 compares the phases of the frequency divisions from the first and second frequency dividers 21 and 22 with the modulation frequency from the modulation section 23 to generate the phase difference signals. The LPF 25 removes and outputs a high frequency component included in the phase difference signal from the phase difference comparator 24. The VCO 26 changes the oscillation frequency in the direction of reducing the magnitude of the phase difference signal from the LPF 25 and outputs it to the SDCLK. In this case, the SDCLK output from the VCO 26 has a frequency spread spectrum in which the frequency increases and decreases in a period synchronized with Hsync, as shown in FIG. 4.

As described above, the liquid crystal display and the driving method thereof according to the present invention synchronize the frequency diffusion period of the SDCLK using the spread spectrum with Hsync so that the pulse width of the control signals determined by counting the SDCLK based on the Hsync is a horizontal period. Let each be the same. Accordingly, the liquid crystal display and the driving method thereof according to the present invention can prevent the luminance difference between the horizontal lines caused by the conventional pulse width difference as the pulse width of the control signal is the same for each horizontal period. As a result, according to the liquid crystal display device and the driving method thereof according to the present invention, noise such as a wave pattern does not occur on the display screen of the liquid crystal panel, so that the display quality can be improved.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

A liquid crystal panel having a pixel matrix; A spread spectrum circuit for spreading the frequency of the input clock signal in a period synchronous with the input horizontal synchronization signal to output a spread clock signal; A timing controller for generating a plurality of control signals having a pulse width determined using the spread clock signal; And a liquid crystal panel driver for driving the liquid crystal panel by using control signals from the timing controller. The method of claim 1, The spread spectrum circuit is A modulation frequency generator for generating a modulation frequency having a modulation period in synchronization with the horizontal synchronization signal; And a phase locked loop circuit for generating the spread clock signal having the modulation period and spreading the frequency by using the clock signal and the modulation frequency. The method of claim 1, The timing controller is And counting the spread clock signal based on the horizontal synchronization signal to determine pulse widths of the control signals. The method of claim 3, wherein The timing controller is And the control signals are generated by using a vertical synchronization signal from the outside together with the spread clock signal and a data enable signal indicating an effective period of the pixel data. The method of claim 1, The control signals The liquid crystal panel driver includes a gate start pulse, a gate shift clock, and a gate enable signal required to drive the gate lines of the liquid crystal panel, and a source start pulse required to drive the data lines of the liquid crystal panel. And a source shift clock, a source enable signal, and a polarity control signal. Generating a spread clock signal by spreading a frequency of the input clock signal in a period in synchronization with the input horizontal sync signal; Generating a plurality of control signals having a pulse width determined using the spread clock signal; And driving a liquid crystal panel using the control signals. The method of claim 6, Generating the spread clock signal Generating a modulation frequency having a modulation period in synchronization with the horizontal synchronization signal; And generating the spread clock signal having the modulation period and spreading the frequency by using the clock signal and the modulation frequency. The method of claim 6, Generating the control signals And counting the spread clock signal based on the horizontal synchronization signal to determine pulse widths of the control signals. The method of claim 8, Generating the control signals And generating the control signals by using the vertical synchronization signal from the outside together with the spread clock signal and a data enable signal indicating an effective period of the pixel data. The method of claim 6, The control signals A gate start pulse, a gate shift clock, and a gate enable signal required to drive the gate lines of the liquid crystal panel; a source start pulse, a source shift clock, required to drive the data lines of the liquid crystal panel; A method of driving a liquid crystal display device comprising a source enable signal and a polarity control signal.