KR20040023311A - Method for forming pad of semiconductor drvice - Google Patents
Method for forming pad of semiconductor drvice Download PDFInfo
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- KR20040023311A KR20040023311A KR1020020055022A KR20020055022A KR20040023311A KR 20040023311 A KR20040023311 A KR 20040023311A KR 1020020055022 A KR1020020055022 A KR 1020020055022A KR 20020055022 A KR20020055022 A KR 20020055022A KR 20040023311 A KR20040023311 A KR 20040023311A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
- H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
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Abstract
본 발명은 패드부의 금속 배선을 전체적으로 오픈 시키는 대신 라인-스페이서 구조로 오픈 시킨 후 범퍼 공정으로 Au를 스퍼터링 방식으로 증착하여 갭필링 시킴으로써 보호막과 패드부의 단차로 인해 발생하는 Dimple 현상을 방지할 수 있는 이점이 있다.The present invention has the advantage of preventing the dimple phenomenon caused by the gap between the protective film and the pad portion by gap filling by depositing Au by sputtering method in a bumper process instead of opening the metal wiring of the pad portion as a whole. There is this.
Description
본 발명은 반도체 소자의 패드(PAD)에 관한 것으로서, 보다 상세하게는 반도체장치를 외부 회로와 연결시키는 접속점의 역할을 하는 반도체 소자의패드 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pad (PAD) of a semiconductor device, and more particularly, to a method of forming a pad of a semiconductor device that serves as a connection point for connecting a semiconductor device to an external circuit.
반도체장치의 웨이퍼공정을 통해 웨이퍼 상에 다수의 칩이 완성되면 이 칩들은 개개의 단위로 분할되어 패키지공정을 통해 상용 반도체 칩의 형태를 갖추게 된다. 이때 웨이퍼공정에서는 칩이 회로 상으로 완성되면 형성된 칩을 보호하기 위해서 웨이퍼 표면에 보호막을 형성시키게 되고 패키지공정에서는 패드들을 각각 완성된 반도체 칩에서 외부회로와 접속될 리드선들과 연결시키게 된다.When a plurality of chips are completed on a wafer through a wafer process of a semiconductor device, the chips are divided into individual units to form a commercial semiconductor chip through a package process. In the wafer process, when the chip is completed on the circuit, a protective film is formed on the wafer surface to protect the formed chip. In the packaging process, pads are connected to lead wires to be connected to external circuits in the completed semiconductor chip.
한편, 이러한 연결을 위해서는 일반적으로 반도체장치의 패드 금속(Pad Metal)으로 이루어지는 패드들 위의 부도체 보호막을 제거하여 그 위치의 패드가 드러나게 하는 패드접속부 형성작업이 필요하다. 따라서 완성된 패드접속부는 외부 회로와 연결되기 위한 패드가 드러나고 그 주위는 보호막의 층이 형성되어 있다.On the other hand, in order to make such a connection, it is necessary to form a pad connecting portion for removing the non-conductive protective film on the pads made of pad metal of the semiconductor device so that the pad at the position is exposed. Accordingly, the pad for connecting the completed pad is exposed and the layer of the protective film is formed around the pad.
일반적인 패드구조는 비교적 단순한 패턴을 가지는 넓은 영역의 전도성 금속재료가 산화막 위에 형성되어 이루어진다. 여기서 전도성이 있는 금속재료를 따라 반도체장치의 셀(Cell)부나 논리회로에 전기적인 신호가 입출력되며, 범프(Bump)나 와이어(Wire)를 패키지 프레임과 접착시킴으로써 연결되게 한다.A general pad structure is formed by forming a conductive metal material of a large area having a relatively simple pattern on an oxide film. Herein, an electrical signal is inputted and outputted to a cell part or a logic circuit of a semiconductor device along a conductive metal material, and is connected by bonding a bump or a wire to a package frame.
도1은 종래 기술에 의한 반도체 소자의 패드 구조를 나타낸 단면도이다.1 is a cross-sectional view showing a pad structure of a semiconductor device according to the prior art.
여기에 도시된 바와 같이 소정의 하부 구조가 형성된 반도체 기판(100) 상에제 1 층간 절연막(101) 및 제 2 층간절연막(102)을 순차적으로 형성한다.As shown here, the first interlayer insulating film 101 and the second interlayer insulating film 102 are sequentially formed on the semiconductor substrate 100 on which a predetermined substructure is formed.
이어서, 제 2 층간 절연막 상부에 금속배선(103)을 형성하고, 금속 배선(103)을 매립시키도록 보호막(104)으로 TEOS(Tetra Ethyl Ortho Silicate)막을 증착한 후, 보호막(104) 상에 표면이 평탄해지도록 충분한 두께로 P·SiN을 증착하여 평탄화막(105)을 형성한다.Subsequently, a metal wiring 103 is formed on the second interlayer insulating film, and a TEOS (Tetra Ethyl Ortho Silicate) film is deposited on the protective film 104 to fill the metal wiring 103, and then the surface is formed on the protective film 104. P · SiN is deposited to a sufficient thickness to form the planarization film 105.
그리고 평탄화막(105) 상에 감광막(미도시함)을 도포한 후, 금속배선(103)과 대응되는 부위가 노출되도록 패턴 식각하여 감광막패턴(미도시함)을 형성한 후, 감광막패턴을 마스크로 하여 금속 배선(103)이 노출되는 시점까지 평탄화막(105)과 보호막(104)을 식각하여 패드부를 오픈시킨다.After applying a photoresist film (not shown) on the planarization film 105, pattern etching is performed to expose a portion corresponding to the metal wiring 103 to form a photoresist pattern (not shown), and then the photoresist pattern is masked. As a result, the planarization film 105 and the protection film 104 are etched until the metal wire 103 is exposed to open the pad portion.
이어서, 범프 공정으로 금(Au : 106)을 스퍼터링 방식으로 증착한다.Subsequently, gold (Au) 106 is deposited by a sputtering method in a bump process.
그러나, 이러한 종래 기술에 의한 반도체 소자의 패드 구조는 패드 면적의 대부분을 오픈시켜 금속 배선(103)을 오픈시키기 때문에 보호막(104)과 금속 배선(103) 사이에 1.5~1.7㎛의 단차가 발생하게 된다. 이로 인해 Au(106) 스퍼터링 공정시 중앙 부위에 Dimple이 발생하는 구조적인 문제점이 있었다.However, since the pad structure of the semiconductor device according to the related art opens most of the pad area to open the metal wiring 103, a step of 1.5 to 1.7 μm occurs between the protective film 104 and the metal wiring 103. do. Because of this, there was a structural problem that Dimple occurs in the central portion during the Au (106) sputtering process.
상기와 같은 문제점을 해결하기 위한 본 발명은 패드부의 금속 배선을 전체적으로 오픈 시키는 대신 라인-스페이서 구조로 오픈 시킨 후 범퍼 공정으로 Au를 스퍼터링 방식으로 증착하여 갭필링 시킴으로써 보호막과 패드부의 단차로 인해 발생하는 Dimple 현상을 방지하기 위한 반도체 소자의 패드 형성 방법을 제공하는 것이다.The present invention for solving the above problems is to open the line-spacer structure instead of open the metal wiring of the pad portion as a whole, and then deposited by a gap sputtering method by a bumper process, gap filling by the gap between the protective film and the pad portion The present invention provides a method for forming a pad of a semiconductor device to prevent a dimple phenomenon.
도1은 종래 기술에 의한 반도체 소자의 패드 구조를 나타낸 단면도이다.1 is a cross-sectional view showing a pad structure of a semiconductor device according to the prior art.
도2는 본 발명에 의한 반도체 소자의 패드 구조를 타나낸 도면이다.2 is a view showing a pad structure of a semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
100 : 반도체 기판 101 : 제 1 층간 절연막100 semiconductor substrate 101 first interlayer insulating film
102 : 제 2 층간 절연막 103 : 금속 배선102 second interlayer insulating film 103 metal wiring
104 : 보호막 105 : 평탄화막104: protective film 105: planarization film
106 : Au106: Au
상기와 같은 목적을 실현하기 위한 본 발명은 소정의 하부 구조가 형성된 반도체 기판 상에 제 1 층간 절연막 및 제 2 층간절연막을 순차적으로 형성하는 단계와, 상기 제 2 층간 절연막 상부에 금속배선을 형성하고 금속 배선을 매립시키도록 보호막을 증착하는 단계와, 상기 보호막 상부에 표면이 평탄해지도록 평탄화막을 증착하는 단계와, 상기 평탄화막 상에 감광막을 도포한 후, 상기 금속배선과 대응되는 부위가 노출되도록 라인-스페이스 구조로 감광막패턴을 형성하는 단계와, 상기 라인-스페이서 구조의 감광막 패턴을 이용하여 금속 배선이 노출되는 시점까지 평탄화막과 보호막을 패터닝하는 단계와, 상기 라인-스페이서 구조로 패터닝된 결과물 상에 범프 공정으로 금을 스퍼터링 방식으로 증착하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 패드 형성 방법에 관한 것이다.According to an aspect of the present invention, a first interlayer insulating film and a second interlayer insulating film are sequentially formed on a semiconductor substrate on which a predetermined substructure is formed, and metal wiring is formed on the second interlayer insulating film. Depositing a passivation film to fill the metal wiring; depositing a planarization film to flatten the surface on the passivation film; and applying a photoresist film on the planarization film to expose a portion corresponding to the metal wiring. Forming a photoresist pattern with a line-space structure, patterning the planarization film and the passivation layer until the metal wiring is exposed using the photoresist pattern of the line-spacer structure, and patterning the patterned structure with the line-spacer structure Depositing gold on a bump process in a bump process on a peninsula It relates to a pad forming method of the sieve element.
상기 보호막은 TEOS막으로 형성하는 것을 특징으로 하고, 상기 평탄화막은 질화막으로 형성하는 것을 특징으로 한다.The protective film may be formed of a TEOS film, and the planarization film may be formed of a nitride film.
상기 라인-스페이서 구조의 패턴으로 형성하는 대신 홀 또는 고립형 패턴으로 형성하는 것을 특징으로 한다.Instead of forming the pattern of the line-spacer structure is characterized in that formed in a hole or an isolated pattern.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도2는 본 발명에 의한 반도체 소자의 패드 구조를 타나낸 도면이다.2 is a view showing a pad structure of a semiconductor device according to the present invention.
여기에 도시된 바와 같이, 소정의 하부 구조가 형성된 반도체 기판(100) 상에 제 1 층간 절연막(101) 및 제 2 층간절연막(102)을 순차적으로 형성한다.As shown here, the first interlayer insulating film 101 and the second interlayer insulating film 102 are sequentially formed on the semiconductor substrate 100 on which a predetermined substructure is formed.
이어서, 제 2 층간 절연막 상부에 금속배선(103)을 형성하고, 금속 배선(103)을 매립시키도록 보호막(104)으로 TEOS(Tetra Ethyl Ortho Silicate)막을 증착한 후, 보호막(104) 상에 표면이 평탄해지도록 충분한 두께로 P·SiN을 증착하여 평탄화막(105)을 형성한다.Subsequently, a metal wiring 103 is formed on the second interlayer insulating film, and a TEOS (Tetra Ethyl Ortho Silicate) film is deposited on the protective film 104 to fill the metal wiring 103, and then the surface is formed on the protective film 104. P · SiN is deposited to a sufficient thickness to form the planarization film 105.
그리고 평탄화막(105) 상에 감광막(미도시함)을 도포한 후, 금속배선(103)과 대응되는 부위가 노출되도록 패턴 식각하여 감광막패턴(미도시함)을 형성한다.After applying a photoresist film (not shown) on the planarization film 105, a pattern is etched to expose a portion corresponding to the metal wiring 103 to form a photoresist pattern (not shown).
이때 감광막 패턴은 라인-스페이스 구조로 형성하여 감광막패턴을 마스크로 하여 금속 배선(103)이 노출되는 시점까지 평탄화막(105)과 보호막(104)을 라인-스페이서 구조로 패터닝한다.In this case, the photoresist pattern is formed in a line-space structure, and the planarization film 105 and the passivation layer 104 are patterned in a line-spacer structure until the metal wiring 103 is exposed using the photoresist pattern as a mask.
이어서, 범프 공정으로 금(Au : 106)을 스퍼터링 방식으로 증착하면 오픈된 평탄화막(105) 사이로 Au(106)이 갭필링되고 전체적인 범프 형상이 Dimple 문제없이 평탄하게 형성된다.Subsequently, when gold (Au) 106 is deposited by a sputtering method in a bump process, Au 106 is gap-filled between the open planarization films 105 and the overall bump shape is formed flat without a Dimple problem.
상기한 바와 같이 본 발명은 패드부의 금속 배선을 전체적으로 오픈 시키는 대신 라인-스페이서 구조로 오픈 시킨 후 범퍼 공정으로 Au를 스퍼터링 방식으로증착하여 갭필링 시킴으로써 보호막과 패드부의 단차로 인해 발생하는 Dimple 현상을 방지할 수 있는 이점이 있다.As described above, the present invention prevents the dimple phenomenon caused by the gap between the passivation layer and the pad part by gap-filling by depositing Au by sputtering method in the bumper process instead of opening the metal wiring of the pad part as a whole. There is an advantage to this.
또한, 평탄화막과 Au 간의 접촉 면적이 증가하여 쉬어 테스트 페일(Ball Shear Test Fail)을 제거할 수 있는 이점이 있다.In addition, there is an advantage that the contact area between the planarization layer and Au is increased to remove a ball shear test fail.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100731081B1 (en) * | 2005-12-30 | 2007-06-22 | 동부일렉트로닉스 주식회사 | How passivation is formed |
| US10714438B2 (en) | 2018-01-03 | 2020-07-14 | Samsung Electronics Co., Ltd. | Semiconductor device having metal bump and method of manufacturing the same |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100731081B1 (en) * | 2005-12-30 | 2007-06-22 | 동부일렉트로닉스 주식회사 | How passivation is formed |
| US10714438B2 (en) | 2018-01-03 | 2020-07-14 | Samsung Electronics Co., Ltd. | Semiconductor device having metal bump and method of manufacturing the same |
| US11037894B2 (en) | 2018-01-03 | 2021-06-15 | Samsung Electronics Co., Ltd. | Semiconductor device having metal bump and method of manufacturing the same |
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