KR20040008528A - Method for manufacturing a flash memory device - Google Patents

Abstract

The present invention relates to a method of manufacturing a flash memory device, wherein the etching step for patterning the floating gate and the control gate is omitted by forming an isolated floating gate using a mask pattern and then forming a control gate using a damascene method. The production of by-products is prevented, and the steps of the entire process are reduced, and the floating gate and the control gate are formed in the trench by the damascene method, so that it is also applicable to the manufacture of ultra-high integrated devices having design rules of 0.13 mu m or less.

Description

Method for manufacturing a flash memory device {Method for manufacturing a flash memory device}

The present invention relates to a method of manufacturing a flash memory device, and more particularly, to form an isolated floating gate using a mask pattern and to form a control gate using a damascene method so as to enable the manufacture of an ultra-high density device. A method of manufacturing a flash memory device.

As the degree of integration of semiconductor memory devices increases, the size of memory cells also decreases. Therefore, in implementing a flash memory device, a device isolation layer using a shallow trench is formed to secure a ratio of memory cells per wafer.

The reduction of the size of the pattern due to the reduction of the design rule causes a problem regarding the reliability of the device. Recently, a self-aligned floating gate (SAFG) was formed by forming a device isolation layer using a micro trench and forming a self-aligned floating gate (SAFG) to secure a wider channel length than the cell size. Silicon and tungsten silicide (WSi) are formed in a stacked structure or tungsten (W) to reduce the resistance value.

Conventionally, as shown in FIG. 1A, after the tunnel oxide film 2 and the first polysilicon layer 3 are formed on the silicon substrate 1, the silicon substrate 1 of the device isolation region is formed using a predetermined mask pattern. The first polysilicon layer 3 and the tunnel oxide film 2 are patterned so as to be exposed, and the fine silicon substrate 4 is formed by etching the exposed silicon substrate 1 to a predetermined depth. The oxide film 5 is formed on the entire upper surface so that the trench 4 is embedded, and then the oxide film 5 is removed and planarized by a chemical mechanical polishing (CMP) method. An element isolation film 5 is formed. After forming the dielectric film 6, the second polysilicon layer 7, the tungsten silicide layer 8 and the nitride film 9 on the entire upper surface as shown in Figure 1c, the nitride film 9, tungsten silicide by a self-aligned etching method The layer 8 and the second polysilicon layer 7 are patterned to form a control gate as shown in FIG. 1D.

In the process of forming a floating gate (SAFG) using a conventional self-aligned etching process, the first polysilicon layer 3 is patterned in the direction of a word line as shown in FIG. In the process of forming the gate is patterned in the bit line direction as shown in Figure 1d.

However, in the reactive ion etching (RIE) process for forming the control gate, since several layers having high steps are etched simultaneously, by-products generated by the etching reactants are generated, and damage to the semiconductor substrate due to overetching occurs.

As the integration degree of the device is increased, the design rule is further reduced, so that the step is further increased, making it difficult to proceed with reactive ion etching as described above, and the subsequent step is difficult due to the high step of the gate. For example, it is difficult to fill an insulating film between gates, and an etching process having a high etching ratio of an oxide film and an oxide film to protect the gate when forming a contact hole for connection with an upper metal layer is required. Since it is further reduced, the critical dimension of the contact hole is reduced, making it difficult to secure a contact resistance below a certain value.

In addition, before the control gate is formed, the tunnel oxide film 2 and the first polysilicon layer 3 formed on the semiconductor substrate 1 in the peripheral circuit region must be removed, thereby removing the peripheral circuit region and the memory cell region. When a step is generated, a contact hole is not normally formed in a peripheral circuit area having a low step when forming a contact hole for connection with a metal layer.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor memory device which can solve the above disadvantages by forming an isolated floating gate using a mask pattern and then forming a control gate using a damascene method.

The present invention for achieving the above object is to form a mask layer on the semiconductor substrate and then patterning, etching the exposed semiconductor substrate to a predetermined depth to form a trench, the trench in the direction crossing the trench Patterning the mask layer to be formed, forming an oxide film on the entire upper surface of the trench to fill the trench, and then planarizing the oxide layer by removing the oxide layer until the mask layer is exposed. Wet etching the oxide film remaining on the semiconductor substrate by a predetermined thickness, forming a tunnel oxide film and a floating gate on the semiconductor substrate between the remaining oxide film patterns, and removing the oxide pattern pattern remaining on the semiconductor substrate. After the impurity ions are implanted into the exposed semiconductor substrate, the source / drain Forming an etch stop layer on the entire upper surface, and forming an insulating film on the entire upper surface such that the gap between the floating gate is filled and planarized; and the insulating film and the etch such that a predetermined portion of the floating gate is exposed. Patterning the prevention film, sequentially forming a dielectric film, a polysilicon layer, and a metal layer on the entire upper surface, and removing and planarizing the metal layer until the polysilicon layer is exposed, thereby flattening the polysilicon layer and the metal layer. It characterized in that it comprises a step to form a control gate consisting of.

The floating gate is formed by sequentially forming a tunnel oxide film and a polysilicon layer on the entire upper surface, and removing and planarizing the polysilicon layer and the tunnel oxide film until the oxide film is exposed. .

And removing the dielectric film in the peripheral circuit area from forming the dielectric film.

1A to 1D are cross-sectional views of a device for explaining a method of manufacturing a conventional flash memory device.

2 and 3 are layout views for explaining a method of manufacturing a flash memory device according to the present invention.

4A to 9A are cross-sectional views cut along the A1-A2 portion of FIG.

4B to 9B are cross-sectional views cut along the B1-B2 portion of FIG.

<Explanation of symbols for the main parts of the drawings>

1 and 11: semiconductor substrates 2 and 14: tunnel oxide film

3 and 15: first polysilicon layer 4: trench

5 and 13a: device isolation films 6 and 19: dielectric film

7 and 20: second polysilicon layer 8: tungsten silicide layer

9: nitride films 10a and 10b: trenches

12: pad nitride film 13: oxide film

16: source / drain 17: etch barrier

18: insulating film 21: metal layer

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 and 3 are layout views for explaining a method of manufacturing a flash memory device according to the present invention. FIGS. 4A to 9A are cross-sectional views taken along the line A1-A2 of FIG. 2, and FIGS. It is sectional drawing which cut | disconnected the B1-B2 part of FIG.

4A and 4B, a pad oxide film 11 and a pad nitride film 12 are formed on the semiconductor substrate 10. The pad nitride layer 12 and the pad oxide layer 11 are patterned by using an isolation mask, and the exposed semiconductor substrate 10 is etched to a predetermined depth to form the trench 10a as shown in FIG. 3. The pad nitride film 12 and the pad oxide film 11 are patterned to form the trench 10b in a direction perpendicular to the trench 10a using a predetermined mask. That is, the pad nitride film 12 and the pad oxide film 11 are first patterned on the semiconductor substrate 10 to form the trenches 10a in the bit line (not shown) direction of the semiconductor substrate 10. The pad nitride layer 12 and the pad oxide layer 11 are patterned in a secondary manner so that the trench 10b is formed in the direction of the word line 21.

Afterwards, an oxide film 13 is formed on the entire upper surface of the trenches 10a and 10b so that the trenches 10a and 10b are embedded, and the oxide film 13 is polished until the pad nitride film 12 is exposed by chemical mechanical polishing (CMP). Planarize.

The pad nitride film 12 is formed to a thickness of 2000 to 4000 kPa, and the oxide film 13 uses a high density plasma (High Density Plasma) oxide film. In addition, after the trench 10a is formed, an oxidation process is performed to compensate for damage of the sidewalls of the trench 10a due to etching.

5A and 5B, after removing the pad nitride layer 12 and the pad oxide layer 11, the oxide layer 13 remaining on the semiconductor substrate 10 is etched by a predetermined thickness. At this time, the size of the oxide film 13 is reduced by the isotropic etching to increase the distance between the remaining oxide film 13, the distance between the oxide film 13 to be the width of the floating gate.

6A and 6B, after the ion implantation process such as the threshold voltage control, the tunnel oxide layer 14 and the first polysilicon layer 15 are sequentially formed on the entire upper surface thereof, and chemical mechanical polishing (CMP) is performed. The floating gate 15 is formed by removing the first polysilicon layer 15 and the tunnel oxide layer 14 until the oxide layer 13 is exposed by the method.

7A and 7B, after removing the oxide layer 13 remaining on the semiconductor substrate 10, impurity ions are implanted into the exposed portion of the semiconductor substrate 10 to form a source / drain 16. . In this case, the isolation layer 13a remains only in the trench 10a by removing the oxide layer 13 remaining on the semiconductor substrate 10.

Referring to FIGS. 8A and 8B, after forming the etch stop layer 17 on the entire upper surface, the insulating layer 18 is formed on the entire upper surface such that the space between the floating gates 15 is completely filled and planarized. In this case, a nitride film is used as the etch stop layer 17, and the thickness of the insulating layer 18 is the thickness of the control gate.

9A and 9B, a trench is formed to expose a predetermined portion of the control gate 15 by patterning the insulating layer 18 and the etch stop layer 17 to form a control gate by a damascene method. In this case, the damage of the floating gate 15 is prevented by the etch stop layer 17.

After the dielectric film 19, the second polysilicon layer 20, and the metal layer 21 are sequentially formed on the entire upper surface, the time point at which the second polysilicon layer 20 is exposed by chemical mechanical polishing (CMP) method By removing the metal layer 21, a control gate including the second polysilicon layer 20 and the metal layer 21 is formed on the floating gate 15. The second polysilicon layer 20 is used as an etch stop layer when the metal layer 21 is removed, and almost no loss of the metal layer 21 occurs when the second polysilicon layer 20 is removed. .

Here, after the dielectric film 19 is formed, the dielectric film 19 in the peripheral circuit region is removed so that the gate electrode of the transistor including the first polysilicon layer 15 and the second polysilicon layer 20 is formed. do.

The dielectric film 19 has a structure in which an oxide film, a nitride film, and an oxide film are stacked, and the second polysilicon layer 20 is formed to a thickness of 300 to 700 GPa, and the metal layer 21 is tungsten silicide (WSi). To form a thickness of 1000 to 3000 1000.

Thereafter, an insulating film is formed on the entire upper surface such that the gap between the gates 15 and 21 is completely filled, and then the insulating film is patterned to expose the drain 16 to form a contact hole, and the drain hole is formed through the contact hole. The bit line is formed to be connected with

As described above, the present invention forms an isolated floating gate using a mask pattern and then forms a control gate using a damascene method. Therefore, using the present invention, firstly, an etching step for patterning the floating gate and the control gate is omitted, thereby preventing the generation of etching by-products and reducing the steps of the entire process. Second, since the floating gate and the control gate are formed in the trench by the damascene method, it is also applicable to the fabrication of an ultra-high integration device having a design rule of 0.13 μm or less. Third, since the step difference between the stacked floating gate and the control gate is about 2750 to 3000Å, the step difference can be reduced by about 50% compared to the prior art, and the gate electrodes of the transistors formed in the peripheral circuit region are formed into the first and second polysilicon layers. By doing so, the step between the memory cell area and the peripheral circuit area is minimized.

Claims (10)

Forming a trench by forming a mask layer on the semiconductor substrate and etching the exposed portion of the semiconductor substrate to a predetermined depth; Patterning the mask layer to form a trench in a direction crossing the trench; Forming an oxide film on the entire upper surface of the trench to fill the trench, and then removing and planarizing the oxide film until the mask layer is exposed; Removing the mask layer and wet etching an oxide film remaining on the semiconductor substrate, Forming a tunnel oxide film and a floating gate on the semiconductor substrate between the remaining oxide pattern; Removing the oxide pattern remaining on the semiconductor substrate and implanting impurity ions into the exposed semiconductor substrate to form a source / drain; Forming an insulating film on the entire upper surface to form an etch stop layer on the entire upper surface and to planarize the gap between the floating gates; Patterning the insulating layer and the etch stop layer to expose a predetermined portion of the floating gate; Sequentially forming a dielectric film, a polysilicon layer, and a metal layer on the entire upper surface; And removing and planarizing the metal layer until a time point at which the polysilicon layer is exposed to form a control gate formed of the polysilicon layer and the metal layer. The method of claim 1, wherein the mask layer is formed of a pad oxide film and a pad nitride film. The method of claim 1, further comprising performing an oxidation process to compensate damage of the trench sidewalls due to etching from forming the trench. The method of manufacturing a flash memory device according to claim 1, wherein the oxide film is a high density plasma oxide film. The method of claim 1, further comprising ion implanting the semiconductor layer exposed from the wet etching of the oxide layer by a predetermined thickness to adjust a threshold voltage or the like. The method of claim 1, wherein the floating gate comprises sequentially forming a tunnel oxide film and a polysilicon layer on an entire upper surface thereof; And removing and planarizing the polysilicon layer and the tunnel oxide layer until a time point at which the oxide layer is exposed. The method of claim 1, wherein the etch stop layer is a nitride layer. The method of claim 1, wherein the metal layer is made of tungsten silicide and is formed to a thickness of 1000 to 3000 microns. The method of claim 1, wherein the planarization is performed by a chemical mechanical polishing method. 2. The method of claim 1, further comprising removing the dielectric film in a peripheral circuit area from forming the dielectric film.