KR20040001544A - Method for isolation film in semiconductor device - Google Patents
Method for isolation film in semiconductor device Download PDFInfo
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- KR20040001544A KR20040001544A KR1020020036776A KR20020036776A KR20040001544A KR 20040001544 A KR20040001544 A KR 20040001544A KR 1020020036776 A KR1020020036776 A KR 1020020036776A KR 20020036776 A KR20020036776 A KR 20020036776A KR 20040001544 A KR20040001544 A KR 20040001544A
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000002955 isolation Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 150000004767 nitrides Chemical class 0.000 claims abstract description 25
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000005498 polishing Methods 0.000 claims abstract description 7
- 238000004140 cleaning Methods 0.000 claims abstract description 6
- 239000007789 gas Substances 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 2
- 229910001882 dioxygen Inorganic materials 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- 229920000642 polymer Polymers 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 2
- 238000012805 post-processing Methods 0.000 abstract 1
- 238000001312 dry etching Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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Abstract
본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 반도체 기판상에 패드 산화막과 질화막 및 BARC/PR막을 형성하는 단계; 상기 BARC/PR막을 선택적으로 제거하여 BARC/PR 패턴을 형성하는 단계; 상기 BARC/PR 패턴을 마스크로 하는 식각으로 상기 기판이 노출되도록 상기 질화막과 패드 산화막을 선택적으로 제거하는 단계; 상기 노출된 기판 일부를 제거하여 제1경사부를 형성하는 단계; 상기 제1경사부가 형성된 기판을 선택적으로 제거하여 2중 경사를 갖는 트렌치를 형성하고 후처리하는 단계; 상기 BARC/PR 패턴을 일부 제거하고 이를 마스크로 하는 식각으로 선택적으로 제거된 질화막 및 패드 산화막을 일부 제거하는 단계; 상기 트렌치 내면에 측벽 산화막을 형성하는 단계; 상기 트렌치를 매립하도록 상기 기판 전면에서 필드 산화막을 형성하고 연마하는 단계; 상기 질화막 및 패드 산화막을 제거하여 상기 트렌치내에 소자분리막을 형성하는 단계; 및 상기 기판을 세정하는 단계를 포함하며, 2중 경사를 갖는 트렌치 모서리 형태에 의해 응력 집중을 최소화할 수 있으며, 트렌치 형성후 다시 PR 패턴 폭을 넓혀 줌으로써 갭 필(gap fill) 폭이 넓어져 모우트가 발생하지 않게 되어 험프(hump) 및 서브문턱전압(subthreshold) 등의 소자의 전기적 특성이 향상되는 효과가 있는 것이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, comprising: forming a pad oxide film, a nitride film, and a BARC / PR film on a semiconductor substrate; Selectively removing the BARC / PR film to form a BARC / PR pattern; Selectively removing the nitride layer and the pad oxide layer to expose the substrate by etching using the BARC / PR pattern as a mask; Removing a portion of the exposed substrate to form a first inclined portion; Selectively removing the substrate on which the first inclined portion is formed to form a trench having a double inclination and post-processing the trench; Partially removing the BARC / PR pattern and partially removing the nitride film and the pad oxide film selectively removed by etching using the BARC / PR pattern as a mask; Forming a sidewall oxide layer on the inner surface of the trench; Forming and polishing a field oxide film over the entire surface of the substrate to fill the trench; Removing the nitride layer and the pad oxide layer to form an isolation layer in the trench; And cleaning the substrate, wherein stress concentration can be minimized by a trench edge shape having a double slope, and a gap fill width is widened by widening the PR pattern width after trench formation. There is an effect that the electrical characteristics of the device, such as the hump (hump) and sub-threshold voltage (improved) is improved because the trap is not generated.
Description
본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 보다 상세하게는 모우트를 최소화하여 소자의 특성 열화를 방지할 수 있는 반도체 소자의 소자분리막 형성방법에 관한 것이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device that can prevent deterioration of device characteristics by minimizing the moat.
일반적으로 반도체 소자를 제조하는데 있어서 트랜지스터와 캐패시터 등을 형성하기 위하여 반도체 기판에는 전기적으로 통전이 가능한 활성 영역(activeregion)과 전기적으로 통전되는 것을 방지하고 소자를 전기적으로 분리하도록 하는 소자분리 영역(isolation region)을 형성한다.In general, in the fabrication of semiconductor devices, in order to form transistors, capacitors, and the like, an isolation region is formed in the semiconductor substrate to prevent electrically conduction from an electrically conducting active region and to electrically isolate the device. ).
위와 같은 소자분리 영역 형성에는 반도체 기판상의 패드 산화막과 질화막에 대한 마스크 공정과 산화 공정으로 소자를 분리하는 LOCOS(local oxidation of silicon) 공정과, LOCOS 공정의 패드 산화막과 질화막 사이에 버퍼 역할을 하는 폴리실리콘막을 개재하여 완충역할을 하여 필드산화막을 성장시키는 PBL (poly buffered LOCOS) 공정 등이 사용된다.Formation of the device isolation region as described above includes a LOCOS (local oxidation of silicon) process that separates the device by a mask process and an oxidation process for the pad oxide film and the nitride film on the semiconductor substrate, and a poly which serves as a buffer between the pad oxide film and the nitride film of the LOCOS process. A PBL (poly buffered LOCOS) process is used to grow a field oxide film by acting as a buffer via a silicon film.
최근의 0.25㎛ 이하의 반도체 소자의 소자분리막 형성에는 STI(shallow trench isolation) 공정이 사용된다.In recent years, a shallow trench isolation (STI) process is used to form a device isolation film of a semiconductor element of 0.25 µm or less.
종래 기술에 따른 반도체 소자의 소자분리막 형성방법은 먼저 반도체 기판에 일정한 깊이를 갖는 트렌치(trench)를 형성하고, 상기 트렌치를 비롯한 기판 전면상에 산화막을 증착시킨다.In the method of forming a device isolation film of a semiconductor device according to the related art, a trench having a predetermined depth is first formed in a semiconductor substrate, and an oxide film is deposited on the entire surface of the substrate including the trench.
이어서, CMP(chemical mechanical polishing) 공정으로 불필요한 산화막을 식각한 후 세정 공정 등을 진행하여 소자분리막 형성을 완성한다.Subsequently, the unnecessary oxide film is etched by a chemical mechanical polishing (CMP) process and then a cleaning process is performed to complete the formation of the device isolation film.
그러나, 종래 기술에 따른 반도체 소자의 소자분리막 형성방법에 있어서는 다음과 같은 문제점이 있다.However, the method of forming a device isolation film of a semiconductor device according to the prior art has the following problems.
종래 기술에 있어서는, 트렌치의 상부 모서리와 하부 모서리에 응력이 집중되어 소자 특성이 저하되는 것과 갭 필(gap fill)의 많은 어려움과 CMP 공정 적용으로 인해 공정이 복잡해지고 균일성(uniformity)이 좋지 않게 되는 문제점이 있다.In the prior art, stress is concentrated on the upper and lower edges of the trench, resulting in deterioration of device characteristics, many difficulties in gap fill, and the application of CMP processes, resulting in complex processes and poor uniformity. There is a problem.
또한, 소자분리막 형성후 이어지는 식각 및 세정 공정에서 소자분리막의 양측 모서리 부분이 과도하게 식각되어 나타나는 모우트(moat)에 의해 험프(hump) 특성 등의 소자 특성을 열화시키는 문제점도 있다.In addition, there is a problem in that device characteristics such as a hump characteristic are deteriorated by a moat that is caused by excessive etching of both edge portions of the device isolation layer in the etching and cleaning processes following the formation of the device isolation layer.
이에 본 발명은 상기한 종래 기술상의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 모서리부를 2중 경사 형태로 형성하고 트렌치 형성후 다시 PR 패턴 폭을 넓혀 줌으로써 모우트 형성을 방지할 수 있는 반도체 소자의 소자분리막 형성방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above-mentioned problems in the prior art, an object of the present invention is to form a corner portion in a double inclined shape and widen the PR pattern width after the trench formation to prevent the formation of the moat The present invention provides a method for forming a device isolation film of a semiconductor device.
도 1 내지 도 9는 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 도시한 공정별 단면도.1 to 9 are cross-sectional views illustrating processes of forming an isolation layer of a semiconductor device in accordance with the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100; 반도체 기판200,200a,200b; 패드 산화막100; Semiconductor substrates 200, 200a and 200b; Pad oxide
300,300a,300b; 질화막400,400a,400b; BARC/PR300,300a, 300b; Nitride films 400, 400a and 400b; BARC / PR
500; 트렌치600; 측벽 산화막500; Trench 600; Sidewall oxide
700,700a,700b; 필드산화막(소자분리막)700,700a, 700b; Field Oxide (Device Separation)
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 소자분리막 형성방법은, 반도체 기판상에 패드 산화막과 질화막 및 BARC/PR막을 형성하는 단계; 상기 BARC/PR막을 선택적으로 제거하여 BARC/PR 패턴을 형성하는 단계; 상기 BARC/PR 패턴을 마스크로 하는 식각으로 상기 기판이 노출되도록 상기 질화막과 패드 산화막을 선택적으로 제거하는 단계; 상기 노출된 기판 일부를 제거하여 제1경사부를 형성하는 단계; 상기 제1경사부가 형성된 기판을 선택적으로 제거하여 2중 경사를 갖는 트렌치를 형성하는 단계; 상기 트렌치를 후처리하는 단계; 상기 BARC/PR 패턴을 일부 제거하는 단계; 상기 일부 제거된 BARC/PR 패턴을 마스크로 하는 식각으로 선택적으로 제거된 질화막 및 패드 산화막을 일부 제거하는 단계; 상기 BARC/PR 패턴을 제거하고 상기 트렌치 내면에 측벽 산화막을 형성하는 단계; 상기 트렌치를 매립하도록 상기 기판 전면에서 필드 산화막을 형성하는 단계; 상기 질화막이 노출되도록 상기 필드 산화막을 화학적 기계적 연마하는 단계; 상기 질화막 및 패드 산화막을 제거하여 상기 트렌치내에 필드 산화막이 매립된 형태의 소자분리막을 형성하는 단계; 및 상기 소자분리막이 형성된 기판을 세정하는 단계를 포함하는 것을 특징으로 한다.A device isolation film forming method of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a pad oxide film, a nitride film and a BARC / PR film on a semiconductor substrate; Selectively removing the BARC / PR film to form a BARC / PR pattern; Selectively removing the nitride layer and the pad oxide layer to expose the substrate by etching using the BARC / PR pattern as a mask; Removing a portion of the exposed substrate to form a first inclined portion; Selectively removing the substrate on which the first inclined portion is formed to form a trench having a double inclination; Post-treating the trench; Removing part of the BARC / PR pattern; Partially removing the nitride film and the pad oxide film selectively removed by etching using the partially removed BARC / PR pattern as a mask; Removing the BARC / PR pattern and forming a sidewall oxide layer on the inner surface of the trench; Forming a field oxide film on the entire surface of the substrate to fill the trench; Chemical mechanical polishing the field oxide layer to expose the nitride layer; Removing the nitride layer and the pad oxide layer to form a device isolation layer in which a field oxide layer is embedded in the trench; And cleaning the substrate on which the device isolation film is formed.
본 발명에 의하면, 2중 경사를 갖는 트렌치 모서리 형태에 의해 응력 집중을 최소화할 수 있으며, 트렌치 형성후 다시 PR 패턴 폭을 넓혀 줌으로써 갭 필(gap fill) 폭이 넓어져 모우트가 발생하지 않게 된다.According to the present invention, it is possible to minimize the stress concentration by the trench edge shape having a double inclination, and widen the gap fill width by widening the PR pattern width after the trench formation, so that no moat occurs. .
이하, 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a device isolation film of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 9는 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 도시한 공정별 단면도이다.1 to 9 are cross-sectional views of processes illustrating a method of forming an isolation layer of a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 소자분리막 형성방법은, 도 1에 도시된 바와 같이, 반도체 기판(100)상에 패드 산화막(200)과 질화막(300) 및 BARC(bottom anti reflective coating)/PR(photoresist)(400)을 순차로 형성한다.In the device isolation film forming method of the semiconductor device according to the present invention, as shown in FIG. 1, the pad oxide film 200, the nitride film 300, and BARC (bottom anti reflective coating) / PR (photoresist) on the semiconductor substrate 100. ) 400 is sequentially formed.
예를 들어, 상기 패드 산화막(200)은 50~300Å 두께로 형성하고, 상기 질화막(300)은 1,000~2,000Å 두께로 형성한다.For example, the pad oxide film 200 is formed to a thickness of 50 ~ 300 Å, the nitride film 300 is formed to a thickness of 1,000 ~ 2,000 Å.
이어서, 도 2에 도시된 바와 같이, 상기 BARC/PR막(400)을 사진 공정으로 패터닝하여 BARC/PR 패턴(400a)을 형성한 후 상기 BARC/PR 패턴(400)을 마스크로 하는 건식각 공정으로 상기 기판(100)이 노출되도록 상기 질화막(300) 및 패드 산화막(200)을 선택적으로 제거한다.Subsequently, as shown in FIG. 2, the BARC / PR film 400 is patterned by a photo process to form a BARC / PR pattern 400a, and then a dry etching process using the BARC / PR pattern 400 as a mask. The nitride film 300 and the pad oxide film 200 are selectively removed to expose the substrate 100.
그런다음, CHF3와 CF4가스를 이용하여 폴리머(polymer)가 노출된 기판(100) 표면에 적층되도록 하면서 상기 기판(100)을 200Å 깊이로 과도식각(over etch)하여 제1경사부(A)를 형성한다.Then, the first inclined portion (A) is overetched by using a CHF 3 and CF 4 gas so as to stack the polymer on the exposed surface of the substrate 100 to a depth of 200 μs. ).
이때, 상기 제1경사부(A)를 형성하는 단계는 50~70sccm의 CHF3와 30~50sccm의 CF4가스비를 조절하여 상기 제1경사부(A)의 폭은 0.05㎛로 형성하고 상기 제1경사부(A)의 경사는 상기 기판(100) 표면을 중심으로 20~50°를 갖도록 하게 한다.At this time, the step of forming the first inclined portion (A) is 50 to 70 sccm CHF 3 and 30 to 50 sccm CF 4 gas ratio by adjusting the width of the first inclined portion (A) is formed to 0.05㎛ and the The inclination of the one inclined portion A is 20 to 50 ° with respect to the surface of the substrate 100.
그다음, 도 3에 도시된 바와 같이, 상기 제1경사부(A)가 형성되어 있는 노출된 기판(100)을 선택적으로 제거하여 2,500~40,000Å 깊이의 트렌치(500)를 형성한다. 상기 트렌치(500)를 형성하는 단계는 100~150sccm의 HBr과 35~70sccm의 Cl2가스비 조절을 통하여 상기 트렌치(500)의 측면 경사를 상기 기판(100) 표면을 중심으로 70~90°로 형성한다.3, the exposed substrate 100 on which the first inclined portion A is formed is selectively removed to form a trench 500 having a depth of 2,500 to 40,000 Å. The step of forming the trench 500 forms a side slope of the trench 500 at 70 to 90 ° with respect to the surface of the substrate 100 by adjusting the HBr of 100 to 150 sccm and Cl 2 gas ratio of 35 to 70 sccm. do.
그러면, 상기 트렌치(500)는 20~50°의 제1경사부(A)를 갖는 상면 모서리부와 70~90°경사를 갖는 측면부를 갖게 된다. 즉, 이중 경사를 갖는 트렌치(500)가 형성된다.Then, the trench 500 has an upper edge portion having a first inclined portion A of 20 to 50 ° and a side portion having a 70 to 90 ° inclination. In other words, a trench 500 having a double slope is formed.
이어서, 상기 트렌치(500)를 형성한 후에는 후처리를 40~50초 동안 진행하여Subsequently, after the trench 500 is formed, the post treatment is performed for 40 to 50 seconds.
상기 트렌치(500)내의 손상된 기판(100) 표면을 보완한다.Complement the damaged substrate 100 surface in the trench (500).
다음으로, 도 4에 도시된 바와 같이, 1,000sccm의 Ar과 50~200sccm의 O2가스비를 이용하는 건식각 공정을 사용하여 상기 BARC/PR 패턴(400a)을 일부 제거하여일부 제거된 BARC/PR 패턴(400b) 폭이 상기 트렌치(500) 폭보다 상대적으로 넓도록 형성한다.Next, as shown in FIG. 4, the BARC / PR pattern partially removed by partially removing the BARC / PR pattern 400a using a dry etching process using an Ar gas of 1,000 sccm and an O 2 gas ratio of 50 to 200 sccm. A width 400b is formed to be relatively wider than the width of the trench 500.
계속하여, 상기 일부 제거된 BARC/PR 패턴(400b)을 마스크로 하는 건식각으로 상기 기판(100)상의 질화막(300a)과 패드 산화막(200a)을 일부 제거하여 상기 일부 제거된 BARC/PR 패턴(400b)과 정렬되는 질화막(300a)과 패드 산화막(200a)으로 형성한다.Subsequently, the nitride film 300a and the pad oxide film 200a on the substrate 100 are partially removed by dry etching using the partially removed BARC / PR pattern 400b as a mask. It is formed of a nitride film 300a and a pad oxide film 200a aligned with 400b.
그다음, 도 5에 도시된 바와 같이, 상기 일부 제거된 BARC/PR 패턴(400b)을 제거하고 상기 트렌치(500) 내면에 측벽 산화막(600)을 형성한다. 상기 측벽 산화막(600) 형성 공정은 1050℃의 건조 산소 가스를 이용한 산화 공정으로 100Å 두께로 형성하여 상기 트렌치(500)의 모서리부를 전단계의 후처리에 이어서 재보완하는 것이다.Next, as shown in FIG. 5, the partially removed BARC / PR pattern 400b is removed and a sidewall oxide film 600 is formed on the inner surface of the trench 500. The sidewall oxide film 600 is formed by an oxidation process using dry oxygen gas at 1050 ° C. to a thickness of 100 μs, thereby re-compensating the corner portion of the trench 500 after the previous step.
이와 같은 상기 트렌치(500) 모서리부의 굴곡을 완만하게 해주어 응력 집중을 줄이는데, 온도 및 상기 패드 산화막(200b)의 두께에 따라 상단 모서리부의 굴곡이 달라진다.This smooths the bend of the corner of the trench 500 to reduce stress concentration. The bend of the upper edge varies depending on the temperature and the thickness of the pad oxide film 200b.
이어서, 도 6에 도시된 바와 같이, 상기 트렌치(500)를 매립하도록 상기 기판(100) 전면에 필드 산화막(700), 예를 들어 HLD(high temperature low pressure dielectric) 등을 형성한다.Subsequently, as shown in FIG. 6, a field oxide film 700, for example, a high temperature low pressure dielectric (HLD) or the like, is formed on the entire surface of the substrate 100 to fill the trench 500.
그다음, 도 7에 도시된 바와 같이, 상기 필드 산화막(700)을 상기 질화막(300b)이 노출되도록 화학적 기계적 연마(CMP)하여 평탄화시킨다. 한편, 패턴 밀도(pattern density)에 따라 CMP 평탄화 공정의 연마 비율이 틀려 이를 보완해 주기 위하여 별도의 마스크(미도시)를 통해 패턴 밀도가 높은 부분을 먼저 식각하는 단계를 CMP 공정이전에 진행할 수 있다.Subsequently, as shown in FIG. 7, the field oxide film 700 is planarized by chemical mechanical polishing (CMP) to expose the nitride film 300b. On the other hand, the polishing rate of the CMP planarization process is different according to the pattern density to compensate for this, the step of etching the portion having a high pattern density first through a separate mask (not shown) may be performed before the CMP process. .
이어서, 도 8에 도시된 바와 같이, 상기 질화막(300b) 및 패드 산화막(200b)을 제거하여 상기 트렌치(500)내에 필드 산화막(700a)이 매립된 형태의 소자분리막(700a)을 형성한다.Subsequently, as shown in FIG. 8, the nitride film 300b and the pad oxide film 200b are removed to form the device isolation film 700a in which the field oxide film 700a is embedded in the trench 500.
그다음, 도 9에 도시된 바와 같이, 상기 기판(100)을 세정한다. 이때, 세정 공정에 의해 양측 모서리부가 식각된 상태이지만 모우트가 발생되지 않은 소자분리막(700b)이 형성된다.Next, as shown in FIG. 9, the substrate 100 is cleaned. At this time, the device isolation film 700b having both corners etched by the cleaning process but no moat is formed.
본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게 실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한 모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 소자분리막 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the device isolation film forming method of the semiconductor device according to the present invention has the following effects.
본 발명에 있어서는, 2중 경사를 갖는 트렌치 모서리 형태에 의해 응력 집중을 최소화할 수 있으며, 트렌치 형성후 다시 PR 패턴 폭을 넓혀 줌으로써 갭 필(gap fill) 폭이 넓어져 모우트가 발생하지 않게 된다.In the present invention, it is possible to minimize the stress concentration by the trench edge shape having a double inclination, widen the gap fill width by widening the PR pattern width after the trench is formed so that no moat occurs. .
따라서, 응력 집중 방지와 모우트 형성 방지로 인하여 험프(hump) 및 서브문턱전압(subthreshold) 등의 소자의 전기적 특성이 향상되는 효과가 있다.Therefore, the electrical characteristics of devices such as a hump and a subthreshold voltage may be improved due to the prevention of stress concentration and prevention of moat formation.
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