KR20030090390A - Apparatus for acquisition of synchronization in wireless lan system which is using orthogonal frequency division multiplexing - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a synchronization acquisition apparatus in a WLAN using orthogonal frequency division multiplexing.

2. The technical problem to be solved by the invention

The power consumption of the synchronization acquisition device can be reduced and the configuration can be simplified.

3. Summary of Solution to Invention

SUMMARY OF THE INVENTION An aspect of the present invention provides an apparatus for synchronization acquisition in a WLAN system using orthogonal frequency division multiplexing, comprising: a shift register for shifting a received signal by N bits; A first adder configured to add the value output from the shift register and the received signal and output the added signal; A plurality of delayers connected in series to sequentially delay the signals output from the first adder; A plurality of second adders for adding signals outputted from a pair of delayers symmetrically left and right among the plurality of delayers; A plurality of multipliers for performing multiplication of the signal output from the second adder and the respective pattern data; And a plurality of third adders for summing signals output from the plurality of multipliers.

4. Important uses of the invention

It is used for synchronization acquisition of WLAN using orthogonal frequency division multiplexing.

Description

Asynchronous Acquisition System for Wireless LAN System Using Orthogonal Frequency Division Multiplexing {APPARATUS FOR ACQUISITION OF SYNCHRONIZATION IN WIRELESS LAN SYSTEM WHICH IS USING ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING}

The present invention relates to a wireless LAN system using orthogonal frequency division multiplexing, and more particularly, to an apparatus for synchronization acquisition.

1 illustrates a schematic transmission / reception block in a WLAN system using an orthogonal frequency division multiplexing scheme.

2 shows a conventional synchronization acquisition device.

In general, a transmission / reception block of a WLAN system using an Orthogonal Frequency Division Multiplexing (OFDM) scheme has a configuration as shown in FIG. 1.

1, FEC (11: Forward Error Correction) of the transmitter 10 is for correcting an error on a channel, and a mapper 12 is for mapping a symbol corresponding to various modulation schemes such as BPSK or QPSK. In addition, IFFT (13: Inverse Fast Fourier Transform) converts a signal on a frequency domain into a signal on a time domain to perform multicarrier modulation, and a GI Guard Interval mitigates interference with the signal. It inserts an interval for it.

The synchronization acquisition device 23 of the reception unit 20 is for acquiring synchronization of the received signal, the GI removal unit 22 performs an operation of removing the above-described interval, and the FFT (Fast Fourier Transform) is a time domain. The signal of the phase is converted into a signal of the frequency domain.

FIG. 2 schematically shows the synchronization acquisition device 23 of the receiver 20, where synchronization refers to frame synchronization, and a matched filter is generally used to obtain this.

As shown in FIG. 2, the conventional synchronization acquisition apparatus includes M delays 211, M multipliers 212, 213, 214, and 215, M-1 to obtain frame synchronization of M repeated symbols. Adders 216, 217, and 218 are used.

Therefore, since a large number of delay units 211, multipliers 212, 213, 214, 215, and adders 216, 217, 218 must be used for the synchronization acquisition device, manufacturing cost increases, and the calculation amount increases. There is a problem that power consumption increases.

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a synchronization acquisition apparatus capable of inexpensive manufacturing cost, reducing calculation amount, and reducing power consumption in a WLAN system using orthogonal frequency division multiplexing. have.

1 illustrates a schematic transmission / reception block in a WLAN system using an orthogonal frequency division multiplexing scheme.

2 shows a conventional synchronization acquisition device.

3 shows a synchronization acquisition apparatus according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

311, 312, 313, 314, 315, 316, 317: first to seventh delay

320: first adder 321, 322, 323: second adder

324, 325, 326: third adder 300: N-bit shift register

331, 332, 333, 334: first to fourth multipliers

According to an aspect of the present invention, there is provided an apparatus for synchronization acquisition in a WLAN system using orthogonal frequency division multiplexing, comprising: a shift register for shifting a received signal by N bits; A first adder configured to add the value output from the shift register and the received signal and output the added signal; A plurality of delayers connected in series to sequentially delay the signals output from the first adder; A plurality of second adders for adding signals outputted from a pair of delayers symmetrically left and right among the plurality of delayers; A plurality of multipliers for performing multiplication of the signal output from the second adder and the respective pattern data; And a plurality of third adders for summing signals output from the plurality of multipliers.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 shows a synchronization acquisition apparatus according to an embodiment of the present invention.

In the synchronization acquisition apparatus according to the present invention, synchronization is obtained by using a left-right symmetrical point of 7-bit data present in the preamble data in one frame of data.

In general, a data frame transmitted in a WLAN system of orthogonal frequency division multiplexing has a preamble area for synchronization acquisition. In this case, 16 bits are allocated to the preamble area, and the data examples of the reserved bits are shown in the following table.

turn data I Q One 0.0460 + 0.0460i 2 -0.1324 + 0.0023i 3 -0.0135-0.0785i 4 0.1428-0.0127i 5 0.0920-0.0000i 6 0.1428-0.0127i 7 -0.0135-0.0785i 8 -0.1324 + 0.0023i 9 0.0460 + 0.0460i 10 0.0023-0.1324i 11 -0.0785-0.0135i 12 -0.0127 + 0.1428i 13 0.0000 + 0.0920i 14 -0.0127 + 0.1428i 15 -0.0785-0.0135i 16 0.0023-0.1324i

The input data has values of I and Q, and the Q value is received with an 8-bit delay compared to I. Accordingly, in the present invention, as shown in FIG. 3, the value of I and Q is matched by delaying the Q value by 8 taps using the N-bit shift register 300. Therefore, the signal output from the first adder 320 is output as shown in Table 2 below.

turn data I Q One 0.0460 + 0.0460i 2 -0.1324-0.1324i 3 -0.0135-0.0135i 4 0.1428 + 0.1428i 5 0.0920 + 0.0920i 6 0.1428 + 0.1428i 7 -0.0135-0.0135i 8 -0.1324-0.1324i 9 0.0460 + 0.0460i 10 0.0023 + 0.023i 11 -0.0785-0.0785i 12 -0.0127-0.0127i 13 0.0000 + 0.0000i 14 -0.0127-0.0127i 15 -0.0785-0.0785i 16 0.0023 + 0.0023i

In this case, it can be seen that seven data are symmetrical from side to side with respect to the fifth bit. In addition, it can be seen that the data value of these 7 bit sections is larger than the data values of other sections, and thus retains most of the preamble data. In the present invention, a synchronization acquisition device is implemented using the characteristics of the preamble data.

The Q-delayed 8-tap delayed signals are added to each of the delayers 311, 312, 313, 314, 315, 316, and 317 connected in series by the first adder 320.

The signals output from the respective delayers 311, 312, 313, 314, 315, 316, and 317 are input to the second adders 321, 322, and 323. The sixth data is the same, the third and seventh values are the same, and the second and eighth data values are the same.

That is, the first adder 321 of the second adder adds the second and eighth data values, the second adder 322 adds the third and seventh data values, and the third adder ( 323 adds the fourth and sixth data values and outputs them.

Then, the multipliers 331, 332, 333, and 334 multiply the values output from the second adders 321, 322, and 323 with the respective pattern data stored in the memory. Meanwhile, the fourth multiplier 334 multiplies the fifth bit data directly output from the delay unit 314 by the pattern data and outputs the multiplied data.

The signals output from the multipliers 331, 332, 333, and 334 are added by the third adders 324, 325, and 326, and the synchronization detector detects the final synchronization. That is, if the sum of the values added by the third adders 324, 325, and 326 is equal to or greater than a predetermined value, it is determined that the synchronization is correct, otherwise the synchronization is determined to be incorrect.

Meanwhile, in the above-described embodiment, seven bits are examined, but more than that are possible. When checking bits when data is symmetric with an even number, the multiplier 334 which receives a signal output from the delay unit 314 directly, such as the fourth multiplier 334, is not necessary.

The present invention reduces the number of adders, multipliers, and delays to less than half by using the preamble data characteristics of a WLAN using orthogonal frequency division multiplexing as described above. It can reduce power consumption, lower power consumption, and lower manufacturing costs.

As described above, the present invention reduces the number of adders, multipliers, and delayers by less than half by using the characteristics of preamble data whose left and right are symmetric about a predetermined bit, thereby simplifying the configuration of the synchronization acquisition device and reducing the amount of calculation. It can lower the power consumption and reduce the manufacturing cost.

Claims (3)

An apparatus for synchronization acquisition in a wireless LAN system using orthogonal frequency division multiplexing, A shift register for shifting the received signal by N bits; A first adder configured to add the value output from the shift register and the received signal and output the added signal; A plurality of delayers connected in series to sequentially delay the signals output from the first adder; A plurality of second adders for adding signals outputted from a pair of delayers symmetrically left and right among the plurality of delayers; A plurality of multipliers for performing multiplication of the signal output from the second adder and the respective pattern data; And, And a plurality of third adders for summing signals output from the plurality of multipliers. The method according to claim 1, In the case where the plurality of delay units is an odd number, the apparatus for acquiring synchronization in a WLAN system using an orthogonal frequency division multiplexing method further comprises a multiplier for multiplying the signal output from the middle delay unit with the pattern data. . The method according to claim 2, The multiple delayers are seven, the plurality of second adders are three, the plurality of multipliers are four, and the plurality of third adders are three. Synchronous acquisition device in a WLAN system.