KR20030090266A - A array substrate for LCD with TFT and method for fabricating the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a configuration of an array substrate for a liquid crystal display device including a thin film transistor and a manufacturing method thereof.

The present invention provides an array substrate forming process in which a gate electrode and a gate wiring of a double metal layer are first formed, and an active layer, a source electrode and a drain electrode are formed on the gate electrode, wherein the gate electrode and the gate wiring connected thereto are part of a substrate. Etch is formed in the etched portion.

In this case, since the gate electrode and the gate wiring are substantially parallel to the substrate, an overhang or shoulder caused by a difference in the etching rate during the wet etching of the gate electrode of the double metal layer is performed. The gate insulating film can be prevented from opening due to the step difference.

Therefore, an etching solution for etching the source and drain electrodes penetrates between the open gate insulating layers, thereby preventing the gate electrode or the gate wiring from being disconnected.

Description

A array substrate for LCD with TFT and method for fabricating the same}

The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device including a thin film transistor and a manufacturing method thereof.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light polarized by optical anisotropy may be arbitrarily modulated to express image information.

Currently, active matrix LCDs (AM-LCDs) in which thin film transistors and pixel electrodes connected to the thin film transistors are arranged in a matrix manner have attracted the most attention due to their excellent resolution and video performance.

Hereinafter, a configuration of the liquid crystal display device will be described with reference to FIG. 1.

1 is a plan view schematically illustrating a general liquid crystal display device.

As shown, the liquid crystal display device 11 includes an upper substrate 5 on which a black matrix 6, a sub color filter 7, and a common electrode 9 are formed, and a pixel electrode in the pixel region P and the pixel region. And the lower substrate 10 having the switching element T and the array wiring formed therein, and the liquid crystal 13 is filled between the upper substrate 5 and the lower substrate 10.

The lower substrate 10 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 18 and the data wiring 26 passing through the plurality of thin film transistors cross each other. Is formed.

The pixel area P is an area defined by the gate wiring 18 and the data wiring 26 intersecting with each other. The pixel electrode 34 formed in the pixel region P uses a transparent conductive metal having relatively high light transmittance, such as indium-tin-oxide (ITO).

In the liquid crystal display configured as described above, the thin film transistor T and the pixel electrode 34 connected thereto display an image by being present in a matrix.

FIG. 2 is an enlarged plan view schematically illustrating a part of the array substrate in the configuration of FIG. 1.

The elements necessary for driving the liquid crystal (13 in FIG. 1) of the above-described configuration include a gate wiring 18 for transmitting a scanning signal (gate voltage) and an image signal (data voltage) for transmitting the image signal. A thin film transistor T, which is a switching element connected to a data line 26, the gate line and the data line, and positioned at an intersection point of the gate line 18 and the data line 26, and the thin film transistor. Connected to the pixel electrode 34.

The thin film transistor T includes a gate electrode 16 connected to the gate wiring 18, a source electrode 28 and a drain electrode disposed on the gate electrode 16 and overlapping a predetermined area with an insulating layer therebetween. 30).

In this case, the source electrode 38 and the drain electrode 30 are spaced apart from each other with a semiconductor layer 20 (hereinafter referred to as an "active layer") interposed therebetween.

The active layer 20 may be generally formed using amorphous silicon (a-Si: H).

In this case, the source electrode 28 is formed to be connected to the data line 26, and the drain electrode 30 is connected to the pixel electrode 34 positioned on the pixel area P.

A portion of the pixel electrode 34 extends to an upper portion of the gate wiring 18 defining the pixel region P, and forms a storage capacitor C together with the gate wiring. The composition of can vary widely.)

In the above-described configuration, the liquid crystal panel applies a scan signal (gate voltage) to the gate electrode 16 connected to the gate wiring 18 to turn the thin film transistor on. When the image signal of which amplitude is modulated from the drain electrode in synchronization is transmitted to the pixel electrode, the liquid crystal (13 in FIG. 1) distributed on the pixel electrode is polarized and rearranged by the transmitted signal.

If the gate electrode 16 is not selected, the gate electrode 16 is turned off, and the charge accumulated in the pixel region P through the thin film transistor T is turned off and the thin film transistor T and the liquid crystal (FIG. 1). 11) the data voltage continues to be discharged.

In order to prevent such a phenomenon, the storage capacitor C is connected in parallel to the pixel electrode 46 and used. The storage capacitor C maintains the data voltage by replenishing the discharged charge. It will play a role.

The storage capacitor C uses a portion of the gate wiring 18 defining the pixel area P as a first storage electrode and the pixel electrode 34 as a second storage electrode.

In the above-described configuration, the gate electrode 16 and the gate wiring 18 of the thin film transistor T are formed of a double metal layer including aluminum (Al) to reduce signal delay.

However, the double metal layer is patterned with the same etching solution for the same time.

In this case, since the double metal layer has different etching ratios with respect to the same etching solution, the etching states are different, and generally, the lower layer formed of aluminum tends to be etched more quickly.

Accordingly, the cross-sectional shape of the patterned gate electrode causes inverse taper, that is, a step difference (over hang or shoulder).

Hereinafter, the manufacturing process of FIGS. 3A to 3G will be described in detail.

3A to 3G are cross-sectional views taken along the line III-III ′ of FIG. 2 and shown according to a conventional process sequence.

First, as shown in FIG. 3A, aluminum (Al) or an aluminum alloy is deposited on the substrate 10 to form the first metal layer 12, and molybdenum (Mo), on the upper part of the first metal layer 12, is formed. A selected one of chromium (Cr) is deposited to form the second metal layer 14.

Subsequently, a photoresist (hereinafter referred to as "PR") is applied on the second metal layer 14 to form a PR layer 15. (At this time, PR uses a positive type.)

Subsequently, a mask M composed of a transmission portion E and a reflection portion F is positioned on the PR layer 15, and the lower PR layer is irradiated with light L on the mask M. The process of exposing (15) is advanced.

In this case, the blocking part F of the mask M is positioned corresponding to a portion where the gate electrode and the gate wiring are formed.

A developing process for removing the exposed PR layer 15 is performed as shown in FIG. 3B.

As shown in FIG. 3B, the second metal layer 14 is exposed between the PR layers 15 left after the developing process.

Subsequently, the exposed second metal layer 14 and the lower first metal layer 12 are etched through the same etching solution (using a mixed acid solution of nitric acid + phosphoric acid + acetic acid), and the remaining PR layer PR is removed. Progress of the removal step in turn as shown in Figure 3c.

As shown in FIG. 3C, when the etching process is performed, the gate wiring 18 and the gate electrode 16 formed of the double metal layer are formed.

At this time, the gate wiring 18 or the gate electrode 16 has a cross-sectional area, such as a step coverage (over hang) or a shoulder (shoulder) poor step coverage (step coverage) occurs.

This is because, as mentioned above, the etching rate of the first metal layer 12, which is an aluminum layer, is faster than that of the second metal layer 14.

One selected from the group of inorganic insulating materials such as silicon oxide (SiO ₂ ) and silicon nitride (SiN _X ) is deposited on the entire surface of the substrate 10 having the gate electrode 16 and the gate wiring 18 having such a cross-sectional state. The gate insulating film 17 is formed.

At this time, the gate insulating layer 17 is a deposition failure due to the side difference between the gate wiring 18 and the gate electrode 16. In a plan view, the insulating film corresponding to the outer side of the gate wiring or the gate electrode causes cracks A to occur. do.

This crack causes a fatal defect in the gate wiring and the gate electrode during the subsequent process.

Hereinafter, the photolithography process for forming the gate wiring and the gate electrode is also described, but the active layer formed in the process, the process of patterning the source and drain electrode layers, the protective film, and the process of forming the pixel electrode are described. .

As shown in FIG. 3D, pure amorphous silicon (a-Si: H) and impurities (n-type) are doped on the entire surface of the substrate 10 on which the gate insulating layer 17 is formed. An impurity amorphous silicon layer (n + a-Si: H) is formed and patterned by a second mask process to form an active layer 20 and an ohmic contact layer on the gate insulating film 20 on the gate electrode 16. An ohmic layer 22 is formed.

Next, as illustrated in FIG. 3E, aluminum (Al), molybdenum (Mo), chromium (Cr), and the like are included on the entire surface of the substrate 10 on which the active layer 20 and the ohmic contact layer 22 are formed. A selected one of the conductive metal groups is deposited and patterned by a third mask process to form the data line 26, the source electrode 28 connected thereto, and the drain electrode 30 spaced apart from the predetermined distance.

The source and drain electrodes 28 and 30 are patterned by a wet etching process.

At this time, the etching solution penetrates through the crack A of the lower gate insulating layer 17 during the wet etching process, thereby causing a defect in etching the gate electrode 16 or the gate wiring 18. That is, referring to the planar structure of FIG. 1, an etching solution penetrates into a gate line in which the source and drain electrodes 28 and 30 do not overlap or a gate insulating layer on the gate electrode.

Next, as shown in FIG. 3F, benzocyclobutene (BCB) and acrylic resin (resin) and the like are formed on the entire surface of the substrate 10 on which the source and drain electrodes 28 and 30 are formed. The protective film 32 is formed by depositing one selected from the group of transparent organic insulating materials included therein.

Subsequently, the passivation layer 32 is patterned by a fourth mask process to form a drain contact hole 33 exposing a part of the drain electrode 30.

Next, as illustrated in FIG. 3G, one selected from a transparent conductive metal group of indium tin oxide (ITO) is deposited and patterned on the substrate 10 on which the passivation layer 32 is formed. The pixel electrode 34 extends on the pixel region P while being in contact with 30, and overlaps a part of the gate line 18 with one extended end thereof.

In the arrangement of the array substrate, the gate wiring 18 is used as the first storage electrode, the pixel electrode 34 is used as the second storage electrode, and the insulating film interposed between the two electrodes is used as the dielectric. Capacitor C is configured.

In the same manner as described above, a conventional array substrate for a liquid crystal display device can be manufactured.

However, in the conventional array substrate for a liquid crystal display device, as described above, a poor step coverage of the double metal layer constituting the gate wiring and the gate electrode causes a poor deposition of the insulating layer formed thereon, thereby etching the upper metal layer. The etching solution used penetrates into the gate wiring and the gate electrode through the insulating film, thereby causing a defect in opening them.

The present invention has been proposed for the purpose of solving the above-described problem, and proposes a method of forming a gate wiring and a gate electrode in an etched portion by etching a portion of the substrate.

In this way, the thicknesses of the gate wiring and the gate electrode appearing on the upper portion of the substrate are reduced, so that the level difference between the gate insulating films formed on these upper portions is relatively low.

Therefore, the deposition failure of the gate insulating film can be prevented, whereby a defect in which the gate wiring and the gate electrode are disconnected by the etching solution for etching the upper metal layer does not occur.

1 is a plan view schematically illustrating a general liquid crystal display device;

2 is a plan view showing a portion of a conventional array substrate for a liquid crystal display device;

3A to 3G are cross-sectional views taken along the line III-III ′ of FIG. 2 and shown according to a conventional process sequence.

4 is an enlarged plan view showing a part of an array substrate for a liquid crystal display device according to the present invention;

5A through 5G are cross-sectional views taken along the line VV ′ of FIG. 4, and according to the process sequence of the present invention.

<Description of the symbols for the main parts of the drawings>

100 substrate 116 gate electrode

118 gate electrode 120 gate insulating film

122: active layer 124: ohmic contact layer

126 data wiring 128 source electrode

130: drain electrode 132: protective film

134: pixel electrode

According to an aspect of the present invention, there is provided an array substrate for a liquid crystal display device comprising: a substrate in which a partial region is etched; A gate wiring and a gate electrode of a double metal layer formed in the etched portion; An active layer and an ohmic contact layer stacked on the gate electrode with a first insulating film interposed therebetween; A data wiring crossing the gate wiring to define a pixel region, a source electrode extending from the data wiring to an ohmic contact layer, and a drain electrode spaced apart from the data wiring; A second insulating film formed over the drain electrode and exposing a part of the drain electrode; And a pixel electrode configured to be in contact with the drain electrode and formed in the pixel region.

The first layer of the gate wiring and the gate electrode, which is the double metal layer, is aluminum (Al) or an aluminum alloy, and the second layer includes chromium (Cr), tungsten (W), and molybdenum (Mo).

The active layer is made of pure amorphous silicon (a-Si: H), and the ohmic contact layer is made of amorphous silicon (n + a-Si: H) containing impurities.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method comprising: etching a portion of the substrate; Forming a gate wiring and a gate electrode on the etched portion of the substrate using a double metal layer of a first metal layer, which is an aluminum-based metal layer, and a second metal layer, which is a conductive metal layer except for the aluminum-based metal; Forming a gate insulating film on the entire surface of the substrate on which the gate wiring and the gate electrode are formed; Stacking an active layer and an ohmic contact layer on the gate electrode on the gate insulating layer; Forming a data line crossing the gate line to define a pixel region, a source electrode extending from the data line to one side of the ohmic contact layer, and a drain electrode spaced apart from the gate line; Forming a protective film, which is a second insulating film, on an entire surface of the substrate on which the source and drain electrodes are formed, and exposing a portion of the drain electrode; And forming a transparent pixel electrode extending over a portion of the gate line through the pixel region while contacting the exposed drain electrode.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

The present invention is characterized in that the substrate is etched to a predetermined depth, and a gate wiring and a gate electrode formed of a double metal layer are formed on the etched portion.

4 is a plan view schematically illustrating a part of an array substrate for a liquid crystal display according to the present invention.

As illustrated, the gate line 118 and the data line 126 are orthogonal to define the pixel region P, and the thin film transistor, which is a switching element, is disposed at orthogonal points of the gate line 118 and the data line 126. T) is located.

The thin film transistor T is connected to the gate line 118 to receive a scan signal and receives a scan signal, and the source electrode 128 connected to the data line 126 to receive a data signal and spaced apart from the gate electrode 116. The drain electrode 130.

In addition, the thin film transistor T includes an active layer 122 formed on the gate electrode 116 and in contact with the source electrode 128 and the drain electrode 130.

The pixel region P includes a transparent pixel electrode 136 in contact with the drain electrode 128, and a portion of the pixel electrode 136 extends over the gate wiring 118.

In this case, a part of the gate wiring 118 functions as a first storage electrode, and the pixel electrode 136 functions as a second storage electrode, and is positioned between the first storage electrode and the second storage electrode. The gate insulating layer (not shown) becomes a storage capacitor C serving as a dielectric.

In the above-described configuration, the gate line 118 and the gate electrode 116 etch the substrate to a predetermined depth and form the etched portion.

In this way, the deposition failure of the gate insulating film formed thereon can be prevented by the step generated in the gate wiring 118 and the gate electrode 116.

A description with reference to FIGS. 5A to 5G is as follows.

5A to 5G are cross-sectional views illustrating a process sequence by cutting along line VV ′ of FIG. 4.

As shown in FIG. 5A, the pixel region P, the switching region S, the gate wiring region G, and the data wiring region D are defined on the substrate 100.

After the PR layer 102 is formed on the substrate 100 in which the respective regions are defined, an exposure process and a development process are performed to form a substrate corresponding to a part of the switching region S and the gate wiring region G. 100).

Subsequently, a portion of the gate wiring region G and the switching region T are etched to a predetermined depth to form an etching groove 110.

Next, as shown in FIG. 5B, the first metal layer 112 is formed by depositing aluminum (Al) or an aluminum alloy on the entire surface of the substrate 100 on which the etching grooves 110 are formed, and tungsten (W). And one selected from a conductive metal such as molybdenum (Mo) and chromium (Cr) is formed to form the second metal layer 114.

Next, as illustrated in FIG. 5C, the stacked metal layers are patterned to form a gate electrode 116 and a gate wiring 118 extending therein in the etch groove 110.

At this time, most of the height of the gate electrode 116 and the gate wiring 118 is buried inside the etching groove 110.

Accordingly, it can be seen that the side step difference between the gate wiring 118 and the gate electrode 116 is very low based on the substrate 100.

As shown in FIG. 5D, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN _X ) is formed on the entire surface of the substrate 100 on which the gate electrode 116 and the gate wiring 118 are formed. Accordingly, the gate insulating layer 120 is formed by depositing an organic insulating material such as benzocyclobutene (BCB) and acrylic resin.

Subsequently, pure amorphous silicon (a-Si: H) is deposited on the gate insulating layer 120, and subsequently doped with impurities (n-type or p-type) on the surface of the pure amorphous silicon, thereby forming a pure amorphous silicon layer and The impurity amorphous silicon layer is formed and then patterned to form the active layer 122 and the ohmic contact layer 124.

As shown in FIG. 5E, aluminum (Al), aluminum alloy (AlNd), tungsten (W), chromium (Cr), and the like are formed on the entire surface of the substrate 100 on which the active layer 122 and the ohmic contact layer 124 are formed. By depositing and patterning a selected one of a conductive metal group such as molybdenum (Mo), titanium (Ti), tantalum (Ta), switching in the data line 126 and the data line 126 in the data line area (D) The source electrode 128 extending to the region S and the drain electrode 130 spaced apart from each other are formed.

Next, as shown in 5f, benzocyclobutene (BCB) and acrylic resin (resin) and the like are placed on the entire surface of the substrate 100 on which the source electrode 128, the drain electrode 130, and the like are formed. A protective film 132 is formed by depositing one selected from the group of transparent organic insulating materials including the transparent organic insulating material.

Next, the passivation layer 132 is patterned to form a drain contact hole 134 exposing a part of the drain electrode 130.

Next, as shown in FIG. 5G, a transparent conductive metal such as indium tin oxide (ITO) and indium zinc oxide (IZO) is deposited on the entire surface of the substrate 100 on which the passivation layer 132 is formed. One side forms a pixel electrode 136 in electrical contact with the drain electrode 130 through the drain contact hole 134.

In this case, a portion of the gate wiring 118 defining the pixel region P functions as a first storage electrode, and a portion of the pixel electrode 136 extending above the gate wiring 118 is second storage. A storage capacitor C is provided in which a function of an electrode and an insulating film interposed between the two electrodes functions as a dielectric.

As described above, since the gate wiring 118 and the gate electrode 116 are formed in the etching groove 110 of the substrate 100, the side steps thereof are moved into the etching groove 110. It is a hidden shape.

Accordingly, the gate insulating layer 120 may be normally deposited on the gate electrode 116 and the gate line 118, which form a natural step coverage with the surface of the substrate 100.

As a result, since the deposition failure of the gate insulating film 120 does not occur as in the prior art, a defect in which the gate wiring 118 and the gate electrode 116 are disconnected by an etching solution that patterns the source and drain electrodes 128 and 130 is eliminated. Does not occur.

According to the above-described process, an array substrate for a liquid crystal display device according to the present invention can be manufactured.

In the present invention as described above, since the gate wiring formed from the double metal layer and the side surface of the gate electrode enter the recessed portions of the etching grooves formed in the substrate, the step difference is not so high that the gate insulating film formed on the gate electrode and the gate wiring is formed. Deposition failure does not occur.

Therefore, the problem that the etching solution for patterning the source and drain electrodes penetrates into the gate insulating film and causes the disconnection of the gate wiring and the gate electrode can be prevented, thereby improving the yield of the product.

Claims (6)

A substrate on which some regions are etched; A gate wiring and a gate electrode of a double metal layer formed in the etched portion; An active layer and an ohmic contact layer stacked on the gate electrode with a first insulating film interposed therebetween; A data wiring crossing the gate wiring to define a pixel region, a source electrode extending from the data wiring to an ohmic contact layer, and a drain electrode spaced apart from the data wiring; A second insulating film formed over the drain electrode and exposing a part of the drain electrode; A pixel electrode formed in the pixel area in contact with the drain electrode; Array substrate for a liquid crystal display device comprising a. The method of claim 1. The double layer of the gate wiring and the first electrode of the gate electrode is aluminum (Al) or aluminum alloy, the second layer is selected from the group of conductive metals including chromium (Cr), tungsten (W), molybdenum (Mo) Array substrate for liquid crystal display device. The method of claim 1, And the active layer is made of pure amorphous silicon (a-Si: H), and the ohmic contact layer is made of amorphous silicon (n + a-Si: H) containing impurities. Etching a portion of the substrate; Forming a gate wiring and a gate electrode on the etched portion of the substrate using a double metal layer of a first metal layer, which is an aluminum-based metal layer, and a second metal layer, which is a conductive metal layer except for the aluminum-based metal; Forming a gate insulating film on the entire surface of the substrate on which the gate wiring and the gate electrode are formed; Stacking an active layer and an ohmic contact layer on the gate electrode on the gate insulating layer; Forming a data line crossing the gate line to define a pixel region, a source electrode extending from the data line to one side of the ohmic contact layer, and a drain electrode spaced apart from the gate line; Forming a protective film, which is a second insulating film, on an entire surface of the substrate on which the source and drain electrodes are formed, and exposing a portion of the drain electrode; Forming a transparent pixel electrode in contact with the exposed drain electrode and extending over a portion of a gate line through the pixel region; Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 4, wherein The active layer is formed of pure amorphous silicon (a-Si: H), and the amorphous silicon containing impurities is formed of amorphous silicon (n + or p + a-Si: H) containing impurities. Manufacturing method. The method of claim 4, wherein And the second metal layer is one selected from a group of conductive metals including chromium (Mo), molybdenum (Mo), and tungsten (W).