KR20030088324A - Semiconductor memory device comprising delayed locked loop and the method of outputting data in the semiconductor memory device comprising delayed locked loop - Google Patents

Abstract

Disclosed are a semiconductor memory device having a delayed synchronization loop and a method of outputting data in the semiconductor memory device. In accordance with another aspect of the present invention, a semiconductor memory device includes: a delay synchronization loop configured to receive a predetermined external clock and generate an internal clock synchronized with the external clock; A buffer for receiving the internal clock and outputting a data clock delaying the internal clock by a first time; An enable signal generator for receiving the internal clock and generating an enable signal for delaying the internal clock by a second time in response to a data read command; And a data output buffer for outputting data corresponding to the data read command in response to the enable signal and the data clock, wherein the second time is shorter than the first time. According to the present invention, the data output enable signal for enabling the data output is activated before the data clock signal for synchronizing the data output buffer, thereby eliminating errors in the output signal of the memory device even in a system requiring a high frequency. Has the effect of outputting

Description

Semiconductor memory device comprising delayed locked loop and the method of outputting data in the semiconductor memory device comprising delayed locked loop

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a method of outputting data including controlling a latency signal in consideration of a signal delay in a semiconductor memory device having a delay synchronization loop, and a semiconductor memory device accordingly. .

A semiconductor memory device having a delayed locked loop (DLL) generates an internal clock synchronized with an external clock, and outputs predetermined data in synchronization with a data clock synchronized with an external clock in response to a data read command. .

In general, a latency signal outputs a signal that enables a data output when data is read, thereby activating the output unit. When a data read command is received, data must be output after a clock number corresponding to a predetermined CAS latency (CL), so the latency signal must be generated before the rising edge of the data clock.

1 is a diagram illustrating a generation path of a conventional latency signal. Referring to FIG. 1, the delay synchronization loop 10 receives a predetermined external clock EXT_CLK and outputs an internal clock INT_CLK synchronized with the external clock EXT_CLK. The internal clock INT_CLK is input to the latency generator 12 via the predetermined buffer 11. The internal clock INT_CLK also serves as a data clock signal.

The latency generator 12 outputs a latency signal LATENCY in response to the read command signal READ_INF. The latency signal LATENCY is input to the enable generation circuit 14 via a predetermined buffer 13. The enable signal generation circuit 14 generates an enable signal EN for enabling the data output buffer 15 in response to the latency signal LATENCY. In FIG. 1, there is a line delay and a repeater delay for the latency signal LATENCY to reach the enable signal generation circuit 14.

2 is a diagram illustrating a circuit diagram of the latency generator 12. The latency generator 12 of FIG. 2 is composed of a plurality of flip-flops 20, 21, 22, 23 and a multiplexer 24. The latency is generated in synchronization with the internal clock signal INT_CLK in response to the read command signal READ_INF.

Referring to FIG. 2, the semiconductor memory device must support various CAS latencies according to an external setting, and thus a multiplexing delay occurs due to multiplexing to select a signal according to various CAS latencies. .

These line delays, multiplexing delays, and repeater delays are not a problem when the operating frequency of the memory device is low. However, the higher the frequency, the greater the problem.

3 is a timing diagram of signals according to a conventional semiconductor memory device. Referring to FIG. 3, when the frequency of the data clock is increased, an enable signal is input after the rising edge of the data clock (td> tcc), thereby reducing the size of the output of the data or generating an error that does not occur. There is this.

Accordingly, an aspect of the present invention is to provide a semiconductor memory device that generates a latency signal and an enable signal in consideration of delays received by the latency signal.

Another object of the present invention is to provide a data output method for generating data by generating a latency signal and an enable signal in consideration of delays received by the latency signal.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a diagram illustrating a generation path of a conventional latency signal.

2 is a diagram illustrating a circuit diagram of a latency generator.

3 is a timing diagram illustrating timing of signals according to a conventional semiconductor memory device.

4 is a first embodiment showing a semiconductor memory device according to the present invention.

5 is a second embodiment of the semiconductor memory device according to the present invention.

6 is a third embodiment of the semiconductor memory device according to the present invention.

7 is a timing diagram of each signal in the semiconductor memory device according to the present invention.

One aspect of the present invention for achieving the above technical problem relates to a semiconductor memory device. In accordance with another aspect of the present invention, a semiconductor memory device includes: a delay synchronization loop configured to receive a predetermined external clock and generate an internal clock synchronized with the external clock; A buffer for receiving the internal clock and outputting a data clock delaying the internal clock by a first time; An enable signal generator for receiving the internal clock and generating an enable signal for delaying the internal clock by a second time in response to a data read command; And a data output buffer for outputting data corresponding to the data read command in response to the enable signal and the data clock, wherein the second time is shorter than the first time.

Preferably, the delay synchronization loop further comprises an additional compensation delay unit to quickly reach the output buffer a signal enabling the output buffer.

Also preferably, the enable signal generation unit may include a latency generation circuit configured to output a latency signal in synchronization with the internal clock in response to a data read command; And an enable signal generation circuit for generating a signal for enabling the output buffer in response to the latency signal.

Another aspect of the present invention for achieving the above technical problem relates to a semiconductor memory device. In accordance with another aspect of the present invention, a semiconductor memory device includes: a first delay synchronizer loop configured to receive a predetermined external clock and output a first internal clock synchronized with the external clock; A second delay lock loop for receiving the external clock and outputting a second internal clock synchronized with the external clock; A data output enable signal generation circuit for receiving the second internal clock and outputting a data output enable signal; And an output buffer configured to output data in synchronization with the first internal clock signal in response to the data output enable signal, wherein the second delay lock loop compensates for the delay time of the data output enable signal. And a compensation delay unit in the first delay loop.

Preferably, the data output enable signal generation circuit includes a latency generation circuit configured to output a latency signal in synchronization with the latency clock in response to a data read command; And an enable signal generation circuit configured to receive the latency signal and generate a signal for enabling a data output.

Also preferably, the compensation delayer may compensate for a delay amount generated in the data output enable generation circuit.

Another aspect of the present invention for achieving the above technical problem relates to a method of outputting data in a semiconductor memory device. According to another aspect of the present invention, there is provided a method of outputting data, the method including: receiving an external clock and generating an internal clock synchronized with the external clock; Generating a data clock signal having received the internal clock and delaying the internal clock by a first time; Generating a data output enable signal for receiving the internal clock and data read command and delaying the internal clock for a second time; And outputting predetermined data in synchronization with the data clock signal in response to the data output enable signal, wherein the data output enable signal is activated before the data clock signal.

Preferably, the generating of the data output enable signal comprises: generating a predetermined latency signal in response to the data read command and the internal clock signal; And generating the data output enable signal in response to the latency signal.

Another aspect of the present invention for achieving the above technical problem relates to a method of outputting data in a semiconductor memory device. A method of outputting data in a semiconductor memory device according to the present invention includes: receiving a predetermined external clock and generating a first clock synchronized with the external clock; Receiving the first clock and delaying the first clock to generate a data clock signal; Receiving the first clock and delaying a second time to generate a second clock; Generating a data output enable signal for enabling a data output terminal in response to the second clock and data read command; And outputting predetermined data in synchronization with the data clock signal at the data output terminal in response to the data output enable signal, wherein the data output enable signal is earlier to the data output terminal than the data clock signal. Generate a second clock to reach.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

4 is a first embodiment showing a semiconductor memory device according to the present invention. Referring to FIG. 4, the semiconductor memory device includes a delay synchronization loop 410, a buffer 420, an enable signal generator 430, a plurality of delay circuits 46 and 47, and a data output buffer 440. do.

The delay synchronization loop 410 includes a variable delay line 40, a phase detector 41, a low pass filter 42, and a compensation delay 43. The enable signal generator 430 includes a latency generator circuit 44 and an enable signal generator circuit 45.

The operation of the present invention will be described with reference to FIG. 4. The delay synchronization loop 410 receives the external clock EXT_CLK, generates an internal clock INT_CLK synchronized with the external clock EXT_CLK, and outputs the internal clock INT_CLK to the buffer 420. The buffer 420 receives the internal clock INT_CLK and outputs the internal clock INT_CLK after a predetermined time delay. The output signal of the buffer 420 is input to the data output buffer 440 as the data clock signal CLKDQ_D through a predetermined delay 46.

The delay circuit 47 receives the output signal of the buffer 420 and delays the predetermined time to output the latency clock signal CLKDQ_L generated to the enable signal generator 430.

The enable signal generator 430 generates a latency signal LATENCY in response to the read command signal READ_INF and the latency clock signal CLKDQ_L, and the enable signal generator 45 receives the latency signal LATENCY. And outputs a signal EN to enable the data output buffer 440. The data output buffer 440 outputs predetermined data in synchronization with the data clock signal CLKDQ_D in response to the data output enable signal EN.

Among the data clock signal CLKDQ_D and the data output enable signal EN arriving at the data output buffer 440, the data output enable signal EN is activated earlier than the data clock signal CLKDQ_D. It's the key.

5 is a second embodiment of the semiconductor memory device according to the present invention. The semiconductor memory device illustrated in FIG. 5 includes a delay synchronization loop 510, a buffer 520, an enable signal generator 530, and a data output buffer 540.

The delayed synchronization loop 510 includes a variable delay line 50, a first phase detector 51, a second phase detector 52, a low pass filter 53, a first compensation delay 54 and a second compensation delay. Group 55 is provided. The enable signal generator 530 includes a latency generation circuit 59 and an enable generation circuit 58.

The operation of the present invention will be described with reference to FIG. 5. In FIG. 5, the data clock signal CLKDQ_D receives the external clock EXT_CLK and is output as a predetermined clock signal synchronized with the external clock EXT_CLK through the first compensation delay 54 and the first phase detector 51. . The latency clock signal CLKDQ_L is output as a predetermined clock signal synchronized with the external clock EXT_CLK through the second compensation delay 55 and the second phase detector 52.

The second compensation delay unit 55 is provided to compensate for the delay amount generated by the enable signal generator 530. As a result, the data output enable signal EN is activated earlier than the data clock CLKDQ_D. Will be.

6 is a third embodiment of the semiconductor memory device according to the present invention. Referring to FIG. 6, the semiconductor memory device includes a first delayed synchronizer loop 61, a second delayed delay loop 62, an enable signal generator 63, and a data output buffer 67.

Referring to Figure 6 will be described the operation of the present invention. The first delay synchronizer loop 61 receives an external clock EXT_CLK to generate an internal clock INT_CLK1 synchronized with the external clock EXT_CLK, and the internal clock INT_CLK1 passes through a predetermined delay 68 to receive a data clock signal. (CLKDQ_D).

The second delay synchronizer loop 62 receives the external clock EXT_CLK to generate an internal clock INT_CLK2 synchronized with the external clock EXT_CLK, and becomes a latency clock signal CLKDQ_L through a predetermined delay 64. .

The enable signal generator 63 receives the latency clock signal CLKDQ_L and generates a data output enable signal EN. In the present invention, in order to enable the data output enable signal EN to be activated before the data clock signal CLKDQ_D, the delay amount of the compensation delay unit (not shown) in the delay synchronization loops 61 and 62 is compensated.

7 is a timing diagram of each signal in the semiconductor memory device according to the present invention. As shown in FIG. 7, according to the present invention, the latency clock is compensated by tcomp, so that the enable signal is activated before the rising edge of the data clock, thereby allowing a margin of tmargin.

Finally, a method of outputting data from a semiconductor memory device will be described with reference to the semiconductor memory device of FIGS. 4 to 5. In the method of outputting data in the semiconductor memory device, an external clock EXT_CLK is received and an internal clock INT_CLK synchronized with the external clock EXT_CLK is generated. This step is performed in delayed synchronization loops 410 and 510.

Next, a step of receiving the internal clock INT_CLK and generating the data clock signal CLKDQ_D having delayed the internal clock INT_CLK by a first time is performed. The data clock signal CLKDQ_D is generated by the internal clock INT_CLK passing through the buffers 420 and 520 and the predetermined delays 46 and 57.

In addition, a step of receiving the internal clock INT_CLK and the data read command READ_INF and generating a data output enable signal EN with a delay of the internal clock INT_CLK for a second time is performed. The step is performed by the predetermined delays 47 and 60 and the enable signal generators 430 and 530. Finally, in response to the data output enable signal EN, a step of outputting predetermined data in synchronization with the data clock signal CLKDQ_D is provided.

In particular, the method of the present invention is characterized in that the data output enable signal EN is activated before the data clock signal CLKDQ_D.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the semiconductor memory device and the data output method according to the present invention enable a data output enable signal for enabling data output before data clock signal for synchronizing the data output buffer, thereby requiring a high frequency. In addition, there is an effect to eliminate the error of the output signal of the memory device to output the correct data.

Claims (10)

In a semiconductor memory device, A delay synchronization loop for receiving a predetermined external clock and generating an internal clock synchronized with the external clock; A buffer for receiving the internal clock and outputting a data clock delaying the internal clock by a first time; An enable signal generator for receiving the internal clock and generating an enable signal for delaying the internal clock by a second time in response to a data read command; And And a data output buffer for outputting data corresponding to the data read command in response to the enable signal and the data clock. And the second time is shorter than the first time. The method of claim 1, wherein the delay synchronization loop And an additional compensation delay unit for quickly reaching the output buffer to enable the signal to enable the output buffer. The method of claim 1, wherein the semiconductor memory device And the enable signal is activated before the data clock. The method of claim 1, wherein the enable signal generator A latency generation circuit configured to output a latency signal in synchronization with the internal clock in response to a data read command; And, And an enable signal generation circuit for generating a signal for enabling an output buffer in response to the latency signal. In a semiconductor memory device having a delayed synchronization loop, A first delay lock loop for receiving a predetermined external clock and outputting a first internal clock synchronized with the external clock; A second delay lock loop for receiving the external clock and outputting a second internal clock synchronized with the external clock; A data output enable signal generation circuit for receiving the second internal clock and outputting a data output enable signal; And, An output buffer configured to output data in synchronization with the first internal clock signal in response to the data output enable signal; And the second delay lock loop further includes a compensation delay block in the first delay lock loop to compensate for the delay time of the data output enable signal. 6. The data output enable signal generating circuit of claim 5, wherein A latency generation circuit configured to output a latency signal in synchronization with the latency clock in response to a data read command; And, And an enable signal generation circuit configured to receive the latency signal and generate a signal for enabling a data output. The method of claim 5, wherein the compensation delay And compensating for a delay amount generated in the data output enable generation circuit. A method of outputting data in a semiconductor memory device having a delayed synchronization loop, Receiving an external clock and generating an internal clock synchronized with the external clock; Generating a data clock signal having received the internal clock and delaying the internal clock by a first time; Generating a data output enable signal for receiving the internal clock and data read command and delaying the internal clock for a second time; And, Outputting predetermined data in synchronization with the data clock signal in response to the data output enable signal; And the data output enable signal is activated before the data clock signal. The method of claim 8, wherein the data output enable signal generating step Generating a predetermined latency signal in response to the data read command and the internal clock signal; And, And generating the data output enable signal in response to the latency signal. In the method for outputting data in a semiconductor memory device having a delay synchronization loop, Receiving a predetermined external clock and generating a first clock synchronized with the external clock; Receiving the first clock and delaying the first clock to generate a data clock signal; Receiving the first clock and delaying a second time to generate a second clock; Generating a data output enable signal for enabling a data output terminal in response to the second clock and data read command; And, Outputting predetermined data in synchronization with the data clock signal at the data output terminal in response to the data output enable signal; And generating a second clock such that the data output enable signal is activated before the data clock signal.