KR20030071300A - Manufacturing method for divice junction Josephson superconductor - Google Patents
Manufacturing method for divice junction Josephson superconductor Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000002887 superconductor Substances 0.000 title claims description 14
- 239000010408 film Substances 0.000 claims abstract description 79
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 31
- 239000010703 silicon Substances 0.000 claims abstract description 31
- 239000010409 thin film Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000059 patterning Methods 0.000 claims abstract description 7
- 150000002500 ions Chemical class 0.000 claims abstract description 6
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 238000009832 plasma treatment Methods 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 10
- 239000000463 material Substances 0.000 description 10
- 230000001681 protective effect Effects 0.000 description 5
- 229910021521 yttrium barium copper oxide Inorganic materials 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 229910052761 rare earth metal Inorganic materials 0.000 description 2
- 150000002910 rare earth metals Chemical group 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 229910001233 yttria-stabilized zirconia Inorganic materials 0.000 description 2
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005292 diamagnetic effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0912—Manufacture or treatment of Josephson-effect devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0268—Manufacture or treatment of devices comprising copper oxide
- H10N60/0296—Processes for depositing or forming copper oxide superconductor layers
- H10N60/0576—Processes for depositing or forming copper oxide superconductor layers characterised by the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0268—Manufacture or treatment of devices comprising copper oxide
- H10N60/0661—Processes performed after copper oxide formation, e.g. patterning
- H10N60/0688—Etching
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/10—Junction-based devices
- H10N60/12—Josephson-effect devices
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Abstract
본 발명은 초전도 조셉슨 접합 소자 제조 방법에 관한 것이다. 이와 같은 본 발명에 따른 초전도 조셉슨 접합 소자 제조는, 기판 위에 초전도 박막과 실리콘 막을 순차적으로 형성하고 패터닝하는 단계, 상기 실리콘 막의 일부분에 산화막을 형성하는 단계, 상기 산화막을 에칭하고, 상기 실리콘 막에 이온을 주입하여 초전도 박막의 계면을 형성하는 단계로 이루어진다.The present invention relates to a method for manufacturing a superconducting Josephson junction element. In the manufacturing of the superconducting Josephson junction device according to the present invention, the step of sequentially forming and patterning a superconducting thin film and a silicon film on a substrate, forming an oxide film on a portion of the silicon film, etching the oxide film, ions in the silicon film Forming an interface of the superconducting thin film;
Description
본 발명은 초전도 조셉슨 접합 소자 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a superconducting Josephson junction element.
일반적으로 초전도체는 완전도체성질, 완전반자성성질 그리고 조셉슨 현상을 가진 물질로서, 수십 년 전부터 주목을 받아왔으나 초전도현상이 시작되는 임계온도가 4k 정도의 극저온이어서 산업화의 길은 요원한 것으로 인식되었다.In general, superconductors are materials with perfect conductor properties, fully diamagnetic properties, and Josephson phenomena. They have been attracting attention for decades, but the critical temperature of superconductivity starts at about 4k.
그러나, 1986년 산화물 고온초전도체가 발견된 이후, 값싼 액체질소를 이용하여 충분히 임계온도 이하로 냉각시킬 수 있게 되면서 초전도 현상을 이용한 응용 연구가 산업화에 적용될 수 있을 것이라는 예상이 나오면서, 고온초전도체를 이용한 다양한 소자 제작이 활발히 전개되었다.However, after the discovery of oxide high temperature superconductors in 1986, it was possible to cool them below the critical temperature by using cheap liquid nitrogen, and it was expected that applied research using superconductivity could be applied to industrialization. Device fabrication has been actively developed.
또한, 고온초전도체는 간섭길이(coherence length)가 짧고, 이방성이 커서 조셉슨 접합을 제작하는 것이 대단히 어렵다. 따라서, 저온초전도체에서 사용되던 부도체 절연막을 이용한 샌드위치 접합의 제작에는 아무도 성공하지 못하고 있다.In addition, the high temperature superconductor has a short coherence length and anisotropy, making it very difficult to fabricate a Josephson junction. Therefore, no one has succeeded in producing a sandwich junction using a non-conductor insulating film used in a low temperature superconductor.
샌드위치 접합이 성공하기만 한다면 제작의 간편성, 재현성 측면에 우수한 결과를 기대할 수 있지만, 현재 각국의 연구진들은 샌드위치 접합대신 GB(Grain Boundary)접합이나, 에지 지오메트리(edge geometry)를 이용한 SNS(초전도-상전도-초전도), S-artificial interface-S, S-resonant tunneling barrier-S 접합 등 다양한 시도를 하고 있다.If the sandwich joint is successful, it can be expected to have excellent results in terms of simplicity and reproducibility.However, researchers in other countries have replaced the sandwich joint with GB (Grain Boundary) or SNS (edge conductivity) using edge geometry. Doo-superconductor), S-artificial interface-S, S-resonant tunneling barrier-S junctions.
이하 첨부된 도면을 참조하여 종래 기술에 따른 조셉슨 접합 소자 제조 방법을 설명하기로 한다.Hereinafter, a Josephson junction device manufacturing method according to the related art will be described with reference to the accompanying drawings.
도 1a 내지 도 1f는 종래 기술에 따른 조셉슨 접합 소자 제조 공정 단계를순차적으로 나타낸 도면이다.1A to 1F are sequential diagrams illustrating the steps of manufacturing a Josephson junction device according to the prior art.
먼저 도 1a와 같이 기판(1) 위에 초전도 박막(2)을 형성하고 상기 초전도 박막(2) 위에 절연막(3)을 형성한다.First, as shown in FIG. 1A, the superconducting thin film 2 is formed on the substrate 1, and the insulating film 3 is formed on the superconducting thin film 2.
그리고, 상기 초전도 박막(2)과 절연막(3)의 일부분을 이온 밀링(ion milling)을 이용하여 경사지게 에칭하여 제거한다. (도 1b)Then, the superconducting thin film 2 and a part of the insulating film 3 are removed by being etched obliquely using ion milling. (FIG. 1B)
상기 도 1b 와 같이 에칭한 후, SrTiO3나 CuRuO3와 같이 초전도 물질위의 보호막(6), 계면막(4), 절연막(3)의 일부분이 자라고, 초전도성이 아닌 물질을 증착하여 계면막(4)을 형성한다. (도 1c)After etching as shown in FIG 1b, growing a portion of the superconducting material above the protection film 6, the surface layer 4, the insulating film 3, such as SrTiO 3 or CuRuO 3, by depositing a material other than a superconducting interface film ( 4) form. (FIG. 1C)
그 다음 상기 계면막(4) 위에 YBa2Cu3O7과 같은 초전도 물질(5)을 형성한 다음 패터닝 한다. (도 1d)Next, a superconducting material 5 such as YBa 2 Cu 3 O 7 is formed on the interface film 4 and then patterned. (FIG. 1D)
상기와 같이 패터닝 한 후, 보호막(6)을 형성한 후, 상기 초전도 박막(2)과 초전도 물질(5)의 일부분을 제거한 후 컨택 홀(contact hole)을 형성한다. (도 1e)After patterning as described above, the protective film 6 is formed, and then a portion of the superconducting thin film 2 and the superconducting material 5 is removed to form a contact hole. (FIG. 1E)
그리고, 상기 컨택 홀 위에 금과 같은 물질을 형성하여 패드(7)를 제작한다. (도 1f)The pad 7 is manufactured by forming a material such as gold on the contact hole. (FIG. 1F)
이와 같은, 조셉슨 접합 소자는 계면막이 수 Å으로 매우 얇고, 복잡한 구조를 갖는 물질이기 때문에 초전도체를 형성하기 매우 어려우며, 초전도체 전체를 균일하게 형성하기 어렵기 때문에 재현성 있고, 신뢰성 있는 디바이스 제작이 거의 불가능하다.Such a Josephson junction element is very difficult to form a superconductor because the interface film is very thin and has a complicated structure, and it is difficult to form the entire superconductor uniformly, making it almost impossible to manufacture a reproducible and reliable device. .
그리고, 경사지게 에칭한 초전도체의 표면특성이 아주 좋아야 하는데, 에칭시 표면이 손상을 입어 표면특성이 저하되는 문제점이 있다.In addition, the surface characteristics of the superconductor etched obliquely should be very good, but there is a problem in that the surface is damaged during etching, thereby lowering the surface characteristics.
따라서, 본 발명의 목적은 이상에서 언급한 종래 기술의 문제점을 감안하여 안출한 것으로서, 아주 얇은 계면막을 형성하여 재현성 있고, 신뢰성 있는 초전도 조셉슨 접합 소자 제조 방법을 제공하기 위한 것이다.Accordingly, an object of the present invention is to provide a reproducible and reliable superconducting Josephson junction element manufacturing method by forming a very thin interface film in view of the problems of the prior art mentioned above.
도 1a 내지 도 1f는 일반적인 초전도 조셉슨 접합 소자 제조 공정을 순차적으로 보여주는 도면1A to 1F sequentially illustrate a general superconducting Josephson junction device manufacturing process
도 2a 내지 도 2h는 본 발명에 따른 초전도 조셉슨 접합 소자 제조 공정을 순차적으로 보여주는 단면도이고, 도 2b' 내지 도 2h'는 도 2b 내지 도 2h에서 보여주는 도면의 평면도2A through 2H are cross-sectional views sequentially illustrating a manufacturing process of a superconducting Josephson junction device according to the present invention, and FIGS. 2B 'through 2H' are plan views of the drawings shown in FIGS. 2B through 2H.
도 3a 내지 도 3h는 본 발명에 따른 초전도 조셉슨 접합 소자 제조 공정을 순차적으로 보여주는 단면도이고, 도 3b' 내지 도 3h'는 도 3b 내지 도 3h에서 보여주는 도면의 평면도3A through 3H are cross-sectional views sequentially illustrating a manufacturing process of a superconducting Josephson junction element according to the present invention, and FIGS. 3B 'through 3H' are plan views of the drawings shown in FIGS. 3B through 3H.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10 : 기판 11 : 초전도 박막10 substrate 11 superconducting thin film
12 : 실리콘 막 13 : 산화막12 silicon film 13 oxide film
14 : 비정질층 15 : 보호막14 amorphous layer 15 protective film
16 : 콘택 홀 17 : 골드 패드16: contact hole 17: gold pad
이상과 같은 목적을 달성하기 위한 본 발명의 일 특징에 따르면, 기판 위에 초전도 박막과 실리콘 막을 순차적으로 형성하고 패터닝하는 단계, 상기 실리콘 막의 일부분에 산화막을 형성하는 단계, 상기 산화막을 에칭하고, 상기 실리콘 막에 이온을 주입하여 초전도 박막의 계면을 형성하는 단계로 이루어진다.According to an aspect of the present invention for achieving the above object, the step of sequentially forming and patterning a superconducting thin film and a silicon film on a substrate, forming an oxide film on a portion of the silicon film, etching the oxide film, Injecting ions into the membrane to form an interface of the superconducting thin film.
바람직하게, 상기 실리콘 막은 비정질 실리콘이나 다결정 실리콘 중 하나이고, 상기 산화막은 열산화 공정이나 산소 플라즈마 처리로 산화막을 형성한다.Preferably, the silicon film is either amorphous silicon or polycrystalline silicon, and the oxide film forms an oxide film by a thermal oxidation process or an oxygen plasma treatment.
그리고, 상기 실리콘 막에 이온이 주입되면, 초전도체 부분은 결정구조가 깨져서 비정질 상태가 되어 초전도 성질을 잃게 되어 초전도막이 패터닝 된다.In addition, when ions are implanted into the silicon film, the superconductor portion is broken in a crystal structure to become an amorphous state and loses superconducting properties, thereby patterning the superconducting film.
이상과 같은 다른 목적을 달성하기 위한 본 발명의 다른 특징에 따르면, 기판 위에 초전도 박막과 실리콘 막을 순차적으로 형성하고 패터닝하는 단계, 상기 실리콘 막의 일부분에 산화막을 형성하는 단계, 상기 산화막을 에칭하고, 상기 실리콘 막을 식각하여 초전도 박막의 계면을 형성하는 단계로 이루어진다.According to another feature of the present invention for achieving the above object, the step of sequentially forming and patterning a superconducting thin film and a silicon film on a substrate, forming an oxide film on a portion of the silicon film, etching the oxide film, Etching the silicon film to form an interface of the superconducting thin film.
이하 본 발명의 바람직한 일 실시 예에 따른 구성 및 작용을 첨부된 도면을 참조하여 설명한다.Hereinafter, a configuration and an operation according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.
먼저, 본 발명의 개념은 다양한 초전도 박막에 응용될 수 있지만 최근 가장 주목받고 있는 YBCO 박막 초전도체와 STO 기판을 이용한 것에 대해서 기술한다.First, the concept of the present invention can be applied to a variety of superconducting thin film, but describes the use of the YBCO thin film superconductor and STO substrate which is attracting the most attention recently.
통상 YBCO 박막이라고 기술하는 박막의 조성은 YBa2Cu3O7-x이며 x<0.1이하일 때 약 90K이하에서 초전도 특성이 나타나고, x>0.4일 경우 부도체가 된다.The composition of a thin film, which is generally described as a YBCO thin film, is YBa 2 Cu 3 O 7-x, and superconductivity is exhibited at about 90 K or less when x <0.1 or less, and an insulator when x> 0.4.
도 2a 내지 도 2h는 본 발명에 따른 초전도 조셉슨 접합 소자 제조 공정을 순차적으로 보여주는 단면도이고, 도 2b' 내지 도 2h'는 도 2b 내지 도 2h에서 보여주는 도면의 평면도이다.2A to 2H are cross-sectional views sequentially illustrating a manufacturing process of a superconducting Josephson junction device according to the present invention, and FIGS. 2B 'to 2H' are plan views of the drawings shown in FIGS. 2B to 2H.
도 2a에 도시된 바와 같이 먼저 기판(10)위에 약 200nm의 초전도 박막(11)을 PLD(Pulsed Laser Deposotion)법이나 이베포레이션(evaporation)등을 이용하여 증착 시킨다.As shown in FIG. 2A, a superconducting thin film 11 having a thickness of about 200 nm is first deposited on a substrate 10 using PLD (Pulsed Laser Deposotion) or evaporation.
여기서, 상기 초전도 박막(11)의 물질은 산소 함량에 따라 그 특성이 변하는 YBCO, RBCO(R은 rare earth 물질), BSCCO, TIBCCO, LSCO, NCCO 중 하나를 사용하며, 증착 방법은 PLD, sputtering, CVD, coevaporation, MBE 등을 이용한다.Here, the material of the superconducting thin film 11 uses one of YBCO, RBCO (R is rare earth material), BSCCO, TIBCCO, LSCO, NCCO, the properties of which change depending on the oxygen content, and the deposition method is PLD, sputtering, CVD, coevaporation, MBE and the like are used.
또한, 상기 기판(10)은 상기 초전도 박막(11)이 에피택시 성장하는 STO, SAO, NGO, MgO, YSZ, 샤파이어, 실리콘, LSAT 등을 이용한다.In addition, the substrate 10 uses STO, SAO, NGO, MgO, YSZ, sapphire, silicon, LSAT, etc. in which the superconducting thin film 11 is epitaxially grown.
그리고, 상기 초전도 박막(11)위에 비정질실리콘막이나 다결정실리콘막(12)을 형성한 다음 패터닝 한다.(도 2b)In addition, an amorphous silicon film or a polysilicon film 12 is formed on the superconducting thin film 11 and then patterned (FIG. 2B).
여기서 상기 비정질실리콘막이나 다결정실리콘막(12)의 형성은, LPCVD(Low Pressure Chemical Vapor Deposition)법이나 PECVD(Plasma Enhanced ChemicalVapor Deposition)법, 그리고 sputtering 법 등을 이용하며, 도 2b'에 나타낸 바와 같이, 조셉슨 접합이 이루어질 부분의 폭은 1μm이하가 되게 좁게하고, 패드부분은 넓게 한다. (B부분이 접합 계면이 형성되는 부분임)Here, the amorphous silicon film or the polysilicon film 12 is formed using a low pressure chemical vapor deposition (LPCVD) method, a plasma enhanced chemical vapor deposition (PECVD) method, a sputtering method, or the like, as shown in FIG. 2B '. The width of the part where Josephson junction is to be made should be narrow to be less than 1μm, and the pad part should be wide. (B part is the part where the bonding interface is formed)
그 다음 상기 실리콘막(12)의 일부분을 열산화 공정 혹은 기타 산화공정(산소플라즈마 처리 등)을 사용하여 산화막(13)을 형성한다.(도 2c)A portion of the silicon film 12 is then formed using an thermal oxidation process or other oxidation process (oxygen plasma treatment, etc.) to form the oxide film 13 (FIG. 2C).
이때, 조셉슨 접합면이 이루어질 부분(B)의 실리콘막(12)의 폭이 수 Å 내지 수십 Å이 남을 때까지 산화공정을 진행한다.At this time, the oxidation process is performed until the width of the silicon film 12 of the portion B on which the Josephson junction surface is to be formed remains.
그리고, 상기 산화 공정을 통하여 형성한 산화막(13)을 불산(HF)과 같은 에칭용액을 사용하여 제거한다.(도 2d)Then, the oxide film 13 formed through the oxidation process is removed using an etching solution such as hydrofluoric acid (HF) (FIG. 2D).
이때, 상기 불산을 사용할 경우, 초전도막(11)과 실리콘막(12)은 전혀 에칭이 되지 않고 산화막(13)만 에칭되어 제거된다.At this time, when the hydrofluoric acid is used, the superconducting film 11 and the silicon film 12 are not etched at all, and only the oxide film 13 is etched and removed.
그 다음, 상기 남아 있는 실리콘막(12)을 마스크로 하여 이온 주입 공정을 한다.(도 2e)Next, an ion implantation process is performed using the remaining silicon film 12 as a mask (FIG. 2E).
이렇게 하면, 이온이 주입되는 초전도체 부분은 결정구조가 깨어져서 비정질 상태가 되며 이로 인해 초전도의 성질을 잃게 되어 초전도막(11)이 패터닝 되게 된다.In this case, the superconductor portion into which the ions are implanted is broken in a crystal structure to become an amorphous state, which causes the superconductor film 11 to be lost, thereby causing the superconducting film 11 to be patterned.
즉, 상기와 같이 이온 주입 공정으로 B부분의 초전도 폭이 수~수십 Å이 되어 조셉슨 접합 계면이 만들어진다.That is, as described above, the width of the superconductivity of the portion B becomes several tens to several tens of kV in the ion implantation process, thereby making the Josephson junction interface.
그리고, 도 2f와 같이 보호막(15)을 형성하고, 도 2g와 같이 콘택홀(16)을 형성하고, 도 2h와 같이 골드 패드(17)를 형성한다.Then, the protective film 15 is formed as shown in FIG. 2F, the contact hole 16 is formed as shown in FIG. 2G, and the gold pad 17 is formed as shown in FIG. 2H.
도 3a 내지 도 3h는 본 발명에 따른 초전도 조셉슨 접합 소자 제조 공정을 순차적으로 보여주는 단면도이고, 도 3b' 내지 도 3h'는 도 3b 내지 도 3h에서 보여주는 도면의 평면도이다.3A through 3H are cross-sectional views sequentially illustrating a manufacturing process of a superconducting Josephson junction device according to the present invention, and FIGS. 3B 'through 3H' are plan views of the drawings shown in FIGS. 3B through 3H.
도 3a에 도시된 바와 같이 먼저 기판(20)위에 약 200nm의 초전도 박막(21)을 PLD(Pulsed Laser Deposotion)법이나 이베포레이션(evaporation)등을 이용하여 증착 시킨다.As shown in FIG. 3A, a superconducting thin film 21 having a thickness of about 200 nm is first deposited on a substrate 20 using PLD (Pulsed Laser Deposotion) or evaporation.
여기서, 상기 초전도 박막(21)의 물질은 산소 함량에 따라 그 특성이 변하는 YBCO, RBCO(R은 rare earth 물질), BSCCO, TIBCCO, LSCO, NCCO 중 하나를 사용하며, 증착 방법은 PLD, sputtering, CVD, coevaporation, MBE 등을 이용한다.Here, the material of the superconducting thin film 21 uses one of YBCO, RBCO (R is rare earth material), BSCCO, TIBCCO, LSCO, NCCO, the properties of which change depending on the oxygen content, and the deposition method is PLD, sputtering, CVD, coevaporation, MBE and the like are used.
또한, 상기 기판(20)은 상기 초전도 박막(21)이 에피택시 성장하는 STO, SAO, NGO, MgO, YSZ, 샤파이어, 실리콘, LSAT 등을 이용한다.In addition, the substrate 20 uses STO, SAO, NGO, MgO, YSZ, sapphire, silicon, LSAT, etc. in which the superconducting thin film 21 is epitaxially grown.
그리고, 상기 초전도 박막(21)위에 비정질실리콘막이나 다결정실리콘막(12)을 형성한 다음 패터닝 한다.(도 3b)In addition, an amorphous silicon film or a polysilicon film 12 is formed on the superconducting thin film 21 and then patterned (FIG. 3B).
여기서 상기 비정질실리콘막이나 다결정실리콘막(12)의 형성은, LPCVD(Low Pressure Chemical Vapor Deposition)법이나 PECVD(Plasma Enhanced Chemical Vapor Deposition)법, 그리고 sputtering 법 등을 이용하며, 도 3b'에 나타낸 바와 같이, 조셉슨 접합이 이루어질 부분의 폭은 1μm이하가 되게 좁게하고, 패드부분은 넓게 한다. (B부분이 접합 계면이 형성되는 부분임)The amorphous silicon film or the polysilicon film 12 may be formed by using a low pressure chemical vapor deposition (LPCVD) method, a plasma enhanced chemical vapor deposition (PECVD) method, a sputtering method, or the like, as shown in FIG. 3B '. Likewise, the width of the portion where the Josephson junction is to be made is narrowed to be 1 μm or less, and the pad portion is made wide. (B part is the part where the bonding interface is formed)
그 다음 상기 실리콘막(22)의 일부분을 열 산화 공정 혹은 기타 산화공정(산소플라즈마 처리 등)을 사용하여 산화막(23)을 형성한다.(도 2c)A portion of the silicon film 22 is then formed using an thermal oxidation process or other oxidation process (oxygen plasma treatment or the like) to form the oxide film 23 (FIG. 2C).
이때, 조셉슨 접합면이 이루어질 부분(B)의 실리콘막(22)의 폭이 수 Å 내지 수십 Å이 남을 때까지 산화공정을 진행한다.At this time, the oxidation process is performed until the width of the silicon film 22 of the portion B on which the Josephson bonding surface is to be formed remains.
그리고, 상기 산화 공정을 통하여 형성한 산화막(13)을 불산(HF)과 같은 에칭용액을 사용하여 제거한다.(도 3d)Then, the oxide film 13 formed through the oxidation process is removed using an etching solution such as hydrofluoric acid (HF) (FIG. 3D).
이때, 상기 불산을 사용할 경우, 초전도막(21)과 실리콘막(22)은 전혀 에칭이 되지 않고 산화막(23)만 에칭되어 제거된다.At this time, when the hydrofluoric acid is used, the superconducting film 21 and the silicon film 22 are not etched at all, and only the oxide film 23 is etched and removed.
그 다음, 상기 남아 있는 실리콘막(22)을 마스크로 하여 이온 밀링이나 플라즈마 에칭 등이 식각 공정으로 초전도막(21)을 패터닝 한다.(도 3e)Then, using the remaining silicon film 22 as a mask, ion milling, plasma etching, or the like pattern the superconducting film 21 by an etching process (FIG. 3E).
이렇게 하면, B부분의 초전도의 폭이 수~수십 Å이 되어 조셉슨 접합 계면이 만들어진다.In this way, the width of the superconductivity of the portion B is several tens to several tens of kPa, thereby forming the Josephson junction interface.
그리고, 도 3f와 같이 보호막(24)을 형성하고, 도 3g와 같이 콘택홀(25)을 형성하고, 도 3h와 같이 골드 패드(26)를 형성한다.3F, a protective film 24 is formed, a contact hole 25 is formed as illustrated in FIG. 3G, and a gold pad 26 is formed as illustrated in FIG. 3H.
이상의 설명에서와 같이 본 발명은 실리콘막과 열산화 공정을 이용하여 조셉슨 접합 계면을 형성하기 때문에 신뢰성과 재현성이 뛰어난 디바이스 형성이 가능한 효과가 있다.As described above, according to the present invention, since the Josephson junction interface is formed by using a silicon film and a thermal oxidation process, a device having excellent reliability and reproducibility can be formed.
또한, 본 발명은 대면적 적용이 쉬워 양산 적용 시 그 효과가 매우 크고, 실리콘 막은 수분을 잘 막아주기 때문에 초전도막에 대한 YBCO에 대한 보호막 역할을 하여 특성이 우수한 디바이스 제작이 가능하다.In addition, the present invention is easy to apply a large area, the effect is very large when mass production application, and the silicon film to prevent moisture well, it is possible to manufacture a device having excellent characteristics by acting as a protective film for YBCO for the superconducting film.
이상 설명한 내용을 통해 당업자라면 본 발명의 기술 사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.
따라서, 본 발명의 기술적 범위는 실시예에 기재된 내용으로 한정하는 것이 아니라 특허 청구 범위에 의해서 정해져야 한다.Therefore, the technical scope of the present invention should not be limited to the contents described in the examples, but should be defined by the claims.
Claims (5)
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5667979A (en) * | 1979-11-05 | 1981-06-08 | Mitsubishi Electric Corp | Preparation method of josephson element |
| KR920015652A (en) * | 1991-01-31 | 1992-08-27 | 서주인 | Method for manufacturing high temperature superconducting Josephson junction |
| US6066600A (en) * | 1996-12-06 | 2000-05-23 | Trw Inc. | Method of making high-Tc SSNS and SNS Josephson junction |
| KR20010017668A (en) * | 1999-08-13 | 2001-03-05 | 정명세 | Method of fabricating josephson junction |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5667979A (en) * | 1979-11-05 | 1981-06-08 | Mitsubishi Electric Corp | Preparation method of josephson element |
| KR920015652A (en) * | 1991-01-31 | 1992-08-27 | 서주인 | Method for manufacturing high temperature superconducting Josephson junction |
| US6066600A (en) * | 1996-12-06 | 2000-05-23 | Trw Inc. | Method of making high-Tc SSNS and SNS Josephson junction |
| KR20010017668A (en) * | 1999-08-13 | 2001-03-05 | 정명세 | Method of fabricating josephson junction |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP4227693A4 (en) * | 2020-12-29 | 2024-03-20 | Origin Quantum Computing Technology (Hefei) Co., Ltd | QUANTUM CHIP TEST STRUCTURE AND PRODUCTION PROCESS THEREOF AS WELL AS QUANTUM CHIP TESTING PROCESS AND PRODUCTION PROCESS |
| US12016253B2 (en) | 2020-12-29 | 2024-06-18 | Origin Quantum Computing Technology (Hefei) Co., Ltd | Quantum chip test structure and fabrication method therefor, and test method and fabrication method for quantum chip |
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