KR20030059434A - Semiconductor memory device - Google Patents

Abstract

The present invention relates to a semiconductor memory device,

In order to achieve low power consumption and high speed operation,

An equalizing transistor for equalizing the potential of the memory cell is disposed in the memory cell, an equalizing signal generator for providing an equalizing signal to the equalizing transistor, and a cross-coupled sense amplifier operating in the current mode. Set aside for reading and operate in current mode.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of operating in a current mode capable of low power and high speed operation.

1 shows a part of a semiconductor memory device of the prior art, which shows, as an example, a semiconductor memory device in which four memory cells are composed of two rows and two columns.

As shown, the clock signal CLK and the row select signals X0 and X1 are input to the first word line driver 10 and the second word line driver 20, respectively, so that the row select signals X0 and X1 are provided. Enable a specific word line depending on the state of. When a specific bit line pair BL0 and / BL0 or BL1 or / BL1 is enabled based on the column selection signals Y0 and Y1, the sense amplifier SA1 or SA2 senses and amplifies the data voltage stored in the designated cell. The data is output as data bus line pairs DB and / DB. In contrast, a read / write operation is performed by writing a data value from the data bus line pairs DB and / DB to the designated memory cells CEL1 to CEL4.

The memory cells CEL1 to CEL4 and the sense amplifiers SA1 and SA2 of the conventional semiconductor memory device operate based on a voltage. That is, during the read operation, the detectable potential difference (at least 50 mV) of the pair of bit lines must be amplified to a level close to the power supply voltage, so that the swing width is large, the operating speed is low, and the power consumption is large. In addition, the time until the minimum amplifiable level difference occurs is quite long. In addition, during the write operation, the potential difference between the data bus line pairs DB and / DB should be close to the power supply voltage. Therefore, the operation speed is similarly low and power consumption is large.

Recently, devices such as embedded SRAM installed in various portable devices or smart cards require a semiconductor memory device that requires high power while operating at high speed so that data can be exchanged with other devices at high speed.

It is an object of the present invention to achieve high speed operation and low power consumption by operating a semiconductor memory device in a current mode.

1 is a schematic block diagram showing a part of a semiconductor memory device of the prior art;

2 is a schematic block diagram illustrating a portion of a semiconductor memory device according to an embodiment of the present invention.

3 is a circuit diagram illustrating an equalization signal generator according to an embodiment of the present invention.

4 is a circuit diagram illustrating a memory cell according to an embodiment of the present invention.

5 is a circuit diagram showing a write sense amplifier according to an embodiment of the present invention.

6 is a circuit diagram showing a read sense amplifier according to an embodiment of the present invention.

A semiconductor memory device according to the present invention comprises a plurality of memories having an equalizing transistor for equalizing the potentials of the first switch and the second switch by activation of a first switch, a second switch, and an equalizing signal, which are complementary to each other. Cell; And a plurality of equalizing signal generators outputting an equalizing signal to the equalizing transistor before performing a writing operation of the memory cell, based on an external row selection signal and a writing operation enable signal indicating the start of the writing operation.

The equalizing transistor may be a MOS transistor in which an equalization signal is applied to a gate and a source and a drain are connected to the first switch and the second switch, respectively.

In addition, the memory cell may have a 7 T cell structure.

The method may further include a first current mode cross couple sense amplifier configured to amplify the small potential difference of the pair of bit lines connected to the memory cell in the current mode and output the pair of data lines.

In addition, the first current mode cross-coupled sense amplifier may be configured as a PMOS transistor.

In addition, a second current mode cross-coupled sense amplifier may be further provided for amplifying the small potential difference of the data bus line pair in the current mode and outputting the bit potential pair connected to the memory cell.

In addition, the second current mode cross-coupled sense amplifier may be formed of an NMOS transistor.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a schematic block diagram illustrating a portion of a semiconductor memory device according to an embodiment of the present invention.

Each memory cell NCEL1 to NCEL4 of the semiconductor memory device according to the exemplary embodiment of FIG. 2 includes a new form including an equalizing transistor N43 for equalizing the data potential of each memory cell NCEL1 to NCEL4. Is a memory cell. In addition, a plurality of equalizing signal generators 30 and 40 are provided to provide equalizing signals XEQ0 and XEQ1 to equalizing transistors connected to the same row. In addition, a plurality of write sense amplifiers WSA1 and WSA2 and a plurality of read sense amplifiers RSA1 and RSA2 are separately arranged using a current amplifying cross couple sense amplifier. The plurality of writing column selection signals WY0 and WY1 are input to the plurality of writing sense amplifiers WSA1 and WSA2, respectively. The plurality of read column selection signals RY0 and RY1 are input to the plurality of read sense amplifiers RSA1 and RSA2, respectively. The data bus line pairs WDB and / WDB are commonly connected to the plurality of write sense amplifiers WSA1 and WSA2, and the data bus line pairs to be read out to the plurality of read sense amplifiers RSA1 and RSA2. (RDB, / RDB) are commonly connected.

3 is a circuit diagram illustrating a first equalized signal generator 30 according to an embodiment of the present invention.

Referring to FIG. 3, the first equalized signal generator 30 may select a word line WL0 based on a clock signal CLK, a corresponding row select signal X0, and a write enable signal / WE. Immediately before the normal write operation is performed, equalization signals XEQ0 and XEQ1 for equalizing the data potential difference between the first and third memory cells NCEL1 and NCEL3 connected to the same row are output.

That is, the row select signal X0 is input to the gate of the NMOS transistor N31, and the write operation enable signal / WE is inverted by the inverter and input to the gate of the NMOS transistor N32, thereby enabling the write operation. The equalization signal XEQ0 for equalizing the data potential difference between the memory cells NCEL1 and NCEL3 corresponding to the row selection signal X0 input while the signal / WE is applied to the active low pulse is output as the active high pulse. do.

From the foregoing, the configuration of the second equalized signal generator 40 will be apparent to those skilled in the art.

4 illustrates a first memory cell NCEL1 according to an embodiment of the present invention.

Referring to FIG. 4, the PMOS transistor P41 and the NMOS transistor N41 form a CMOS transistor to operate as a first switch. Similarly, PMOS transistor P42 and NMOS transistor N42 form a CMOS transistor to operate as a second switch. The output of the second switch is connected to the gates of the PMOS transistor P41 and the NMOS transistor N41 and connected to the bit line / BL0 when the word line WL0 is activated, and the gates of the MOS transistor P42 and the NMOS transistor N42. Is connected to the output of the first switch and connected to the bit line / BL0 when the word line WL0 is activated. Thus, the first switch and the second switch operate complementarily to each other.

In addition, the drain and the source of the NMOS transistor N43 which are equalization transistors are connected to the gates of the PMOS transistor P41 and the NMOS transistor N41 and the gates of the MOS transistor P42 and the NMOS transistor N42, respectively, and the NMOS. An equalization signal XEQ0 is applied to the gate of the transistor N43.

Therefore, when the equalizing signal XEQ0 is activated and the NMOS transistor N43 is conducted, the drain and the source of the MOS transistor N43 are connected to the gates of the PMOS transistor P41 and the NMOS transistor N41 and the PMOS transistor P42. The potentials of the gates of the NMOS transistors N42 are equalized (equalized) so that the first switch and the second switch are in an intermediate potential state (V _DD / 2).

At this time, when the word line WL0 is activated and the data voltage is input to the bit line pairs BL0 and / BL0, the first switch and the second switch may quickly rise or fall to a high level or a low level in an intermediate potential state. Can be.

That is, since charge transfer is performed in the equalized state to the intermediate potential in advance, the voltage rises or falls rapidly during the write operation.

FIG. 5 shows a first write sense amplifier WSA1 according to an embodiment of the present invention, and FIG. 6 shows a first read sense amplifier RSA1 according to an embodiment of the present invention.

Referring to FIG. 5, the write sense amplifier WSA1 of the present invention is a current amplifying cross-couple sense amplifier made of an NMOS transistor. Referring to FIG. 6, the read sense amplifier RSA1 of the present invention is a PMOS transistor. A current amplifying cross couple sense amplifier.

As is well known, any sense amplifier can be controlled by controlling the area of the transistor. In particular, the cross-coupled sense amplifier is known to operate in a voltage mode when an input is applied to a gate and in a current mode when the input is applied to a drain or a source.

Hereinafter, a reading operation of the cross couple sense amplifier of the present invention will be described with reference to FIG.

When the read column select signal RY0 is activated, the threshold voltages (hereinafter, Vth) of the PMOS transistor P63 and the PMOS transistor P64 are applied to the gate of the PMOS transistor P61 and the gate of the PMOS transistor P62. Initially, the bit line pairs BL0 and / BL0 are both precharged to V _DD . When the read operation is started in this state, a small voltage difference DELTA v occurs in the bit line pairs BL0 and / BL0 due to the data potential difference stored in the designated memory cell. For example, the bit line BL0 remains as V _DD , and the bit line / BL0 becomes V _DD -Δv. This voltage is connected to the source of the PMOS transistor P61 and the source of the PMOS transistor P62. By adjusting the transistor sizing, the threshold voltages of the PMOS transistors P63 and P64 are set lower than the threshold voltages of the PMOS transistors P61 and P62. Thus, the PMOS transistors P61 and P62 remain weakly ON and transfer the voltage of the bit line pair to the source. After such a predetermined time, the current driving capability of the PMOS transistor P61 to which the voltage of the bit line BL0 having the drain voltage is higher is increased, thereby turning off the PMOS transistor P62. Thus, after a certain period of time, the drain of the PMOS transistor (P61) is the voltage V _DD, the voltage of the PMOS transistor (P62) is the Vth (P64) + △ v. Therefore, the small voltage difference can be amplified in the current mode with low power consumption.

In the same manner, the first writing sense amplifier WSA1 is driven in the current mode.

Referring to FIG. 5, initially, the bit lines BL0 and / BL0 are both precharged to V _DD , and the write operation is started to activate the write column select signal WY0. As shown, the writing data bus line WDB is connected to the drain of the NMOS transistor N53, and the writing data bus line / WDB is connected to the drain of the NMOS transistor N54. If a small voltage difference occurs in the data bus line pair, as described above, a large voltage difference of the bit line pair is made in a current mode that consumes low power in the same principle as the read operation.

The voltage difference between the bit line pairs is rapidly written to the memory cells NCEL1 to NCEL4 equalized to the intermediate potential. Thus, high speed operation and low power consumption are achieved.

According to the present invention, the memory cell is equalized by the equalized signal, so that the writing operation can be performed at high speed.

By configuring a cross-coupled sense amplifier driven in the current mode separately for reading and writing, a small current difference can be amplified to a large voltage difference while consuming low power.

Therefore, the memory device can operate at high speed and low power, and can be embedded with other devices to provide an integrated circuit having excellent performance.

Claims (7)

A plurality of memory cells having equalization means for equalizing the potentials of the first switch means and the second switch means by activation of a first switch means, a second switch means, and an equalizing signal complementary to each other; And A plurality of equalizing signal generating means for outputting said equalizing signal to said equalizing means before performing a write operation of said memory cell, based on an external row selection signal and a write operation enable signal indicating the start of a write operation; A semiconductor memory device, characterized in that. The method of claim 1, And said equalizing means is a MOS transistor in which said equalizing signal is applied to a gate and a source and a drain are connected to said first switch means and said second switch means, respectively. The method of claim 1, And the memory cell has a 7 T cell structure. The method according to any one of claims 1 to 3, And a first current mode cross-coupled sense amplifier which amplifies the small potential difference between the bit line pairs connected to the memory cells in the current mode and outputs the data signal to the data bus line pairs. The method of claim 4, wherein And the first current mode cross-coupled sense amplifier comprises a PMOS transistor. The method of claim 5, And a second current mode cross couple sense amplifier which amplifies the small potential difference between the data bus line pairs in a current mode and outputs the bit potential pairs connected to the memory cells. The method of claim 6, And the second current mode cross-coupled sense amplifier comprises an NMOS transistor.